[bea49c9] | 1 | /* The header file is generated by make_header.py from SYS2.json */ |
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| 2 | /* Current script's version can be found at: */ |
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| 3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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| 4 | |
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| 5 | /* |
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| 6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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| 7 | * |
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| 8 | * Czech Technical University in Prague |
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| 9 | * Zikova 1903/4 |
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| 10 | * 166 36 Praha 6 |
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| 11 | * Czech Republic |
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| 12 | * |
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| 13 | * All rights reserved. |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions are met: |
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| 17 | * |
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| 18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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| 19 | * list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 21 | * this list of conditions and the following disclaimer in the documentation |
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| 22 | * and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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| 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | * The views and conclusions contained in the software and documentation are those |
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| 36 | * of the authors and should not be interpreted as representing official policies, |
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| 37 | * either expressed or implied, of the FreeBSD Project. |
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| 38 | */ |
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| 39 | #ifndef LIBBSP_ARM_tms570_SYS2 |
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| 40 | #define LIBBSP_ARM_tms570_SYS2 |
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| 41 | |
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| 42 | #include <bsp/utility.h> |
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| 43 | |
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| 44 | typedef struct{ |
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| 45 | uint32_t PLLCTL3; /*PLL Control Register 3*/ |
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| 46 | uint8_t reserved1 [4]; |
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| 47 | uint32_t STCCLKDIV; /*CPU Logic BIST Clock Divider*/ |
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| 48 | uint8_t reserved2 [24]; |
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| 49 | uint32_t ECPCNTL; /*ECP Control Register*/ |
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| 50 | uint8_t reserved3 [20]; |
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| 51 | uint32_t CLK2CNTRL; /*Clock 2 Control Register*/ |
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| 52 | uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/ |
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| 53 | uint8_t reserved4 [44]; |
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| 54 | uint32_t CLKSLIP; /*Clock Slip Register*/ |
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| 55 | uint8_t reserved5 [120]; |
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| 56 | uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/ |
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| 57 | uint32_t DIEDL_REG0; /*Die Identification Register*/ |
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| 58 | uint32_t DIEDH_REG1; /*Die Identification Register*/ |
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| 59 | uint32_t DIEDL_REG2; /*Die Identification Register*/ |
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| 60 | uint32_t DIEDH_REG3; /*Die Identification Register*/ |
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| 61 | } tms570_sys2_t; |
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| 62 | |
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| 63 | |
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| 64 | /*---------------------TMS570_SYS2PLLCTL3---------------------*/ |
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| 65 | /* field: ODPLL2 - Internal PLL Output Divider */ |
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| 66 | #define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) |
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| 67 | #define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) |
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| 68 | #define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) |
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| 69 | |
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| 70 | /* field: PLLDIV2 - PLL2 Output Clock Divider */ |
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| 71 | #define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) |
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| 72 | #define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) |
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| 73 | #define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) |
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| 74 | |
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| 75 | /* field: REFCLKDIV2 - REFCLKDIV2 */ |
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| 76 | #define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) |
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| 77 | #define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) |
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| 78 | #define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) |
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| 79 | |
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| 80 | /* field: PLLMUL2 - PLL2 Multiplication Factor */ |
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| 81 | #define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) |
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| 82 | #define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) |
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| 83 | #define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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| 84 | |
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| 85 | |
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| 86 | /*--------------------TMS570_SYS2STCCLKDIV--------------------*/ |
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| 87 | /* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */ |
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| 88 | #define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26) |
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| 89 | #define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26) |
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| 90 | #define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) |
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| 91 | |
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| 92 | |
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| 93 | /*---------------------TMS570_SYS2ECPCNTL---------------------*/ |
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| 94 | /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ |
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| 95 | #define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24) |
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| 96 | |
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| 97 | /* field: ECPCOS - ECP continue on suspend. */ |
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| 98 | #define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23) |
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| 99 | |
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| 100 | /* field: ECPINSEL - Select ECP input clock source. */ |
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| 101 | #define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) |
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| 102 | #define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) |
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| 103 | #define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) |
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| 104 | |
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| 105 | /* field: ECPDIV - ECP divider value. */ |
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| 106 | #define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) |
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| 107 | #define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) |
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| 108 | #define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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| 109 | |
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| 110 | |
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| 111 | /*--------------------TMS570_SYS2CLK2CNTRL--------------------*/ |
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| 112 | /* field: VCLK3R - VBUS clock3 ratio. */ |
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| 113 | #define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3) |
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| 114 | #define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 115 | #define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 116 | |
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| 117 | |
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| 118 | /*--------------------TMS570_SYS2VCLKACON1--------------------*/ |
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| 119 | /* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */ |
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| 120 | #define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26) |
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| 121 | #define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26) |
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| 122 | #define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) |
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| 123 | |
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| 124 | /* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */ |
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| 125 | #define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20) |
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| 126 | |
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| 127 | /* field: VCLKA4S - Peripheral asynchronous clock4 source. */ |
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| 128 | #define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19) |
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| 129 | #define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19) |
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| 130 | #define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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| 131 | |
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| 132 | /* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */ |
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| 133 | #define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10) |
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| 134 | #define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10) |
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| 135 | #define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) |
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| 136 | |
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| 137 | /* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */ |
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| 138 | #define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4) |
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| 139 | |
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| 140 | /* field: VCLKA3S - Peripheral asynchronous clock3 source. */ |
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| 141 | #define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3) |
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| 142 | #define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 143 | #define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 144 | |
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| 145 | |
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| 146 | /*---------------------TMS570_SYS2CLKSLIP---------------------*/ |
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| 147 | /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ |
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| 148 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) |
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| 149 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) |
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| 150 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) |
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| 151 | |
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| 152 | /* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ |
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| 153 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) |
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| 154 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 155 | #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 156 | |
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| 157 | |
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| 158 | /*-------------------TMS570_SYS2EFC_CTLREG-------------------*/ |
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| 159 | /* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */ |
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| 160 | #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3) |
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| 161 | #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 162 | #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 163 | |
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| 164 | |
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| 165 | /*-------------------TMS570_SYS2DIEDL_REG0-------------------*/ |
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| 166 | /* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */ |
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| 167 | #define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31) |
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| 168 | #define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 169 | #define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 170 | |
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| 171 | |
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| 172 | |
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| 173 | #endif /* LIBBSP_ARM_tms570_SYS2 */ |
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