| 1 | /* The header file is generated by make_header.py from SYS.json */ |
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| 2 | /* Current script's version can be found at: */ |
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| 3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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| 4 | |
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| 5 | /* |
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| 6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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| 7 | * |
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| 8 | * Czech Technical University in Prague |
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| 9 | * Zikova 1903/4 |
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| 10 | * 166 36 Praha 6 |
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| 11 | * Czech Republic |
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| 12 | * |
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| 13 | * All rights reserved. |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions are met: |
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| 17 | * |
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| 18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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| 19 | * list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 21 | * this list of conditions and the following disclaimer in the documentation |
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| 22 | * and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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| 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | * The views and conclusions contained in the software and documentation are those |
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| 36 | * of the authors and should not be interpreted as representing official policies, |
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| 37 | * either expressed or implied, of the FreeBSD Project. |
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| 38 | */ |
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| 39 | #ifndef LIBBSP_ARM_TMS570_SYS1 |
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| 40 | #define LIBBSP_ARM_TMS570_SYS1 |
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| 41 | |
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| 42 | #include <bsp/utility.h> |
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| 43 | |
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| 44 | typedef struct{ |
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| 45 | uint32_t SYSPC1; /*SYS Pin Control Register 1*/ |
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| 46 | uint32_t SYSPC2; /*SYS Pin Control Register 2*/ |
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| 47 | uint32_t SYSPC3; /*SYS Pin Control Register 3*/ |
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| 48 | uint32_t SYSPC4; /*SYS Pin Control Register 4*/ |
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| 49 | uint32_t SYSPC5; /*SYS Pin Control Register 5*/ |
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| 50 | uint32_t SYSPC6; /*SYS Pin Control Register 6*/ |
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| 51 | uint32_t SYSPC7; /*SYS Pin Control Register 7*/ |
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| 52 | uint32_t SYSPC8; /*SYS Pin Control Register 8*/ |
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| 53 | uint32_t SYSPC9; /*SYS Pin Control Register 9*/ |
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| 54 | uint8_t reserved1 [12]; |
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| 55 | uint32_t CSDIS; /*Clock Source Disable Register*/ |
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| 56 | uint32_t CSDISSET; /*Clock Source Disable Set Register*/ |
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| 57 | uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ |
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| 58 | uint32_t CDDIS; /*Clock Domain Disable Register*/ |
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| 59 | uint32_t CDDISSET; /*Clock Domain Disable Set Register*/ |
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| 60 | uint32_t CDDISCLR; /*Clock Domain Disable Clear Register*/ |
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| 61 | uint32_t GHVSRC; /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/ |
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| 62 | uint32_t VCLKASRC; /*Peripheral Asynchronous Clock Source Register*/ |
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| 63 | uint32_t RCLKSRC; /*RTI Clock Source Register*/ |
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| 64 | uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ |
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| 65 | uint32_t MSTGCR; /*Memory Self-Test Global Control Register*/ |
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| 66 | uint32_t MINITGCR; /*Memory Hardware Initialization Global Control Register*/ |
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| 67 | uint32_t MSIENA; /*Memory Self-Test/Initialization Enable Register*/ |
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| 68 | uint8_t reserved2 [4]; |
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| 69 | uint32_t MSTCGSTAT; /*MSTC Global Status Register*/ |
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| 70 | uint32_t MINISTAT; /*Memory Hardware Initialization Status Register*/ |
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| 71 | uint32_t PLLCTL1; /*PLL Control Register 1*/ |
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| 72 | uint32_t PLLCTL2; /*PLL Control Register 2*/ |
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| 73 | uint32_t SYSPC10; /*SYS Pin Control Register 10*/ |
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| 74 | uint32_t DIEIDL; /*Die Identification Register, Lower Word*/ |
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| 75 | uint32_t DIEIDH; /*Die Identification Register, Upper Word*/ |
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| 76 | uint8_t reserved3 [4]; |
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| 77 | uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ |
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| 78 | uint32_t CLKTEST; /*Clock Test Register*/ |
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| 79 | uint32_t DFTCTRLREG1; /*DFT Control Register*/ |
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| 80 | uint32_t DFTCTRLREG2; /*DFT Control Register 2*/ |
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| 81 | uint8_t reserved4 [8]; |
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| 82 | uint32_t GPREG1; /*General Purpose Register*/ |
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| 83 | uint8_t reserved5 [4]; |
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| 84 | uint32_t IMPFASTS; /*Imprecise Fault Status Register*/ |
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| 85 | uint32_t IMPFTADD; /*Imprecise Fault Write Address Register*/ |
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| 86 | uint32_t SSIR1; /*System Software Interrupt Request 1 Register*/ |
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| 87 | uint32_t SSIR2; /*System Software Interrupt Request 2 Register*/ |
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| 88 | uint32_t SSIR3; /*System Software Interrupt Request 3 Register*/ |
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| 89 | uint32_t SSIR4; /*System Software Interrupt Request 4 Register*/ |
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| 90 | uint32_t RAMGCR; /*RAM Control Register*/ |
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| 91 | uint32_t BMMCR1; /*Bus Matrix Module Control Register 1*/ |
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| 92 | uint8_t reserved6 [4]; |
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| 93 | uint32_t CPURSTCR; /*CPU Reset Control Register*/ |
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| 94 | uint32_t CLKCNTL; /*Clock Control Register*/ |
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| 95 | uint32_t ECPCNTL; /*ECP Control Register*/ |
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| 96 | uint8_t reserved7 [4]; |
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| 97 | uint32_t DEVCR1; /*DEV Parity Control Register 1*/ |
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| 98 | uint32_t SYSECR; /*System Exception Control Register*/ |
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| 99 | uint32_t SYSESR; /*System Exception Status Register*/ |
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| 100 | uint32_t SYSTASR; /*System Test Abort Status Register*/ |
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| 101 | uint32_t GLBSTAT; /*Global Status Register*/ |
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| 102 | uint32_t DEVID; /*Device Identification Register*/ |
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| 103 | uint32_t SSIVEC; /*Software Interrupt Vector Register*/ |
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| 104 | uint32_t SSIF; /*System Software Interrupt Flag Register*/ |
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| 105 | } tms570_sys1_t; |
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| 106 | |
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| 107 | |
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| 108 | /*---------------------TMS570_SYS1_SYSPCx---------------------*/ |
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| 109 | /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ |
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| 110 | #define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0) |
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| 111 | |
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| 112 | |
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| 113 | /*---------------------TMS570_SYS1_CSDIS---------------------*/ |
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| 114 | /* field: CLKSROFF - Clock source[7-3] off. */ |
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| 115 | #define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7) |
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| 116 | #define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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| 117 | #define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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| 118 | |
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| 119 | /* field: CLKSROFF - Clock source[1-0] off. */ |
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| 120 | #define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 1) |
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| 121 | #define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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| 122 | #define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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| 123 | |
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| 124 | |
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| 125 | /*--------------------TMS570_SYS1_CSDISSET--------------------*/ |
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| 126 | /* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */ |
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| 127 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7) |
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| 128 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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| 129 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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| 130 | |
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| 131 | /* field: SETCLKSR_OFF - Set clock source[1-0] to the disabled state. */ |
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| 132 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 1) |
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| 133 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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| 134 | #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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| 135 | |
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| 136 | |
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| 137 | /*--------------------TMS570_SYS1_CSDISCLR--------------------*/ |
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| 138 | /* field: CLRCLKSR_OFF - Enables clock source[7-3]. */ |
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| 139 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7) |
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| 140 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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| 141 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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| 142 | |
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| 143 | /* field: CLRCLKSR_OFF - Enables clock source[1-0]. */ |
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| 144 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 1) |
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| 145 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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| 146 | #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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| 147 | |
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| 148 | |
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| 149 | /*---------------------TMS570_SYS1_CDDIS---------------------*/ |
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| 150 | /* field: VCLKAOFF - VCLKA[4-3] domain off. */ |
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| 151 | #define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11) |
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| 152 | #define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) |
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| 153 | #define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) |
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| 154 | |
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| 155 | /* field: VCLK3OFF - VCLK3 domain off. */ |
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| 156 | #define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8) |
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| 157 | |
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| 158 | /* field: RTICLK1OFF - RTICLK1 domain off. */ |
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| 159 | #define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6) |
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| 160 | |
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| 161 | /* field: VCLKAOFF - VCLKA[2-1] domain off. */ |
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| 162 | #define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5) |
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| 163 | #define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,4, 5) |
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| 164 | #define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) |
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| 165 | |
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| 166 | /* field: VCLK2OFF - VCLK2 domain off. */ |
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| 167 | #define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3) |
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| 168 | |
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| 169 | /* field: VCLKPOFF - VCLK_periph domain off. */ |
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| 170 | #define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2) |
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| 171 | |
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| 172 | /* field: HCLKOFF - HCLK and VCLK_sys domains off. */ |
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| 173 | #define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1) |
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| 174 | |
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| 175 | /* field: GCLKOFF - GCLK domain off. */ |
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| 176 | #define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0) |
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| 177 | |
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| 178 | |
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| 179 | /*--------------------TMS570_SYS1_CDDISSET--------------------*/ |
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| 180 | /* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */ |
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| 181 | #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11) |
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| 182 | #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11) |
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| 183 | #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) |
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| 184 | |
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| 185 | /* field: SETVCLK3OFF - Set VCLK3 domain. */ |
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| 186 | #define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8) |
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| 187 | |
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| 188 | /* field: SETRTI1CLKOFF - Set RTICLK1 domain. */ |
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| 189 | #define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6) |
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| 190 | |
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| 191 | /* field: SETTVCLKA2OFF - Set VCLKA2 domain. */ |
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| 192 | #define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5) |
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| 193 | |
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| 194 | /* field: SETVCLKA1OFF - Set VCLKA1 domain. */ |
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| 195 | #define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4) |
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| 196 | |
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| 197 | /* field: SETVCLK2OFF - Set VCLK2 domain. */ |
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| 198 | #define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3) |
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| 199 | |
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| 200 | /* field: SETVCLKPOFF - Set VCLK_periph domain. */ |
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| 201 | #define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2) |
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| 202 | |
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| 203 | /* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */ |
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| 204 | #define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1) |
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| 205 | |
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| 206 | /* field: SETGCLKOFF - Set GCLK domain. */ |
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| 207 | #define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0) |
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| 208 | |
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| 209 | |
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| 210 | /*--------------------TMS570_SYS1_CDDISCLR--------------------*/ |
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| 211 | /* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */ |
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| 212 | #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11) |
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| 213 | #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) |
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| 214 | #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) |
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| 215 | |
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| 216 | /* field: Reserved - Reserved */ |
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| 217 | #define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9) |
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| 218 | |
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| 219 | /* field: CLRVCLK3OFF - Clear VCLK3 domain. */ |
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| 220 | #define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8) |
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| 221 | |
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| 222 | /* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */ |
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| 223 | #define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6) |
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| 224 | |
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| 225 | /* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */ |
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| 226 | #define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5) |
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| 227 | |
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| 228 | /* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */ |
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| 229 | #define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4) |
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| 230 | |
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| 231 | /* field: CLRVCLK2OFF - Clear VCLK2 domain. */ |
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| 232 | #define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3) |
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| 233 | |
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| 234 | /* field: CLRVCLKPOFF - CLRVCLKPOFF */ |
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| 235 | #define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2) |
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| 236 | |
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| 237 | /* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */ |
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| 238 | #define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1) |
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| 239 | |
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| 240 | /* field: CLRGCLKOFF - Clear GCLK domain. */ |
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| 241 | #define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0) |
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| 242 | |
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| 243 | |
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| 244 | /*---------------------TMS570_SYS1_GHVSRC---------------------*/ |
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| 245 | /* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */ |
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| 246 | #define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27) |
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| 247 | #define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27) |
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| 248 | #define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
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| 249 | |
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| 250 | /* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */ |
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| 251 | #define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19) |
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| 252 | #define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19) |
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| 253 | #define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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| 254 | |
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| 255 | /* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */ |
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| 256 | #define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3) |
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| 257 | #define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 258 | #define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 259 | |
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| 260 | |
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| 261 | /*--------------------TMS570_SYS1_VCLKASRC--------------------*/ |
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| 262 | /* field: VCLKA2S - Peripheral asynchronous clock2 source. */ |
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| 263 | #define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11) |
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| 264 | #define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11) |
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| 265 | #define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) |
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| 266 | |
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| 267 | /* field: VCLKA1S - Peripheral asynchronous clock1 source. */ |
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| 268 | #define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3) |
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| 269 | #define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 270 | #define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 271 | |
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| 272 | |
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| 273 | /*--------------------TMS570_SYS1_RCLKSRC--------------------*/ |
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| 274 | /* field: RTI1DIV - RTI clock1 Divider. */ |
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| 275 | #define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9) |
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| 276 | #define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9) |
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| 277 | #define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) |
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| 278 | |
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| 279 | /* field: RTI1SRC - RTI clock1 source. */ |
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| 280 | #define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3) |
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| 281 | #define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 282 | #define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 283 | |
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| 284 | |
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| 285 | /*--------------------TMS570_SYS1_CSVSTAT--------------------*/ |
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| 286 | /* field: CLKSRV - Clock source[7-0] valid. */ |
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| 287 | #define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7) |
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| 288 | #define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7) |
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| 289 | #define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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| 290 | |
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| 291 | /* field: CLKSR - Clock source[1-0] valid. */ |
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| 292 | #define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1) |
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| 293 | #define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1) |
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| 294 | #define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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| 295 | |
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| 296 | |
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| 297 | /*---------------------TMS570_SYS1_MSTGCR---------------------*/ |
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| 298 | /* field: ROM_DIV - Prescaler divider bits for ROM clock source. */ |
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| 299 | #define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9) |
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| 300 | #define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9) |
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| 301 | #define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) |
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| 302 | |
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| 303 | /* field: MSTGENA - Memory self-test controller global enable key */ |
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| 304 | #define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3) |
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| 305 | #define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 306 | #define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 307 | |
|---|
| 308 | |
|---|
| 309 | /*--------------------TMS570_SYS1_MINITGCR--------------------*/ |
|---|
| 310 | /* field: MINITGENA - Memory hardware initialization global enable key. */ |
|---|
| 311 | #define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3) |
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| 312 | #define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 313 | #define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 314 | |
|---|
| 315 | |
|---|
| 316 | /*---------------------TMS570_SYS1_MSIENA---------------------*/ |
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| 317 | /* field: MSIENA - PBIST controller and memory initialization enable register. */ |
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| 318 | /* Whole 32 bits */ |
|---|
| 319 | |
|---|
| 320 | /*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/ |
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| 321 | /* field: MINIDONE - Memory hardware initialization complete status. */ |
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| 322 | #define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8) |
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| 323 | |
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| 324 | /* field: MSTDONE - Memory self-test run complete status. */ |
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| 325 | #define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0) |
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| 326 | |
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| 327 | |
|---|
| 328 | /*--------------------TMS570_SYS1_MINISTAT--------------------*/ |
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| 329 | /* field: MIDONE - Memory hardware initialization status bit. */ |
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| 330 | /* Whole 32 bits */ |
|---|
| 331 | |
|---|
| 332 | /*--------------------TMS570_SYS1_PLLCTL1--------------------*/ |
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| 333 | /* field: ROS - Reset on PLL Slip */ |
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| 334 | #define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31) |
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| 335 | |
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| 336 | /* field: MASK_SLIP - Mask detection of PLL slip */ |
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| 337 | #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) |
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| 338 | #define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) |
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| 339 | #define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) |
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| 340 | |
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| 341 | /* field: PLLDIV - PLL Output Clock Divider */ |
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| 342 | #define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) |
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| 343 | #define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) |
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| 344 | #define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) |
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| 345 | |
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| 346 | /* field: ROF - Reset on Oscillator Fail */ |
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| 347 | #define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23) |
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| 348 | |
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| 349 | /* field: REFCLKDIV - Reference Clock Divider */ |
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| 350 | #define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) |
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| 351 | #define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) |
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| 352 | #define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) |
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| 353 | |
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| 354 | /* field: PLLMUL - PLL Multiplication Factor */ |
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| 355 | #define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) |
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| 356 | #define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) |
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| 357 | #define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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| 358 | |
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| 359 | |
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| 360 | /*--------------------TMS570_SYS1_PLLCTL2--------------------*/ |
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| 361 | /* field: FMENA - Frequency Modulation Enable. */ |
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| 362 | #define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31) |
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| 363 | |
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| 364 | /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ |
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| 365 | #define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) |
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| 366 | #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) |
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| 367 | #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) |
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| 368 | |
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| 369 | /* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ |
|---|
| 370 | #define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) |
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| 371 | #define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) |
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| 372 | #define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) |
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| 373 | |
|---|
| 374 | /* field: ODPLL - Internal PLL Output Divider. */ |
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| 375 | #define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) |
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| 376 | #define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) |
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| 377 | #define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) |
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| 378 | |
|---|
| 379 | /* field: SPR_AMOUNT - Spreading Amount. */ |
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| 380 | #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) |
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| 381 | #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) |
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| 382 | #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) |
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| 383 | |
|---|
| 384 | |
|---|
| 385 | /*--------------------TMS570_SYS1_SYSPC10--------------------*/ |
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| 386 | /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */ |
|---|
| 387 | #define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0) |
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| 388 | |
|---|
| 389 | |
|---|
| 390 | /*---------------------TMS570_SYS1_DIEIDL---------------------*/ |
|---|
| 391 | /* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */ |
|---|
| 392 | #define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31) |
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| 393 | #define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31) |
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| 394 | #define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31) |
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| 395 | |
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| 396 | /* field: WAFER - These read only bits contain the wafer number of the device. */ |
|---|
| 397 | #define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21) |
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| 398 | #define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21) |
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| 399 | #define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) |
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| 400 | |
|---|
| 401 | /* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */ |
|---|
| 402 | #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15) |
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| 403 | #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15) |
|---|
| 404 | #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
|---|
| 405 | |
|---|
| 406 | /* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */ |
|---|
| 407 | #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7) |
|---|
| 408 | #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7) |
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| 409 | #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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| 410 | |
|---|
| 411 | |
|---|
| 412 | /*---------------------TMS570_SYS1_DIEIDH---------------------*/ |
|---|
| 413 | /* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */ |
|---|
| 414 | #define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13) |
|---|
| 415 | #define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13) |
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| 416 | #define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13) |
|---|
| 417 | |
|---|
| 418 | |
|---|
| 419 | /*-------------------TMS570_SYS1_LPOMONCTL-------------------*/ |
|---|
| 420 | /* field: BIAS_ENABLE - Bias enable. */ |
|---|
| 421 | #define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) |
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| 422 | |
|---|
| 423 | /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ |
|---|
| 424 | #define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) |
|---|
| 425 | |
|---|
| 426 | /* field: HFTRIM - High frequency oscillator trim value. */ |
|---|
| 427 | #define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) |
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| 428 | #define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) |
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| 429 | #define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) |
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| 430 | |
|---|
| 431 | |
|---|
| 432 | /*--------------------TMS570_SYS1_CLKTEST--------------------*/ |
|---|
| 433 | /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ |
|---|
| 434 | #define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) |
|---|
| 435 | |
|---|
| 436 | /* field: RANGEDETCTRL - Range detection control. */ |
|---|
| 437 | #define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25) |
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| 438 | |
|---|
| 439 | /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ |
|---|
| 440 | #define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) |
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| 441 | |
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| 442 | /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ |
|---|
| 443 | #define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) |
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| 444 | #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) |
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| 445 | #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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| 446 | |
|---|
| 447 | /* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */ |
|---|
| 448 | #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11) |
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| 449 | #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11) |
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| 450 | #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) |
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| 451 | |
|---|
| 452 | /* field: SEL_ECP_PIN - ECLK pin clock source select */ |
|---|
| 453 | #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3) |
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| 454 | #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 455 | #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 456 | |
|---|
| 457 | |
|---|
| 458 | /*------------------TMS570_SYS1_DFTCTRLREG1------------------*/ |
|---|
| 459 | /* field: DFTWRITE - DFT logic access. */ |
|---|
| 460 | #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13) |
|---|
| 461 | #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13) |
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| 462 | #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) |
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| 463 | |
|---|
| 464 | /* field: DFTREAD - DFT logic access. */ |
|---|
| 465 | #define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9) |
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| 466 | #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9) |
|---|
| 467 | #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) |
|---|
| 468 | |
|---|
| 469 | /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ |
|---|
| 470 | #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) |
|---|
| 471 | #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) |
|---|
| 472 | #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
|---|
| 473 | |
|---|
| 474 | |
|---|
| 475 | /*------------------TMS570_SYS1_DFTCTRLREG2------------------*/ |
|---|
| 476 | /* field: IMPDF - DFT Implementation defined bits. */ |
|---|
| 477 | #define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31) |
|---|
| 478 | #define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31) |
|---|
| 479 | #define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) |
|---|
| 480 | |
|---|
| 481 | /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ |
|---|
| 482 | #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) |
|---|
| 483 | #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) |
|---|
| 484 | #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
|---|
| 485 | |
|---|
| 486 | |
|---|
| 487 | /*---------------------TMS570_SYS1_GPREG1---------------------*/ |
|---|
| 488 | /* field: EMIF_FUNC - Enable EMIF functions to be output. */ |
|---|
| 489 | #define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31) |
|---|
| 490 | |
|---|
| 491 | /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ |
|---|
| 492 | #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) |
|---|
| 493 | #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) |
|---|
| 494 | #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) |
|---|
| 495 | |
|---|
| 496 | /* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ |
|---|
| 497 | #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) |
|---|
| 498 | #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) |
|---|
| 499 | #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
|---|
| 500 | |
|---|
| 501 | /* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ |
|---|
| 502 | #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) |
|---|
| 503 | #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) |
|---|
| 504 | #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
|---|
| 505 | |
|---|
| 506 | |
|---|
| 507 | /*--------------------TMS570_SYS1_IMPFASTS--------------------*/ |
|---|
| 508 | /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ |
|---|
| 509 | #define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0) |
|---|
| 510 | |
|---|
| 511 | |
|---|
| 512 | /*--------------------TMS570_SYS1_IMPFTADD--------------------*/ |
|---|
| 513 | /* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */ |
|---|
| 514 | /* Whole 32 bits */ |
|---|
| 515 | |
|---|
| 516 | /*---------------------TMS570_SYS1_SSIRx---------------------*/ |
|---|
| 517 | /* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */ |
|---|
| 518 | #define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15) |
|---|
| 519 | #define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15) |
|---|
| 520 | #define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
|---|
| 521 | |
|---|
| 522 | /* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */ |
|---|
| 523 | #define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7) |
|---|
| 524 | #define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7) |
|---|
| 525 | #define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
|---|
| 526 | |
|---|
| 527 | |
|---|
| 528 | /*---------------------TMS570_SYS1_RAMGCR---------------------*/ |
|---|
| 529 | /* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */ |
|---|
| 530 | #define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19) |
|---|
| 531 | #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19) |
|---|
| 532 | #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
|---|
| 533 | |
|---|
| 534 | /* field: WST_AENA0 - eSRAM data phase wait state enable bit. */ |
|---|
| 535 | #define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2) |
|---|
| 536 | |
|---|
| 537 | /* field: WST_DENA0 - eSRAM data phase wait state enable bit. */ |
|---|
| 538 | #define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0) |
|---|
| 539 | |
|---|
| 540 | |
|---|
| 541 | /*---------------------TMS570_SYS1_BMMCR1---------------------*/ |
|---|
| 542 | /* field: MEMSW - Memory swap key. */ |
|---|
| 543 | #define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3) |
|---|
| 544 | #define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3) |
|---|
| 545 | #define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
|---|
| 546 | |
|---|
| 547 | |
|---|
| 548 | /*--------------------TMS570_SYS1_CPURSTCR--------------------*/ |
|---|
| 549 | /* field: CPU_RESET - CPU Reset. */ |
|---|
| 550 | #define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0) |
|---|
| 551 | |
|---|
| 552 | |
|---|
| 553 | /*--------------------TMS570_SYS1_CLKCNTL--------------------*/ |
|---|
| 554 | /* field: VCLK2R - VBUS clock2 ratio. */ |
|---|
| 555 | #define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27) |
|---|
| 556 | #define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27) |
|---|
| 557 | #define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
|---|
| 558 | |
|---|
| 559 | /* field: VCLKR - VBUS clock ratio. */ |
|---|
| 560 | #define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19) |
|---|
| 561 | #define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19) |
|---|
| 562 | #define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
|---|
| 563 | |
|---|
| 564 | /* field: PENA - Peripheral enable bit. */ |
|---|
| 565 | #define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8) |
|---|
| 566 | |
|---|
| 567 | |
|---|
| 568 | /*--------------------TMS570_SYS1_ECPCNTL--------------------*/ |
|---|
| 569 | /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ |
|---|
| 570 | #define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24) |
|---|
| 571 | |
|---|
| 572 | /* field: ECPCOS - ECP continue on suspend. */ |
|---|
| 573 | #define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23) |
|---|
| 574 | |
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| 575 | /* field: ECPINSEL - Select ECP input clock source. */ |
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| 576 | #define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) |
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| 577 | #define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) |
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| 578 | #define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) |
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| 579 | |
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| 580 | /* field: ECPDIV - ECP divider value. */ |
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| 581 | #define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) |
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| 582 | #define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) |
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| 583 | #define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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| 584 | |
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| 585 | |
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| 586 | /*---------------------TMS570_SYS1_DEVCR1---------------------*/ |
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| 587 | /* field: DEVPARSEL - Device parity select bit key. */ |
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| 588 | #define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3) |
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| 589 | #define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 590 | #define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 591 | |
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| 592 | |
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| 593 | /*---------------------TMS570_SYS1_SYSECR---------------------*/ |
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| 594 | /* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */ |
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| 595 | #define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15) |
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| 596 | #define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15) |
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| 597 | #define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) |
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| 598 | |
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| 599 | |
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| 600 | /*---------------------TMS570_SYS1_SYSESR---------------------*/ |
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| 601 | /* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */ |
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| 602 | #define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15) |
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| 603 | |
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| 604 | /* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */ |
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| 605 | #define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14) |
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| 606 | |
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| 607 | /* field: WDRST - Watchdog reset flag. */ |
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| 608 | #define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13) |
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| 609 | |
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| 610 | /* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */ |
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| 611 | #define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5) |
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| 612 | |
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| 613 | /* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */ |
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| 614 | #define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4) |
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| 615 | |
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| 616 | /* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */ |
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| 617 | #define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3) |
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| 618 | |
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| 619 | /* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */ |
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| 620 | #define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0) |
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| 621 | |
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| 622 | |
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| 623 | /*--------------------TMS570_SYS1_SYSTASR--------------------*/ |
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| 624 | /* field: EFUSE_Abort - Test Abort status flag. */ |
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| 625 | #define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4) |
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| 626 | #define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4) |
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| 627 | #define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) |
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| 628 | |
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| 629 | |
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| 630 | /*--------------------TMS570_SYS1_GLBSTAT--------------------*/ |
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| 631 | /* field: FBSLIP - PLL over cycle slip detection. */ |
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| 632 | #define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9) |
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| 633 | |
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| 634 | /* field: RFSLIP - PLL under cycle slip detection. */ |
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| 635 | #define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8) |
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| 636 | |
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| 637 | /* field: OSCFAIL - Oscillator fail flag bit. */ |
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| 638 | #define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0) |
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| 639 | |
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| 640 | |
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| 641 | /*---------------------TMS570_SYS1_DEVID---------------------*/ |
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| 642 | /* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */ |
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| 643 | #define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31) |
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| 644 | |
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| 645 | /* field: TECH - These bits define the process technology by which the device was manufactured. */ |
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| 646 | #define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16) |
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| 647 | #define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16) |
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| 648 | #define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) |
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| 649 | |
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| 650 | /* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */ |
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| 651 | #define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12) |
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| 652 | |
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| 653 | /* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */ |
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| 654 | #define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11) |
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| 655 | |
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| 656 | /* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */ |
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| 657 | #define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10) |
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| 658 | #define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10) |
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| 659 | #define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) |
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| 660 | |
|---|
| 661 | /* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */ |
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| 662 | #define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8) |
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| 663 | |
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| 664 | /* field: VERSION - Version. These bits provide the revision of the device. */ |
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| 665 | #define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7) |
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| 666 | #define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7) |
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| 667 | #define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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| 668 | |
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| 669 | /* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */ |
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| 670 | #define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2) |
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| 671 | #define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2) |
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| 672 | #define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) |
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| 673 | |
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| 674 | |
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| 675 | /*---------------------TMS570_SYS1_SSIVEC---------------------*/ |
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| 676 | /* field: SSIDATA - System software interrupt data key. */ |
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| 677 | #define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15) |
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| 678 | #define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15) |
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| 679 | #define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
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| 680 | |
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| 681 | /* field: SSIVECT - These bits contain the source for the system software interrupt. */ |
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| 682 | #define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7) |
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| 683 | #define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7) |
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| 684 | #define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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| 685 | |
|---|
| 686 | |
|---|
| 687 | /*----------------------TMS570_SYS1_SSIF----------------------*/ |
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| 688 | /* field: SSI_FLAG - System software interrupt flag[4-1]. */ |
|---|
| 689 | #define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3) |
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| 690 | #define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 691 | #define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 692 | |
|---|
| 693 | |
|---|
| 694 | |
|---|
| 695 | #endif /* LIBBSP_ARM_TMS570_SYS1 */ |
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