source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 33.5 KB
Line 
1/* The header file is generated by make_header.py from SYS.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_SYS1
40#define LIBBSP_ARM_tms570_SYS1
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t SYSPC1;            /*SYS Pin Control Register 1*/
46  uint32_t SYSPC2;            /*SYS Pin Control Register 2*/
47  uint32_t SYSPC3;            /*SYS Pin Control Register 3*/
48  uint32_t SYSPC4;            /*SYS Pin Control Register 4*/
49  uint32_t SYSPC5;            /*SYS Pin Control Register 5*/
50  uint32_t SYSPC6;            /*SYS Pin Control Register 6*/
51  uint32_t SYSPC7;            /*SYS Pin Control Register 7*/
52  uint32_t SYSPC8;            /*SYS Pin Control Register 8*/
53  uint32_t SYSPC9;            /*SYS Pin Control Register 9*/
54  uint8_t reserved1 [12];
55  uint32_t CSDIS;             /*Clock Source Disable Register*/
56  uint32_t CSDISSET;          /*Clock Source Disable Set Register*/
57  uint32_t CSDISCLR;          /*Clock Source Disable Clear Register*/
58  uint32_t CDDIS;             /*Clock Domain Disable Register*/
59  uint32_t CDDISSET;          /*Clock Domain Disable Set Register*/
60  uint32_t CDDISCLR;          /*Clock Domain Disable Clear Register*/
61  uint32_t GHVSRC;            /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/
62  uint32_t VCLKASRC;          /*Peripheral Asynchronous Clock Source Register*/
63  uint32_t RCLKSRC;           /*RTI Clock Source Register*/
64  uint32_t CSVSTAT;           /*Clock Source Valid Status Register*/
65  uint32_t MSTGCR;            /*Memory Self-Test Global Control Register*/
66  uint32_t MINITGCR;          /*Memory Hardware Initialization Global Control Register*/
67  uint32_t MSIENA;            /*Memory Self-Test/Initialization Enable Register*/
68  uint8_t reserved2 [4];
69  uint32_t MSTCGSTAT;         /*MSTC Global Status Register*/
70  uint32_t MINISTAT;          /*Memory Hardware Initialization Status Register*/
71  uint32_t PLLCTL1;           /*PLL Control Register 1*/
72  uint32_t PLLCTL2;           /*PLL Control Register 2*/
73  uint32_t SYSPC10;           /*SYS Pin Control Register 10*/
74  uint32_t DIEIDL;            /*Die Identification Register, Lower Word*/
75  uint32_t DIEIDH;            /*Die Identification Register, Upper Word*/
76  uint8_t reserved3 [4];
77  uint32_t LPOMONCTL;         /*LPO/Clock Monitor Control Register*/
78  uint32_t CLKTEST;           /*Clock Test Register*/
79  uint32_t DFTCTRLREG1;       /*DFT Control Register*/
80  uint32_t DFTCTRLREG2;       /*DFT Control Register 2*/
81  uint8_t reserved4 [8];
82  uint32_t GPREG1;            /*General Purpose Register*/
83  uint8_t reserved5 [4];
84  uint32_t IMPFASTS;          /*Imprecise Fault Status Register*/
85  uint32_t IMPFTADD;          /*Imprecise Fault Write Address Register*/
86  uint32_t SSIR1;             /*System Software Interrupt Request 1 Register*/
87  uint32_t SSIR2;             /*System Software Interrupt Request 2 Register*/
88  uint32_t SSIR3;             /*System Software Interrupt Request 3 Register*/
89  uint32_t SSIR4;             /*System Software Interrupt Request 4 Register*/
90  uint32_t RAMGCR;            /*RAM Control Register*/
91  uint32_t BMMCR1;            /*Bus Matrix Module Control Register 1*/
92  uint8_t reserved6 [4];
93  uint32_t CPURSTCR;          /*CPU Reset Control Register*/
94  uint32_t CLKCNTL;           /*Clock Control Register*/
95  uint32_t ECPCNTL;           /*ECP Control Register*/
96  uint8_t reserved7 [4];
97  uint32_t DEVCR1;            /*DEV Parity Control Register 1*/
98  uint32_t SYSECR;            /*System Exception Control Register*/
99  uint32_t SYSESR;            /*System Exception Status Register*/
100  uint32_t SYSTASR;           /*System Test Abort Status Register*/
101  uint32_t GLBSTAT;           /*Global Status Register*/
102  uint32_t DEVID;             /*Device Identification Register*/
103  uint32_t SSIVEC;            /*Software Interrupt Vector Register*/
104  uint32_t SSIF;              /*System Software Interrupt Flag Register*/
105} tms570_sys1_t;
106
107
108/*---------------------TMS570_SYS1SYSPC1---------------------*/
109/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
110#define TMS570_SYS1_SYSPC1_ECPCLKFUN BSP_FLD32(0)
111
112
113/*----------------------TMS570_SYS1CSDIS----------------------*/
114/* field: CLKSROFF - Clock source[7-3] off. */
115#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7)
116#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7)
117#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
118
119/* field: CLKSROFF - Clock source[1-0] off. */
120#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 1)
121#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 1)
122#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
123
124
125/*--------------------TMS570_SYS1CSDISSET--------------------*/
126/* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */
127#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7)
128#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
129#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
130
131/* field: SETCLKSR_OFF - Set clock source[1-0] to the disabled state. */
132#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 1)
133#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
134#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
135
136
137/*--------------------TMS570_SYS1CSDISCLR--------------------*/
138/* field: CLRCLKSR_OFF - Enables clock source[7-3]. */
139#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7)
140#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
141#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
142
143/* field: CLRCLKSR_OFF - Enables clock source[1-0]. */
144#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 1)
145#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
146#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
147
148
149/*----------------------TMS570_SYS1CDDIS----------------------*/
150/* field: VCLKAOFF - VCLKA[4-3] domain off. */
151#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11)
152#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
153#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
154
155/* field: VCLK3OFF - VCLK3 domain off. */
156#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_FLD32(8)
157
158/* field: RTICLK1OFF - RTICLK1 domain off. */
159#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_FLD32(6)
160
161/* field: VCLKAOFF - VCLKA[2-1] domain off. */
162#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5)
163#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,4, 5)
164#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
165
166/* field: VCLK2OFF - VCLK2 domain off. */
167#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_FLD32(3)
168
169/* field: VCLKPOFF - VCLK_periph domain off. */
170#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_FLD32(2)
171
172/* field: HCLKOFF - HCLK and VCLK_sys domains off. */
173#define TMS570_SYS1_CDDIS_HCLKOFF BSP_FLD32(1)
174
175/* field: GCLKOFF - GCLK domain off. */
176#define TMS570_SYS1_CDDIS_GCLKOFF BSP_FLD32(0)
177
178
179/*--------------------TMS570_SYS1CDDISSET--------------------*/
180/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
181#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
182#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
183#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
184
185/* field: SETVCLK3OFF - Set VCLK3 domain. */
186#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_FLD32(8)
187
188/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
189#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_FLD32(6)
190
191/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
192#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_FLD32(5)
193
194/* field: SETVCLKA1OFF - Set VCLKA1 domain. */
195#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_FLD32(4)
196
197/* field: SETVCLK2OFF - Set VCLK2 domain. */
198#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_FLD32(3)
199
200/* field: SETVCLKPOFF - Set VCLK_periph domain. */
201#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_FLD32(2)
202
203/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
204#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_FLD32(1)
205
206/* field: SETGCLKOFF - Set GCLK domain. */
207#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_FLD32(0)
208
209
210/*--------------------TMS570_SYS1CDDISCLR--------------------*/
211/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
212#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
213#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
214#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
215
216/* field: Reserved - Reserved */
217#define TMS570_SYS1_CDDISCLR_Reserved BSP_FLD32(9)
218
219/* field: CLRVCLK3OFF - Clear VCLK3 domain. */
220#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_FLD32(8)
221
222/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
223#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_FLD32(6)
224
225/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
226#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_FLD32(5)
227
228/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
229#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_FLD32(4)
230
231/* field: CLRVCLK2OFF - Clear VCLK2 domain. */
232#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_FLD32(3)
233
234/* field: CLRVCLKPOFF - CLRVCLKPOFF */
235#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_FLD32(2)
236
237/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
238#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_FLD32(1)
239
240/* field: CLRGCLKOFF - Clear GCLK domain. */
241#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_FLD32(0)
242
243
244/*---------------------TMS570_SYS1GHVSRC---------------------*/
245/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
246#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
247#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
248#define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
249
250/* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */
251#define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19)
252#define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19)
253#define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
254
255/* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */
256#define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3)
257#define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
258#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
259
260
261/*--------------------TMS570_SYS1VCLKASRC--------------------*/
262/* field: VCLKA2S - Peripheral asynchronous clock2 source. */
263#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
264#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
265#define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
266
267/* field: VCLKA1S - Peripheral asynchronous clock1 source. */
268#define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3)
269#define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3)
270#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
271
272
273/*---------------------TMS570_SYS1RCLKSRC---------------------*/
274/* field: RTI1DIV - RTI clock1 Divider. */
275#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
276#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
277#define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
278
279/* field: RTI1SRC - RTI clock1 source. */
280#define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3)
281#define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3)
282#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
283
284
285/*---------------------TMS570_SYS1CSVSTAT---------------------*/
286/* field: CLKSRV - Clock source[7-0] valid. */
287#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
288#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
289#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
290
291/* field: CLKSR - Clock source[1-0] valid. */
292#define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1)
293#define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1)
294#define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
295
296
297/*---------------------TMS570_SYS1MSTGCR---------------------*/
298/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
299#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
300#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
301#define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
302
303/* field: MSTGENA - Memory self-test controller global enable key */
304#define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3)
305#define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
306#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
307
308
309/*--------------------TMS570_SYS1MINITGCR--------------------*/
310/* field: MINITGENA - Memory hardware initialization global enable key. */
311#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
312#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
313#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
314
315
316/*---------------------TMS570_SYS1MSIENA---------------------*/
317/* field: MSIENA - PBIST controller and memory initialization enable register. */
318#define TMS570_SYS1_MSIENA_MSIENA(val) BSP_FLD32(val,0, 31)
319#define TMS570_SYS1_MSIENA_MSIENA_GET(reg) BSP_FLD32GET(reg,0, 31)
320#define TMS570_SYS1_MSIENA_MSIENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
321
322
323/*--------------------TMS570_SYS1MSTCGSTAT--------------------*/
324/* field: MINIDONE - Memory hardware initialization complete status. */
325#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_FLD32(8)
326
327/* field: MSTDONE - Memory self-test run complete status. */
328#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_FLD32(0)
329
330
331/*--------------------TMS570_SYS1MINISTAT--------------------*/
332/* field: MIDONE - Memory hardware initialization status bit. */
333#define TMS570_SYS1_MINISTAT_MIDONE(val) BSP_FLD32(val,0, 31)
334#define TMS570_SYS1_MINISTAT_MIDONE_GET(reg) BSP_FLD32GET(reg,0, 31)
335#define TMS570_SYS1_MINISTAT_MIDONE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
336
337
338/*---------------------TMS570_SYS1PLLCTL1---------------------*/
339/* field: ROS - Reset on PLL Slip */
340#define TMS570_SYS1_PLLCTL1_ROS BSP_FLD32(31)
341
342/* field: MASK_SLIP - Mask detection of PLL slip */
343#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
344#define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
345#define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
346
347/* field: PLLDIV - PLL Output Clock Divider */
348#define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
349#define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
350#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
351
352/* field: ROF - Reset on Oscillator Fail */
353#define TMS570_SYS1_PLLCTL1_ROF BSP_FLD32(23)
354
355/* field: REFCLKDIV - Reference Clock Divider */
356#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
357#define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
358#define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
359
360/* field: PLLMUL - PLL Multiplication Factor */
361#define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
362#define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
363#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
364
365
366/*---------------------TMS570_SYS1PLLCTL2---------------------*/
367/* field: FMENA - Frequency Modulation Enable. */
368#define TMS570_SYS1_PLLCTL2_FMENA BSP_FLD32(31)
369
370/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
371#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
372#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
373#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
374
375/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
376#define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
377#define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
378#define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
379
380/* field: ODPLL - Internal PLL Output Divider. */
381#define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
382#define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
383#define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
384
385/* field: SPR_AMOUNT - Spreading Amount. */
386#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
387#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
388#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
389
390
391/*---------------------TMS570_SYS1SYSPC10---------------------*/
392/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
393#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_FLD32(0)
394
395
396/*---------------------TMS570_SYS1DIEIDL---------------------*/
397/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
398#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
399#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
400#define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31)
401
402/* field: WAFER - These read only bits contain the wafer number of the device. */
403#define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21)
404#define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21)
405#define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
406
407/* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */
408#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15)
409#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15)
410#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
411
412/* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */
413#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7)
414#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7)
415#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
416
417
418/*---------------------TMS570_SYS1DIEIDH---------------------*/
419/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
420#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
421#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
422#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
423
424
425/*--------------------TMS570_SYS1LPOMONCTL--------------------*/
426/* field: BIAS_ENABLE - Bias enable. */
427#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
428
429/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
430#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
431
432/* field: HFTRIM - High frequency oscillator trim value. */
433#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
434#define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
435#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
436
437
438/*---------------------TMS570_SYS1CLKTEST---------------------*/
439/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
440#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
441
442/* field: RANGEDETCTRL - Range detection control. */
443#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
444
445/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
446#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
447
448/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
449#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
450#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
451#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
452
453/* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */
454#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11)
455#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11)
456#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
457
458/* field: SEL_ECP_PIN - ECLK pin clock source select */
459#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3)
460#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3)
461#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
462
463
464/*-------------------TMS570_SYS1DFTCTRLREG1-------------------*/
465/* field: DFTWRITE - DFT logic access. */
466#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
467#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
468#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
469
470/* field: DFTREAD - DFT logic access. */
471#define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9)
472#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9)
473#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
474
475/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
476#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
477#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
478#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
479
480
481/*-------------------TMS570_SYS1DFTCTRLREG2-------------------*/
482/* field: IMPDF - DFT Implementation defined bits. */
483#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
484#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
485#define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
486
487/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
488#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
489#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
490#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
491
492
493/*---------------------TMS570_SYS1GPREG1---------------------*/
494/* field: EMIF_FUNC - Enable EMIF functions to be output. */
495#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_FLD32(31)
496
497/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
498#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
499#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
500#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
501
502/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
503#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
504#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
505#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
506
507/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
508#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
509#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
510#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
511
512
513/*--------------------TMS570_SYS1IMPFASTS--------------------*/
514/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
515#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_FLD32(0)
516
517
518/*--------------------TMS570_SYS1IMPFTADD--------------------*/
519/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
520#define TMS570_SYS1_IMPFTADD_IMPFTADD(val) BSP_FLD32(val,0, 31)
521#define TMS570_SYS1_IMPFTADD_IMPFTADD_GET(reg) BSP_FLD32GET(reg,0, 31)
522#define TMS570_SYS1_IMPFTADD_IMPFTADD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
523
524
525/*----------------------TMS570_SYS1SSIR1----------------------*/
526/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
527#define TMS570_SYS1_SSIR1_SSKEY1(val) BSP_FLD32(val,8, 15)
528#define TMS570_SYS1_SSIR1_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
529#define TMS570_SYS1_SSIR1_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
530
531/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
532#define TMS570_SYS1_SSIR1_SSDATA1(val) BSP_FLD32(val,0, 7)
533#define TMS570_SYS1_SSIR1_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
534#define TMS570_SYS1_SSIR1_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
535
536
537/*---------------------TMS570_SYS1RAMGCR---------------------*/
538/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
539#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
540#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
541#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
542
543/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
544#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_FLD32(2)
545
546/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
547#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_FLD32(0)
548
549
550/*---------------------TMS570_SYS1BMMCR1---------------------*/
551/* field: MEMSW - Memory swap key. */
552#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
553#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
554#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
555
556
557/*--------------------TMS570_SYS1CPURSTCR--------------------*/
558/* field: CPU_RESET - CPU Reset. */
559#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_FLD32(0)
560
561
562/*---------------------TMS570_SYS1CLKCNTL---------------------*/
563/* field: VCLK2R - VBUS clock2 ratio. */
564#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
565#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
566#define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
567
568/* field: VCLKR - VBUS clock ratio. */
569#define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19)
570#define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19)
571#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
572
573/* field: PENA - Peripheral enable bit. */
574#define TMS570_SYS1_CLKCNTL_PENA BSP_FLD32(8)
575
576
577/*---------------------TMS570_SYS1ECPCNTL---------------------*/
578/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
579#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_FLD32(24)
580
581/* field: ECPCOS - ECP continue on suspend. */
582#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_FLD32(23)
583
584/* field: ECPINSEL - Select ECP input clock source. */
585#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
586#define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
587#define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
588
589/* field: ECPDIV - ECP divider value. */
590#define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
591#define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
592#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
593
594
595/*---------------------TMS570_SYS1DEVCR1---------------------*/
596/* field: DEVPARSEL - Device parity select bit key. */
597#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
598#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
599#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
600
601
602/*---------------------TMS570_SYS1SYSECR---------------------*/
603/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
604#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
605#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
606#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
607
608
609/*---------------------TMS570_SYS1SYSESR---------------------*/
610/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
611#define TMS570_SYS1_SYSESR_PORST BSP_FLD32(15)
612
613/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
614#define TMS570_SYS1_SYSESR_OSCRST BSP_FLD32(14)
615
616/* field: WDRST - Watchdog reset flag. */
617#define TMS570_SYS1_SYSESR_WDRST BSP_FLD32(13)
618
619/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
620#define TMS570_SYS1_SYSESR_CPURST BSP_FLD32(5)
621
622/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
623#define TMS570_SYS1_SYSESR_SWRST BSP_FLD32(4)
624
625/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
626#define TMS570_SYS1_SYSESR_EXTRST BSP_FLD32(3)
627
628/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
629#define TMS570_SYS1_SYSESR_MPMODE BSP_FLD32(0)
630
631
632/*---------------------TMS570_SYS1SYSTASR---------------------*/
633/* field: EFUSE_Abort - Test Abort status flag. */
634#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
635#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
636#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
637
638
639/*---------------------TMS570_SYS1GLBSTAT---------------------*/
640/* field: FBSLIP - PLL over cycle slip detection. */
641#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_FLD32(9)
642
643/* field: RFSLIP - PLL under cycle slip detection. */
644#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_FLD32(8)
645
646/* field: OSCFAIL - Oscillator fail flag bit. */
647#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_FLD32(0)
648
649
650/*----------------------TMS570_SYS1DEVID----------------------*/
651/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
652#define TMS570_SYS1_DEVID_CP15 BSP_FLD32(31)
653
654/* field: TECH - These bits define the process technology by which the device was manufactured. */
655#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
656#define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16)
657#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
658
659/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
660#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_FLD32(12)
661
662/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
663#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_FLD32(11)
664
665/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
666#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
667#define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10)
668#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
669
670/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
671#define TMS570_SYS1_DEVID_RAM_ECC BSP_FLD32(8)
672
673/* field: VERSION - Version. These bits provide the revision of the device. */
674#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
675#define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7)
676#define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
677
678/* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */
679#define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2)
680#define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2)
681#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
682
683
684/*---------------------TMS570_SYS1SSIVEC---------------------*/
685/* field: SSIDATA - System software interrupt data key. */
686#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
687#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
688#define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
689
690/* field: SSIVECT - These bits contain the source for the system software interrupt. */
691#define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7)
692#define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7)
693#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
694
695
696/*----------------------TMS570_SYS1SSIF----------------------*/
697/* field: SSI_FLAG - System software interrupt flag[4-1]. */
698#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
699#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
700#define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
701
702
703
704#endif /* LIBBSP_ARM_tms570_SYS1 */
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