1 | /* The header file is generated by make_header.py from STC.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_tms570_STC |
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40 | #define LIBBSP_ARM_tms570_STC |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t STCGCR0; /*STC Global Control Register 0*/ |
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46 | uint32_t STCGCR1; /*STCGlobal Control Register 1*/ |
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47 | uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/ |
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48 | uint32_t STC_CADDR; /*STC Current ROM Address Register*/ |
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49 | uint32_t STCCICR; /*STC Current Interval Count Register*/ |
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50 | uint32_t STCGSTAT; /*Self-Test Global Status Register*/ |
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51 | uint32_t STCFSTAT; /*Self-Test Fail Status Register*/ |
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52 | uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/ |
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53 | uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/ |
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54 | uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/ |
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55 | uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/ |
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56 | uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/ |
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57 | uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/ |
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58 | uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/ |
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59 | uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/ |
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60 | uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/ |
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61 | } tms570_stc_t; |
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62 | |
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63 | |
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64 | /*---------------------TMS570_STCSTCGCR0---------------------*/ |
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65 | /* field: INTCOUNT - Number of intervals of self-test run */ |
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66 | #define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31) |
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67 | #define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31) |
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68 | #define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) |
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69 | |
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70 | /* field: RS_CNT - Restart or Continue */ |
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71 | #define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0) |
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72 | |
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73 | |
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74 | /*---------------------TMS570_STCSTCGCR1---------------------*/ |
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75 | /* field: STC_ENA - Self-test run enable key */ |
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76 | #define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3) |
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77 | #define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) |
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78 | #define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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79 | |
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80 | |
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81 | /*----------------------TMS570_STCSTCTPR----------------------*/ |
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82 | /* field: RTOD - Self-test timeout count preload */ |
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83 | #define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31) |
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84 | #define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31) |
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85 | #define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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86 | |
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87 | |
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88 | /*--------------------TMS570_STCSTC_CADDR--------------------*/ |
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89 | /* field: ADDR - Current ROM Address */ |
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90 | #define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31) |
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91 | #define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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92 | #define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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93 | |
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94 | |
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95 | /*---------------------TMS570_STCSTCCICR---------------------*/ |
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96 | /* field: N - Interval Number */ |
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97 | #define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15) |
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98 | #define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15) |
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99 | #define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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100 | |
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101 | |
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102 | /*---------------------TMS570_STCSTCGSTAT---------------------*/ |
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103 | /* field: TEST_FAIL - Test Fail */ |
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104 | #define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1) |
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105 | |
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106 | /* field: TEST_DONE - Test Done */ |
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107 | #define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0) |
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108 | |
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109 | |
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110 | /*---------------------TMS570_STCSTCFSTAT---------------------*/ |
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111 | /* field: TO_ERR - Timeout Error */ |
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112 | #define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2) |
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113 | |
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114 | /* field: CPU2_FAIL - CPU2 failure info */ |
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115 | #define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1) |
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116 | |
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117 | /* field: CPU1_FAIL - CPU1 failure info */ |
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118 | #define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0) |
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119 | |
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120 | |
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121 | /*------------------TMS570_STCCPU1_CURMISR3------------------*/ |
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122 | /* field: MISR - MISR data from CPU1 */ |
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123 | #define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31) |
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124 | #define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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125 | #define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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126 | |
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127 | |
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128 | /*------------------TMS570_STCCPU1_CURMISR2------------------*/ |
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129 | /* field: MISR - MISR data from CPU1 */ |
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130 | #define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31) |
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131 | #define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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132 | #define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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133 | |
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134 | |
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135 | /*------------------TMS570_STCCPU1_CURMISR1------------------*/ |
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136 | /* field: MISR - MISR data from CPU1 */ |
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137 | #define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31) |
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138 | #define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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139 | #define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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140 | |
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141 | |
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142 | /*------------------TMS570_STCCPU1_CURMISR0------------------*/ |
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143 | /* field: MISR - MISR data from CPU1 */ |
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144 | #define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31) |
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145 | #define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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146 | #define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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147 | |
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148 | |
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149 | /*------------------TMS570_STCCPU2_CURMISR3------------------*/ |
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150 | /* field: MISR - MISR data from CPU2 */ |
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151 | #define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31) |
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152 | #define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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153 | #define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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154 | |
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155 | |
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156 | /*------------------TMS570_STCCPU2_CURMISR2------------------*/ |
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157 | /* field: MISR - MISR data from CPU2 */ |
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158 | #define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31) |
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159 | #define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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160 | #define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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161 | |
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162 | |
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163 | /*------------------TMS570_STCCPU2_CURMISR1------------------*/ |
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164 | /* field: MISR - MISR data from CPU2 */ |
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165 | #define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31) |
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166 | #define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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167 | #define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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168 | |
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169 | |
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170 | /*------------------TMS570_STCCPU2_CURMISR0------------------*/ |
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171 | /* field: MISR - MISR data from CPU2 */ |
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172 | #define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31) |
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173 | #define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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174 | #define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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175 | |
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176 | |
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177 | /*---------------------TMS570_STCSTCSCSCR---------------------*/ |
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178 | /* field: FAULT_INS - Enable / Disable fault insertion. */ |
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179 | #define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4) |
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180 | |
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181 | /* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */ |
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182 | #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3) |
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183 | #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) |
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184 | #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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185 | |
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186 | |
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187 | |
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188 | #endif /* LIBBSP_ARM_tms570_STC */ |
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