source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 8.2 KB
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1/* The header file is generated by make_header.py from STC.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_STC
40#define LIBBSP_ARM_tms570_STC
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t STCGCR0;           /*STC Global Control Register 0*/
46  uint32_t STCGCR1;           /*STCGlobal Control Register 1*/
47  uint32_t STCTPR;            /*Self-Test Run Timeout Counter Preload Register*/
48  uint32_t STC_CADDR;         /*STC Current ROM Address Register*/
49  uint32_t STCCICR;           /*STC Current Interval Count Register*/
50  uint32_t STCGSTAT;          /*Self-Test Global Status Register*/
51  uint32_t STCFSTAT;          /*Self-Test Fail Status Register*/
52  uint32_t CPU1_CURMISR3;     /*CPU1 Current MISR Register 3*/
53  uint32_t CPU1_CURMISR2;     /*CPU1 Current MISR Register 2*/
54  uint32_t CPU1_CURMISR1;     /*CPU1 Current MISR Register 1*/
55  uint32_t CPU1_CURMISR0;     /*CPU1 Current MISR Register 0*/
56  uint32_t CPU2_CURMISR3;     /*CPU2 Current MISR Register 3*/
57  uint32_t CPU2_CURMISR2;     /*CPU2 Current MISR Register 2*/
58  uint32_t CPU2_CURMISR1;     /*CPU2 Current MISR Register 1*/
59  uint32_t CPU2_CURMISR0;     /*CPU2 Current MISR Register 0*/
60  uint32_t STCSCSCR;          /*Signature Compare Self-Check Register*/
61} tms570_stc_t;
62
63
64/*---------------------TMS570_STCSTCGCR0---------------------*/
65/* field: INTCOUNT - Number of intervals of self-test run */
66#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
67#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
68#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
69
70/* field: RS_CNT - Restart or Continue */
71#define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0)
72
73
74/*---------------------TMS570_STCSTCGCR1---------------------*/
75/* field: STC_ENA - Self-test run enable key */
76#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
77#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
78#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
79
80
81/*----------------------TMS570_STCSTCTPR----------------------*/
82/* field: RTOD - Self-test timeout count preload */
83#define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31)
84#define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31)
85#define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
86
87
88/*--------------------TMS570_STCSTC_CADDR--------------------*/
89/* field: ADDR - Current ROM Address */
90#define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31)
91#define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
92#define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
93
94
95/*---------------------TMS570_STCSTCCICR---------------------*/
96/* field: N - Interval Number */
97#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
98#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
99#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
100
101
102/*---------------------TMS570_STCSTCGSTAT---------------------*/
103/* field: TEST_FAIL - Test Fail */
104#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1)
105
106/* field: TEST_DONE - Test Done */
107#define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0)
108
109
110/*---------------------TMS570_STCSTCFSTAT---------------------*/
111/* field: TO_ERR - Timeout Error */
112#define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2)
113
114/* field: CPU2_FAIL - CPU2 failure info */
115#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1)
116
117/* field: CPU1_FAIL - CPU1 failure info */
118#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0)
119
120
121/*------------------TMS570_STCCPU1_CURMISR3------------------*/
122/* field: MISR - MISR data from CPU1 */
123#define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
124#define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
125#define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
126
127
128/*------------------TMS570_STCCPU1_CURMISR2------------------*/
129/* field: MISR - MISR data from CPU1 */
130#define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
131#define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
132#define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
133
134
135/*------------------TMS570_STCCPU1_CURMISR1------------------*/
136/* field: MISR - MISR data from CPU1 */
137#define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
138#define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
139#define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
140
141
142/*------------------TMS570_STCCPU1_CURMISR0------------------*/
143/* field: MISR - MISR data from CPU1 */
144#define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
145#define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
146#define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
147
148
149/*------------------TMS570_STCCPU2_CURMISR3------------------*/
150/* field: MISR - MISR data from CPU2 */
151#define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
152#define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
153#define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
154
155
156/*------------------TMS570_STCCPU2_CURMISR2------------------*/
157/* field: MISR - MISR data from CPU2 */
158#define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
159#define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
160#define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
161
162
163/*------------------TMS570_STCCPU2_CURMISR1------------------*/
164/* field: MISR - MISR data from CPU2 */
165#define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
166#define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
167#define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
168
169
170/*------------------TMS570_STCCPU2_CURMISR0------------------*/
171/* field: MISR - MISR data from CPU2 */
172#define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
173#define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
174#define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
175
176
177/*---------------------TMS570_STCSTCSCSCR---------------------*/
178/* field: FAULT_INS - Enable / Disable fault insertion. */
179#define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4)
180
181/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
182#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
183#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
184#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
185
186
187
188#endif /* LIBBSP_ARM_tms570_STC */
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