source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 17.4 KB
Line 
1/* The header file is generated by make_header.py from RTI.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_RTI
40#define LIBBSP_ARM_tms570_RTI
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t COMPx;             /*RTI Compare x Register*/
46  uint32_t UDCPx;             /*RTI Update Compare x Register*/
47} tms570_rti_compare_t;
48
49typedef struct{
50  uint32_t FRCx;              /*RTI Free Running Counter x Register*/
51  uint32_t UCx;               /*RTI Up Counter x Register*/
52  uint32_t CPUCx;             /*RTI Compare Up Counter x Register*/
53  uint8_t reserved1 [4];
54  uint32_t CAFRCx;            /*RTI Capture Free Running Counter x Register*/
55  uint32_t CAUCx;             /*RTI Capture Up Counter x Register*/
56  uint32_t rsvd[2];           /*Reserved*/
57} tms570_rti_counter_t;
58
59typedef struct{
60  uint32_t GCTRL;             /*RTI Global Control Register*/
61  uint32_t TBCTRL;            /*RTI Timebase Control Register*/
62  uint32_t CAPCTRL;           /*RTI Capture Control Register*/
63  uint32_t COMPCTRL;          /*RTI Compare Control Register*/
64  tms570_rti_counter_t CNT[2];/*Counters*/
65  tms570_rti_compare_t CMP[4];/*Compares*/
66  uint32_t TBLCOMP;           /*RTI Timebase Low Compare Register*/
67  uint32_t TBHCOMP;           /*RTI Timebase High Compare Register*/
68  uint8_t reserved2 [8];
69  uint32_t SETINTENA;         /*RTI Set Interrupt Enable Register*/
70  uint32_t CLEARINTENA;       /*RTI Clear Interrupt Enable Register*/
71  uint32_t INTFLAG;           /*RTI Interrupt Flag Register*/
72  uint8_t reserved3 [4];
73  uint32_t DWDCTRL;           /*Digital Watchdog Control Register*/
74  uint32_t DWDPRLD;           /*Digital Watchdog Preload Register*/
75  uint32_t WDSTATUS;          /*Watchdog Status Register*/
76  uint32_t WDKEY;             /*RTI Watchdog Key Register*/
77  uint32_t DWDCNTR;           /*RTI Digital Watchdog Down Counter Register*/
78  uint32_t WWDRXNCTRL;        /*Digital Windowed Watchdog Reaction Control Register*/
79  uint32_t WWDSIZECTRL;       /*Digital Windowed Watchdog Window Size Control Register*/
80  uint32_t INTCLRENABLE;      /*RTI Compare Interrupt Clear Enable Register*/
81  uint32_t COMP0CLR;          /*RTI Compare 0 Clear Register*/
82  uint32_t COMP1CLR;          /*RTI Compare 1 Clear Register*/
83  uint32_t COMP2CLR;          /*RTI Compare 2 Clear Register*/
84  uint32_t COMP3CLR;          /*RTI Compare 3 Clear Register*/
85} tms570_rti_t;
86
87
88/*----------------------TMS570_RTICOMPx----------------------*/
89/* field: COMPx - Compare x. */
90#define TMS570_RTI_COMPx_COMPx(val) BSP_FLD32(val,0, 31)
91#define TMS570_RTI_COMPx_COMPx_GET(reg) BSP_FLD32GET(reg,0, 31)
92#define TMS570_RTI_COMPx_COMPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
93
94
95/*----------------------TMS570_RTIUDCPx----------------------*/
96/* field: UDCPx - Update compare x. */
97#define TMS570_RTI_UDCPx_UDCPx(val) BSP_FLD32(val,0, 31)
98#define TMS570_RTI_UDCPx_UDCPx_GET(reg) BSP_FLD32GET(reg,0, 31)
99#define TMS570_RTI_UDCPx_UDCPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
100
101
102/*-----------------------TMS570_RTIFRCx-----------------------*/
103/* field: FRC0 - FRC0 */
104#define TMS570_RTI_FRCx_FRC0(val) BSP_FLD32(val,0, 31)
105#define TMS570_RTI_FRCx_FRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
106#define TMS570_RTI_FRCx_FRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
107
108
109/*-----------------------TMS570_RTIUCx-----------------------*/
110/* field: UC0 - Up counter 0. */
111#define TMS570_RTI_UCx_UC0(val) BSP_FLD32(val,0, 31)
112#define TMS570_RTI_UCx_UC0_GET(reg) BSP_FLD32GET(reg,0, 31)
113#define TMS570_RTI_UCx_UC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
114
115
116/*----------------------TMS570_RTICPUCx----------------------*/
117/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
118#define TMS570_RTI_CPUCx_CPUC0(val) BSP_FLD32(val,0, 31)
119#define TMS570_RTI_CPUCx_CPUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
120#define TMS570_RTI_CPUCx_CPUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
121
122
123/*----------------------TMS570_RTICAFRCx----------------------*/
124/* field: CAFRC0 - Capture free running counter 0. */
125#define TMS570_RTI_CAFRCx_CAFRC0(val) BSP_FLD32(val,0, 31)
126#define TMS570_RTI_CAFRCx_CAFRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
127#define TMS570_RTI_CAFRCx_CAFRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
128
129
130/*----------------------TMS570_RTICAUCx----------------------*/
131/* field: CAUC0 - Capture up counter 0. */
132#define TMS570_RTI_CAUCx_CAUC0(val) BSP_FLD32(val,0, 31)
133#define TMS570_RTI_CAUCx_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
134#define TMS570_RTI_CAUCx_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
135
136
137/*-----------------------TMS570_RTIrsvd-----------------------*/
138/* field: CAUC0 - Capture up counter 0. */
139#define TMS570_RTI_rsvd_CAUC0(val) BSP_FLD32(val,0, 31)
140#define TMS570_RTI_rsvd_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
141#define TMS570_RTI_rsvd_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
142
143
144/*----------------------TMS570_RTIGCTRL----------------------*/
145/* field: NTUSEL - Select NTU signal. */
146#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
147#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
148#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
149
150/* field: COS - Continue on suspend. */
151#define TMS570_RTI_GCTRL_COS BSP_FLD32(15)
152
153/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
154#define TMS570_RTI_GCTRL_CNT1EN BSP_FLD32(1)
155
156/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
157#define TMS570_RTI_GCTRL_CNT0EN BSP_FLD32(0)
158
159
160/*----------------------TMS570_RTITBCTRL----------------------*/
161/* field: INC - Increment free running counter 0. */
162#define TMS570_RTI_TBCTRL_INC BSP_FLD32(1)
163
164/* field: TBEXT - Timebase external. */
165#define TMS570_RTI_TBCTRL_TBEXT BSP_FLD32(0)
166
167
168/*---------------------TMS570_RTICAPCTRL---------------------*/
169/* field: CAPCNTR1 - Capture counter 1. */
170#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_FLD32(1)
171
172/* field: CAPCNTR0 - Capture counter 0. */
173#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_FLD32(0)
174
175
176/*---------------------TMS570_RTICOMPCTRL---------------------*/
177/* field: COMPSEL3 - Compare select 3. */
178#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_FLD32(12)
179
180/* field: COMPSEL2 - Compare select 2. */
181#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_FLD32(8)
182
183/* field: COMPSEL1 - Compare select 1. */
184#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_FLD32(4)
185
186/* field: COMPSEL0 - Compare select 0. */
187#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_FLD32(0)
188
189
190/*---------------------TMS570_RTITBLCOMP---------------------*/
191/* field: TBLCOMP - Timebase low compare value. */
192#define TMS570_RTI_TBLCOMP_TBLCOMP(val) BSP_FLD32(val,0, 31)
193#define TMS570_RTI_TBLCOMP_TBLCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
194#define TMS570_RTI_TBLCOMP_TBLCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
195
196
197/*---------------------TMS570_RTITBHCOMP---------------------*/
198/* field: TBHCOMP - Timebase high compare value. */
199#define TMS570_RTI_TBHCOMP_TBHCOMP(val) BSP_FLD32(val,0, 31)
200#define TMS570_RTI_TBHCOMP_TBHCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
201#define TMS570_RTI_TBHCOMP_TBHCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
202
203
204/*--------------------TMS570_RTISETINTENA--------------------*/
205/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
206#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_FLD32(18)
207
208/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
209#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_FLD32(17)
210
211/* field: SETTBINT - Set timebase interrupt. */
212#define TMS570_RTI_SETINTENA_SETTBINT BSP_FLD32(16)
213
214/* field: SETDMA3 - Set compare DMA request 3. */
215#define TMS570_RTI_SETINTENA_SETDMA3 BSP_FLD32(11)
216
217/* field: SETDMA2 - Set compare DMA request 2. */
218#define TMS570_RTI_SETINTENA_SETDMA2 BSP_FLD32(10)
219
220/* field: SETDMA1 - Set compare DMA request 1. */
221#define TMS570_RTI_SETINTENA_SETDMA1 BSP_FLD32(9)
222
223/* field: SETDMA0 - Set compare DMA request 0. */
224#define TMS570_RTI_SETINTENA_SETDMA0 BSP_FLD32(8)
225
226/* field: SETINT3 - Set compare interrupt 3. */
227#define TMS570_RTI_SETINTENA_SETINT3 BSP_FLD32(3)
228
229/* field: SETINT2 - Set compare interrupt 2. */
230#define TMS570_RTI_SETINTENA_SETINT2 BSP_FLD32(2)
231
232/* field: SETINT1 - Set compare interrupt 1. */
233#define TMS570_RTI_SETINTENA_SETINT1 BSP_FLD32(1)
234
235/* field: SETINT0 - Set compare interrupt 0. */
236#define TMS570_RTI_SETINTENA_SETINT0 BSP_FLD32(0)
237
238
239/*-------------------TMS570_RTICLEARINTENA-------------------*/
240/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
241#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_FLD32(18)
242
243/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
244#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_FLD32(17)
245
246/* field: CLEARTBINT - Clear timebase interrupt. */
247#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_FLD32(16)
248
249/* field: CLEARDMA3 - Clear compare DMA request 3. */
250#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_FLD32(11)
251
252/* field: CLEARDMA2 - Clear compare DMA request 2. */
253#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_FLD32(10)
254
255/* field: CLEARDMA1 - Clear compare DMA request 1. */
256#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_FLD32(9)
257
258/* field: CLEARDMA0 - Clear compare DMA request 0. */
259#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_FLD32(8)
260
261/* field: CLEARINT3 - Clear compare interrupt 3. */
262#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_FLD32(3)
263
264/* field: CLEARINT2 - Clear compare interrupt 2. */
265#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_FLD32(2)
266
267/* field: CLEARINT1 - Clear compare interrupt 1. */
268#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_FLD32(1)
269
270/* field: CLEARINT0 - Clear compare interrupt 0. */
271#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_FLD32(0)
272
273
274/*---------------------TMS570_RTIINTFLAG---------------------*/
275/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
276#define TMS570_RTI_INTFLAG_OVL1INT BSP_FLD32(18)
277
278/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
279#define TMS570_RTI_INTFLAG_OVL0INT BSP_FLD32(17)
280
281/* field: TBINT - Timebase interrupt flag. */
282#define TMS570_RTI_INTFLAG_TBINT BSP_FLD32(16)
283
284/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
285#define TMS570_RTI_INTFLAG_INT3 BSP_FLD32(3)
286
287/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
288#define TMS570_RTI_INTFLAG_INT2 BSP_FLD32(2)
289
290/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
291#define TMS570_RTI_INTFLAG_INT1 BSP_FLD32(1)
292
293/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
294#define TMS570_RTI_INTFLAG_INT0 BSP_FLD32(0)
295
296
297/*---------------------TMS570_RTIDWDCTRL---------------------*/
298/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
299#define TMS570_RTI_DWDCTRL_DWDCTRL(val) BSP_FLD32(val,0, 31)
300#define TMS570_RTI_DWDCTRL_DWDCTRL_GET(reg) BSP_FLD32GET(reg,0, 31)
301#define TMS570_RTI_DWDCTRL_DWDCTRL_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
302
303
304/*---------------------TMS570_RTIDWDPRLD---------------------*/
305/* field: DWDPRLD - Digital Watchdog Preload Value. */
306#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
307#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
308#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
309
310
311/*---------------------TMS570_RTIWDSTATUS---------------------*/
312/* field: DWWD_ST - Windowed Watchdog Status */
313#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_FLD32(5)
314
315/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
316#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_FLD32(4)
317
318/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
319#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_FLD32(3)
320
321/* field: KEY_ST - Watchdog key status. */
322#define TMS570_RTI_WDSTATUS_KEY_ST BSP_FLD32(2)
323
324/* field: DWD_ST - DWD status. */
325#define TMS570_RTI_WDSTATUS_DWD_ST BSP_FLD32(1)
326
327
328/*----------------------TMS570_RTIWDKEY----------------------*/
329/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
330#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
331#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
332#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
333
334
335/*---------------------TMS570_RTIDWDCNTR---------------------*/
336/* field: DWDCNTR - DWD down counter. */
337#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
338#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
339#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
340
341
342/*--------------------TMS570_RTIWWDRXNCTRL--------------------*/
343/* field: WWDRXN - The DWWD reaction */
344#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
345#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
346#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
347
348
349/*-------------------TMS570_RTIWWDSIZECTRL-------------------*/
350/* field: WWDSIZE - The DWWD window size */
351#define TMS570_RTI_WWDSIZECTRL_WWDSIZE(val) BSP_FLD32(val,0, 31)
352#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_GET(reg) BSP_FLD32GET(reg,0, 31)
353#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
354
355
356/*-------------------TMS570_RTIINTCLRENABLE-------------------*/
357/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
358#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
359#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
360#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
361
362/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
363#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
364#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
365#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
366
367/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
368#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
369#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
370#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
371
372/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
373#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
374#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
375#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
376
377
378/*---------------------TMS570_RTICOMP0CLR---------------------*/
379/* field: CMP0CLR - Compare 0 clear. */
380#define TMS570_RTI_COMP0CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
381#define TMS570_RTI_COMP0CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
382#define TMS570_RTI_COMP0CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
383
384
385/*---------------------TMS570_RTICOMP1CLR---------------------*/
386/* field: CMP0CLR - Compare 1 clear. */
387#define TMS570_RTI_COMP1CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
388#define TMS570_RTI_COMP1CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
389#define TMS570_RTI_COMP1CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
390
391
392/*---------------------TMS570_RTICOMP2CLR---------------------*/
393/* field: CMP2CLR - Compare 2 clear. */
394#define TMS570_RTI_COMP2CLR_CMP2CLR(val) BSP_FLD32(val,0, 31)
395#define TMS570_RTI_COMP2CLR_CMP2CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
396#define TMS570_RTI_COMP2CLR_CMP2CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
397
398
399/*---------------------TMS570_RTICOMP3CLR---------------------*/
400/* field: CMP3CLR - Compare 3 clear. */
401#define TMS570_RTI_COMP3CLR_CMP3CLR(val) BSP_FLD32(val,0, 31)
402#define TMS570_RTI_COMP3CLR_CMP3CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
403#define TMS570_RTI_COMP3CLR_CMP3CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
404
405
406
407#endif /* LIBBSP_ARM_tms570_RTI */
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