1 | /* The header file is generated by make_header.py from PLL.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_TMS570_PLL |
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40 | #define LIBBSP_ARM_TMS570_PLL |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t PLLCTL3; /*PLL Control 3 Register*/ |
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46 | uint8_t reserved1 [108]; |
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47 | uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/ |
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48 | uint8_t reserved2 [7600]; |
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49 | uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/ |
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50 | uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/ |
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51 | uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/ |
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52 | uint32_t CSDIS; /*Clock Source Disable Register*/ |
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53 | uint32_t CSDISSET; /*Clock Source Disable Set Register*/ |
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54 | uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ |
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55 | uint8_t reserved3 [24]; |
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56 | uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ |
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57 | uint8_t reserved4 [24]; |
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58 | uint32_t PLLCTL1; /*PLL Control 1 Register*/ |
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59 | uint32_t PLLCTL2; /*PLL Control 2 Register*/ |
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60 | uint8_t reserved5 [16]; |
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61 | uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ |
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62 | uint32_t CLKTEST; /*Clock Test Register*/ |
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63 | uint8_t reserved6 [16]; |
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64 | uint32_t GPREG1; /*General Purpose Register*/ |
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65 | uint8_t reserved7 [72]; |
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66 | uint32_t GLBSTAT; /*Global Status Register*/ |
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67 | } tms570_pll_t; |
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68 | |
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69 | |
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70 | /*---------------------TMS570_PLL_PLLCTL3---------------------*/ |
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71 | /* field: ODPLL2 - Internal PLL Output Divider */ |
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72 | #define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) |
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73 | #define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) |
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74 | #define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) |
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75 | |
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76 | /* field: PLLDIV2 - PLL2 Output Clock Divider */ |
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77 | #define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) |
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78 | #define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) |
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79 | #define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) |
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80 | |
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81 | /* field: REFCLKDIV2 - Reference Clock Divider */ |
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82 | #define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) |
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83 | #define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) |
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84 | #define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) |
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85 | |
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86 | /* field: PLLMUL2 - PLL2 Multiplication Factor */ |
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87 | #define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) |
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88 | #define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) |
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89 | #define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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90 | |
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91 | |
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92 | /*---------------------TMS570_PLL_CLKSLIP---------------------*/ |
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93 | /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ |
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94 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) |
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95 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) |
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96 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) |
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97 | |
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98 | /* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ |
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99 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) |
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100 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) |
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101 | #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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102 | |
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103 | |
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104 | /*---------------------TMS570_PLL_SSWPLL1---------------------*/ |
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105 | /* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */ |
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106 | #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15) |
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107 | #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15) |
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108 | #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
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109 | |
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110 | /* field: COUNTER_READ_READY - Counter read ready. */ |
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111 | #define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6) |
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112 | |
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113 | /* field: COUNTER_RESET - Counter reset. */ |
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114 | #define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5) |
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115 | |
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116 | /* field: COUNTER_EN - Counter enable. */ |
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117 | #define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4) |
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118 | |
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119 | /* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */ |
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120 | #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3) |
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121 | #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3) |
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122 | #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3) |
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123 | |
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124 | /* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */ |
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125 | #define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0) |
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126 | |
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127 | |
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128 | /*---------------------TMS570_PLL_SSWPLL2---------------------*/ |
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129 | /* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */ |
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130 | /* Whole 32 bits */ |
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131 | |
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132 | /*---------------------TMS570_PLL_SSWPLL3---------------------*/ |
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133 | /* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */ |
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134 | /* Whole 32 bits */ |
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135 | |
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136 | /*----------------------TMS570_PLL_CSDIS----------------------*/ |
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137 | /* field: CLKSR_7_3_OFF - Clock source[7-3] off. */ |
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138 | #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) |
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139 | #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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140 | #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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141 | |
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142 | /* field: CLKSR_1_0_OFF - Clock source[1-0] off. */ |
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143 | #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) |
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144 | #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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145 | #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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146 | |
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147 | |
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148 | /*--------------------TMS570_PLL_CSDISSET--------------------*/ |
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149 | /* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */ |
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150 | #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) |
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151 | #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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152 | #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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153 | |
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154 | /* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */ |
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155 | #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) |
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156 | #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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157 | #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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158 | |
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159 | |
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160 | /*--------------------TMS570_PLL_CSDISCLR--------------------*/ |
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161 | /* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */ |
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162 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) |
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163 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) |
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164 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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165 | |
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166 | /* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */ |
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167 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) |
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168 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) |
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169 | #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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170 | |
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171 | |
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172 | /*---------------------TMS570_PLL_CSVSTAT---------------------*/ |
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173 | /* field: CLKSR_7_3V - Clock source[7-0] valid. */ |
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174 | #define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7) |
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175 | #define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7) |
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176 | #define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) |
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177 | |
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178 | /* field: CLKSR_1_0V - Clock source[1-0] valid. */ |
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179 | #define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1) |
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180 | #define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1) |
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181 | #define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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182 | |
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183 | |
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184 | /*---------------------TMS570_PLL_PLLCTL1---------------------*/ |
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185 | /* field: ROS - Reset on PLL Slip */ |
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186 | #define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31) |
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187 | |
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188 | /* field: MASK_SLIP - Mask detection of PLL slip */ |
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189 | #define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) |
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190 | #define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) |
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191 | #define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) |
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192 | |
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193 | /* field: PLLDIV - PLL Output Clock Divider */ |
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194 | #define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) |
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195 | #define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) |
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196 | #define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) |
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197 | |
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198 | /* field: ROF - Reset on Oscillator Fail */ |
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199 | #define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23) |
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200 | |
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201 | /* field: REFCLKDIV - Reference Clock Divider */ |
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202 | #define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) |
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203 | #define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) |
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204 | #define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) |
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205 | |
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206 | /* field: PLLMUL - PLL Multiplication Factor */ |
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207 | #define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) |
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208 | #define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) |
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209 | #define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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210 | |
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211 | |
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212 | /*---------------------TMS570_PLL_PLLCTL2---------------------*/ |
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213 | /* field: FMENA - Frequency Modulation Enable. */ |
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214 | #define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31) |
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215 | |
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216 | /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ |
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217 | #define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) |
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218 | #define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) |
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219 | #define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) |
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220 | |
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221 | /* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ |
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222 | #define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) |
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223 | #define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) |
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224 | #define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) |
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225 | |
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226 | /* field: ODPLL - Internal PLL Output Divider. */ |
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227 | #define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) |
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228 | #define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) |
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229 | #define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) |
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230 | |
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231 | /* field: SPR_AMOUNT - Spreading Amount. */ |
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232 | #define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) |
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233 | #define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) |
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234 | #define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) |
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235 | |
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236 | |
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237 | /*--------------------TMS570_PLL_LPOMONCTL--------------------*/ |
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238 | /* field: BIAS_ENABLE - Bias enable. */ |
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239 | #define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) |
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240 | |
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241 | /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ |
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242 | #define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) |
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243 | |
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244 | /* field: HFTRIM - High frequency oscillator trim value. */ |
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245 | #define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) |
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246 | #define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) |
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247 | #define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) |
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248 | |
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249 | |
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250 | /*---------------------TMS570_PLL_CLKTEST---------------------*/ |
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251 | /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ |
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252 | #define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) |
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253 | |
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254 | /* field: RANGEDETCTRL - Range detection control. */ |
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255 | #define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25) |
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256 | |
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257 | /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ |
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258 | #define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) |
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259 | |
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260 | /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ |
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261 | #define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) |
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262 | #define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) |
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263 | #define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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264 | |
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265 | |
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266 | /*---------------------TMS570_PLL_GPREG1---------------------*/ |
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267 | /* field: EMIF_FUNC - Enable EMIF functions to be output. */ |
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268 | #define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31) |
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269 | |
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270 | /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ |
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271 | #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) |
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272 | #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) |
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273 | #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) |
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274 | |
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275 | /* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ |
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276 | #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) |
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277 | #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) |
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278 | #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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279 | |
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280 | /* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ |
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281 | #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) |
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282 | #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) |
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283 | #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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284 | |
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285 | |
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286 | /*---------------------TMS570_PLL_GLBSTAT---------------------*/ |
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287 | /* field: FBSLIP - PLL over cycle slip detection. */ |
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288 | #define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9) |
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289 | |
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290 | /* field: RFSLIP - PLL under cycle slip detection. */ |
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291 | #define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8) |
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292 | |
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293 | /* field: OSCFAIL - Oscillator fail flag bit. */ |
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294 | #define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0) |
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295 | |
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296 | |
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297 | |
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298 | #endif /* LIBBSP_ARM_TMS570_PLL */ |
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