source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 14.7 KB
Line 
1/* The header file is generated by make_header.py from PLL.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_PLL
40#define LIBBSP_ARM_tms570_PLL
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t PLLCTL3;           /*PLL Control 3 Register*/
46  uint8_t reserved1 [108];
47  uint32_t CLKSLIP;           /*PLL Clock Slip Control Register*/
48  uint8_t reserved2 [7600];
49  uint32_t SSWPLL1;           /*PLL Modulation Depth Measurement Control Register*/
50  uint32_t SSWPLL2;           /*SSW PLL BIST Control Register 2*/
51  uint32_t SSWPLL3;           /*SSW PLL BIST Control Register 3*/
52  uint32_t CSDIS;             /*Clock Source Disable Register*/
53  uint32_t CSDISSET;          /*Clock Source Disable Set Register*/
54  uint32_t CSDISCLR;          /*Clock Source Disable Clear Register*/
55  uint8_t reserved3 [24];
56  uint32_t CSVSTAT;           /*Clock Source Valid Status Register*/
57  uint8_t reserved4 [24];
58  uint32_t PLLCTL1;           /*PLL Control 1 Register*/
59  uint32_t PLLCTL2;           /*PLL Control 2 Register*/
60  uint8_t reserved5 [16];
61  uint32_t LPOMONCTL;         /*LPO/Clock Monitor Control Register*/
62  uint32_t CLKTEST;           /*Clock Test Register*/
63  uint8_t reserved6 [16];
64  uint32_t GPREG1;            /*General Purpose Register*/
65  uint8_t reserved7 [72];
66  uint32_t GLBSTAT;           /*Global Status Register*/
67} tms570_pll_t;
68
69
70/*---------------------TMS570_PLLPLLCTL3---------------------*/
71/* field: ODPLL2 - Internal PLL Output Divider */
72#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
73#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
74#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
75
76/* field: PLLDIV2 - PLL2 Output Clock Divider */
77#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
78#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
79#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
80
81/* field: REFCLKDIV2 - Reference Clock Divider */
82#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
83#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
84#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
85
86/* field: PLLMUL2 - PLL2 Multiplication Factor */
87#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
88#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
89#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
90
91
92/*---------------------TMS570_PLLCLKSLIP---------------------*/
93/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
94#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
95#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
96#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
97
98/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
99#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
100#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
101#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
102
103
104/*---------------------TMS570_PLLSSWPLL1---------------------*/
105/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
106#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
107#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
108#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
109
110/* field: COUNTER_READ_READY - Counter read ready. */
111#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_FLD32(6)
112
113/* field: COUNTER_RESET - Counter reset. */
114#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_FLD32(5)
115
116/* field: COUNTER_EN - Counter enable. */
117#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_FLD32(4)
118
119/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
120#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
121#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
122#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
123
124/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
125#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_FLD32(0)
126
127
128/*---------------------TMS570_PLLSSWPLL2---------------------*/
129/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
130#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
131#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
132#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
133
134
135/*---------------------TMS570_PLLSSWPLL3---------------------*/
136/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
137#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
138#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
139#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
140
141
142/*----------------------TMS570_PLLCSDIS----------------------*/
143/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
144#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
145#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
146#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
147
148/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
149#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
150#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
151#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
152
153
154/*---------------------TMS570_PLLCSDISSET---------------------*/
155/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
156#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
157#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
158#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
159
160/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
161#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
162#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
163#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
164
165
166/*---------------------TMS570_PLLCSDISCLR---------------------*/
167/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
168#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
169#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
170#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
171
172/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
173#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
174#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
175#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
176
177
178/*---------------------TMS570_PLLCSVSTAT---------------------*/
179/* field: CLKSR_7_3V - Clock source[7-0] valid. */
180#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
181#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
182#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
183
184/* field: CLKSR_1_0V - Clock source[1-0] valid. */
185#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
186#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
187#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
188
189
190/*---------------------TMS570_PLLPLLCTL1---------------------*/
191/* field: ROS - Reset on PLL Slip */
192#define TMS570_PLL_PLLCTL1_ROS BSP_FLD32(31)
193
194/* field: MASK_SLIP - Mask detection of PLL slip */
195#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
196#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
197#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
198
199/* field: PLLDIV - PLL Output Clock Divider */
200#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
201#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
202#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
203
204/* field: ROF - Reset on Oscillator Fail */
205#define TMS570_PLL_PLLCTL1_ROF BSP_FLD32(23)
206
207/* field: REFCLKDIV - Reference Clock Divider */
208#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
209#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
210#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
211
212/* field: PLLMUL - PLL Multiplication Factor */
213#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
214#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
215#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
216
217
218/*---------------------TMS570_PLLPLLCTL2---------------------*/
219/* field: FMENA - Frequency Modulation Enable. */
220#define TMS570_PLL_PLLCTL2_FMENA BSP_FLD32(31)
221
222/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
223#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
224#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
225#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
226
227/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
228#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
229#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
230#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
231
232/* field: ODPLL - Internal PLL Output Divider. */
233#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
234#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
235#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
236
237/* field: SPR_AMOUNT - Spreading Amount. */
238#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
239#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
240#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
241
242
243/*--------------------TMS570_PLLLPOMONCTL--------------------*/
244/* field: BIAS_ENABLE - Bias enable. */
245#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
246
247/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
248#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
249
250/* field: HFTRIM - High frequency oscillator trim value. */
251#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
252#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
253#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
254
255
256/*---------------------TMS570_PLLCLKTEST---------------------*/
257/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
258#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
259
260/* field: RANGEDETCTRL - Range detection control. */
261#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
262
263/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
264#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
265
266/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
267#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
268#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
269#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
270
271
272/*----------------------TMS570_PLLGPREG1----------------------*/
273/* field: EMIF_FUNC - Enable EMIF functions to be output. */
274#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_FLD32(31)
275
276/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
277#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
278#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
279#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
280
281/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
282#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
283#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
284#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
285
286/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
287#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
288#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
289#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
290
291
292/*---------------------TMS570_PLLGLBSTAT---------------------*/
293/* field: FBSLIP - PLL over cycle slip detection. */
294#define TMS570_PLL_GLBSTAT_FBSLIP BSP_FLD32(9)
295
296/* field: RFSLIP - PLL under cycle slip detection. */
297#define TMS570_PLL_GLBSTAT_RFSLIP BSP_FLD32(8)
298
299/* field: OSCFAIL - Oscillator fail flag bit. */
300#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_FLD32(0)
301
302
303
304#endif /* LIBBSP_ARM_tms570_PLL */
Note: See TracBrowser for help on using the repository browser.