1 | /* The header file is generated by make_header.py from PBIST.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_tms570_PBIST |
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40 | #define LIBBSP_ARM_tms570_PBIST |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t DNW[88]; /*Reserved DO NOT WRITE*/ |
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46 | uint32_t RAMT; /*RAM Configuration Register*/ |
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47 | uint32_t DLR; /*Datalogger Register*/ |
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48 | uint8_t reserved1 [24]; |
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49 | uint32_t PACT; /*PBIST Activate/ROM Clock Enable Register*/ |
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50 | uint32_t PBISTID; /*PBIST ID Register*/ |
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51 | uint32_t OVER; /*Override Register*/ |
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52 | uint8_t reserved2 [4]; |
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53 | uint32_t FSRF0; /*Fail Status Fail Register 0*/ |
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54 | uint8_t reserved3 [4]; |
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55 | uint32_t FSRC0; /*Fail Status Count Register 0*/ |
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56 | uint32_t FSRC1; /*Fail Status Count Register 1*/ |
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57 | uint32_t FSRA0; /*Fail Status Address 0 Register*/ |
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58 | uint32_t FSRA1; /*Fail Status Address 1 Register*/ |
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59 | uint32_t FSRDL0; /*Fail Status Data Register 0*/ |
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60 | uint8_t reserved4 [4]; |
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61 | uint32_t FSRDL1; /*Fail Status Data Register 1*/ |
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62 | uint8_t reserved5 [12]; |
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63 | uint32_t ROM; /*ROM Mask Register*/ |
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64 | uint32_t ALGO; /*ROM Algorithm Mask Register*/ |
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65 | uint32_t RINFOL; /*RAM Info Mask Lower Register*/ |
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66 | uint32_t RINFOUL; /*RAM Info Mask Lower Register*/ |
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67 | } tms570_pbist_t; |
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68 | |
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69 | |
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70 | /*----------------------TMS570_PBISTDNW----------------------*/ |
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71 | /* field: Reserved - Do not write */ |
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72 | #define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31) |
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73 | #define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31) |
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74 | #define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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75 | |
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76 | |
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77 | /*----------------------TMS570_PBISTRAMT----------------------*/ |
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78 | /* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */ |
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79 | #define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31) |
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80 | #define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31) |
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81 | #define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) |
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82 | |
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83 | /* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */ |
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84 | #define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23) |
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85 | #define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23) |
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86 | #define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) |
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87 | |
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88 | /* field: DWR - Data Width Register */ |
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89 | #define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15) |
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90 | #define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15) |
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91 | #define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
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92 | |
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93 | /* field: SMS - Sense Margin Select Register */ |
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94 | #define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7) |
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95 | #define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7) |
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96 | #define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) |
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97 | |
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98 | /* field: PLS - Pipeline Latency Select */ |
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99 | #define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5) |
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100 | #define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5) |
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101 | #define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5) |
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102 | |
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103 | /* field: RLS - RAM Latency Select */ |
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104 | #define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1) |
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105 | #define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1) |
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106 | #define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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107 | |
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108 | |
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109 | /*----------------------TMS570_PBISTDLR----------------------*/ |
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110 | /* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */ |
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111 | #define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4) |
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112 | |
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113 | /* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */ |
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114 | #define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2) |
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115 | |
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116 | |
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117 | /*----------------------TMS570_PBISTPACT----------------------*/ |
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118 | /* field: PACT1 - PBIST Activate */ |
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119 | #define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1) |
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120 | |
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121 | /* field: PACT0 - ROM Clock Enable Register */ |
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122 | #define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0) |
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123 | |
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124 | |
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125 | /*--------------------TMS570_PBISTPBISTID--------------------*/ |
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126 | /* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */ |
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127 | #define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7) |
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128 | #define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7) |
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129 | #define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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130 | |
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131 | |
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132 | /*----------------------TMS570_PBISTOVER----------------------*/ |
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133 | /* field: OVER0 - RINFO Override Bit */ |
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134 | #define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0) |
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135 | |
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136 | |
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137 | /*---------------------TMS570_PBISTFSRF0---------------------*/ |
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138 | /* field: FSRF0 - Fail Status 0. */ |
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139 | #define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0) |
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140 | |
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141 | |
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142 | /*---------------------TMS570_PBISTFSRC0---------------------*/ |
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143 | /* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */ |
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144 | #define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7) |
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145 | #define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7) |
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146 | #define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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147 | |
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148 | |
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149 | /*---------------------TMS570_PBISTFSRC1---------------------*/ |
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150 | /* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */ |
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151 | #define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7) |
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152 | #define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7) |
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153 | #define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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154 | |
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155 | |
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156 | /*---------------------TMS570_PBISTFSRA0---------------------*/ |
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157 | /* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */ |
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158 | #define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15) |
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159 | #define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15) |
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160 | #define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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161 | |
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162 | |
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163 | /*---------------------TMS570_PBISTFSRA1---------------------*/ |
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164 | /* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */ |
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165 | #define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15) |
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166 | #define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15) |
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167 | #define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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168 | |
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169 | |
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170 | /*---------------------TMS570_PBISTFSRDL0---------------------*/ |
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171 | /* field: FSRDL1 - Failure data on port 1 */ |
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172 | #define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31) |
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173 | #define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31) |
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174 | #define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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175 | |
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176 | |
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177 | /*---------------------TMS570_PBISTFSRDL1---------------------*/ |
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178 | /* field: FSRDL1 - Failure data on port 1 */ |
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179 | #define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31) |
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180 | #define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31) |
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181 | #define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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182 | |
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183 | |
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184 | /*----------------------TMS570_PBISTROM----------------------*/ |
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185 | /* field: ROM - ROM Mask */ |
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186 | #define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1) |
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187 | #define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1) |
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188 | #define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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189 | |
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190 | |
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191 | /*----------------------TMS570_PBISTALGO----------------------*/ |
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192 | /* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */ |
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193 | #define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31) |
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194 | #define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31) |
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195 | #define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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196 | |
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197 | |
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198 | /*---------------------TMS570_PBISTRINFOL---------------------*/ |
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199 | /* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */ |
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200 | #define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31) |
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201 | #define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31) |
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202 | #define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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203 | |
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204 | |
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205 | /*--------------------TMS570_PBISTRINFOUL--------------------*/ |
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206 | /* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */ |
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207 | #define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31) |
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208 | #define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31) |
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209 | #define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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210 | |
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211 | |
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212 | |
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213 | #endif /* LIBBSP_ARM_tms570_PBIST */ |
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