source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 9.7 KB
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1/* The header file is generated by make_header.py from PBIST.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_PBIST
40#define LIBBSP_ARM_tms570_PBIST
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t DNW[88];           /*Reserved DO NOT WRITE*/
46  uint32_t RAMT;              /*RAM Configuration Register*/
47  uint32_t DLR;               /*Datalogger Register*/
48  uint8_t reserved1 [24];
49  uint32_t PACT;              /*PBIST Activate/ROM Clock Enable Register*/
50  uint32_t PBISTID;           /*PBIST ID Register*/
51  uint32_t OVER;              /*Override Register*/
52  uint8_t reserved2 [4];
53  uint32_t FSRF0;             /*Fail Status Fail Register 0*/
54  uint8_t reserved3 [4];
55  uint32_t FSRC0;             /*Fail Status Count Register 0*/
56  uint32_t FSRC1;             /*Fail Status Count Register 1*/
57  uint32_t FSRA0;             /*Fail Status Address 0 Register*/
58  uint32_t FSRA1;             /*Fail Status Address 1 Register*/
59  uint32_t FSRDL0;            /*Fail Status Data Register 0*/
60  uint8_t reserved4 [4];
61  uint32_t FSRDL1;            /*Fail Status Data Register 1*/
62  uint8_t reserved5 [12];
63  uint32_t ROM;               /*ROM Mask Register*/
64  uint32_t ALGO;              /*ROM Algorithm Mask Register*/
65  uint32_t RINFOL;            /*RAM Info Mask Lower Register*/
66  uint32_t RINFOUL;           /*RAM Info Mask Lower Register*/
67} tms570_pbist_t;
68
69
70/*----------------------TMS570_PBISTDNW----------------------*/
71/* field: Reserved - Do not write */
72#define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31)
73#define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
74#define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
75
76
77/*----------------------TMS570_PBISTRAMT----------------------*/
78/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
79#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
80#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
81#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
82
83/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */
84#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23)
85#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23)
86#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
87
88/* field: DWR - Data Width Register */
89#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15)
90#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15)
91#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
92
93/* field: SMS - Sense Margin Select Register */
94#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7)
95#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7)
96#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
97
98/* field: PLS - Pipeline Latency Select */
99#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5)
100#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5)
101#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5)
102
103/* field: RLS - RAM Latency Select */
104#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1)
105#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1)
106#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
107
108
109/*----------------------TMS570_PBISTDLR----------------------*/
110/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
111#define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4)
112
113/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
114#define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2)
115
116
117/*----------------------TMS570_PBISTPACT----------------------*/
118/* field: PACT1 - PBIST Activate */
119#define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1)
120
121/* field: PACT0 - ROM Clock Enable Register */
122#define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0)
123
124
125/*--------------------TMS570_PBISTPBISTID--------------------*/
126/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
127#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
128#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
129#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
130
131
132/*----------------------TMS570_PBISTOVER----------------------*/
133/* field: OVER0 - RINFO Override Bit */
134#define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0)
135
136
137/*---------------------TMS570_PBISTFSRF0---------------------*/
138/* field: FSRF0 - Fail Status 0. */
139#define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0)
140
141
142/*---------------------TMS570_PBISTFSRC0---------------------*/
143/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
144#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
145#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
146#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
147
148
149/*---------------------TMS570_PBISTFSRC1---------------------*/
150/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
151#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
152#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
153#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
154
155
156/*---------------------TMS570_PBISTFSRA0---------------------*/
157/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
158#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
159#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
160#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
161
162
163/*---------------------TMS570_PBISTFSRA1---------------------*/
164/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
165#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
166#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
167#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
168
169
170/*---------------------TMS570_PBISTFSRDL0---------------------*/
171/* field: FSRDL1 - Failure data on port 1 */
172#define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31)
173#define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
174#define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
175
176
177/*---------------------TMS570_PBISTFSRDL1---------------------*/
178/* field: FSRDL1 - Failure data on port 1 */
179#define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31)
180#define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
181#define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
182
183
184/*----------------------TMS570_PBISTROM----------------------*/
185/* field: ROM - ROM Mask */
186#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
187#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
188#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
189
190
191/*----------------------TMS570_PBISTALGO----------------------*/
192/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
193#define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31)
194#define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31)
195#define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
196
197
198/*---------------------TMS570_PBISTRINFOL---------------------*/
199/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
200#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31)
201#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31)
202#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
203
204
205/*--------------------TMS570_PBISTRINFOUL--------------------*/
206/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
207#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31)
208#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31)
209#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
210
211
212
213#endif /* LIBBSP_ARM_tms570_PBIST */
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