1 | /* The header file is generated by make_header.py from HTU.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_tms570_HTU |
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40 | #define LIBBSP_ARM_tms570_HTU |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t GC; /*Global Control Register*/ |
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46 | uint32_t CPENA; /*Control Packet Enable Register*/ |
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47 | uint32_t BUSY0; /*Control Packet Busy Register 0*/ |
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48 | uint32_t BUSY1; /*Control Packet Busy Register 1*/ |
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49 | uint32_t BUSY2; /*Control Packet Busy Register 2*/ |
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50 | uint32_t BUSY3; /*Control Packet Busy Register 3*/ |
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51 | uint32_t ACPE; /*Active Control Packet and Error Register*/ |
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52 | uint8_t reserved1 [4]; |
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53 | uint32_t RLBECTRL; /*Request Lost and Bus Error Control Register*/ |
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54 | uint32_t BFINTS; /*Buffer Full Interrupt Enable Set Register*/ |
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55 | uint32_t BFINTC; /*Buffer Full Interrupt Enable Clear Register*/ |
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56 | uint8_t reserved2 [8]; |
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57 | uint32_t INTOFF0; /*Interrupt Offset Register 0*/ |
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58 | uint32_t INTOFF1; /*Interrupt Offset Register 1*/ |
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59 | uint32_t BIM; /*Buffer Initialization Mode Register*/ |
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60 | uint32_t RLOSTFL; /*Request Lost Flag Register*/ |
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61 | uint32_t BFINTFL; /*Buffer Full Interrupt Flag Register*/ |
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62 | uint32_t BERINTFL; /*BER Interrupt Flag Register*/ |
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63 | uint32_t MP1S; /*Memory Protection 1 Start Address Register*/ |
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64 | uint32_t MP1E; /*Memory Protection 1 End Address Register*/ |
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65 | uint32_t DCTRL; /*Debug Control Register*/ |
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66 | uint32_t WPR; /*Watch Point Register*/ |
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67 | uint32_t WMR; /*Watch Mask Register*/ |
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68 | uint32_t ID; /*Module Identification Register*/ |
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69 | uint32_t PCR; /*Parity Control Register*/ |
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70 | uint32_t PAR; /*Parity Address Register*/ |
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71 | uint8_t reserved3 [4]; |
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72 | uint32_t MPCS; /*Memory Protection Control and Status Register*/ |
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73 | uint32_t MP0S; /*Memory Protection 0 Start Address Register*/ |
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74 | uint32_t MP0E; /*Memory Protection 0 End Address Register*/ |
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75 | } tms570_htu_t; |
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76 | |
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77 | |
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78 | /*------------------------TMS570_HTUGC------------------------*/ |
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79 | /* field: VBUSHOLD - Hold the VBUS bus */ |
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80 | #define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24) |
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81 | |
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82 | /* field: HTUEN - Transfer Unit Enable Bit */ |
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83 | #define TMS570_HTU_GC_HTUEN BSP_FLD32(16) |
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84 | |
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85 | /* field: DEBM - Debug Mode */ |
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86 | #define TMS570_HTU_GC_DEBM BSP_FLD32(8) |
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87 | |
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88 | /* field: HTURES - HTU Software Reset Request */ |
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89 | #define TMS570_HTU_GC_HTURES BSP_FLD32(0) |
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90 | |
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91 | |
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92 | /*----------------------TMS570_HTUCPENA----------------------*/ |
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93 | /* field: CPENA - CP Enable Bits */ |
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94 | #define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15) |
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95 | #define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15) |
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96 | #define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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97 | |
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98 | |
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99 | /*----------------------TMS570_HTUBUSY0----------------------*/ |
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100 | /* field: BUSY0A - Busy Flag for CP A of DCP 0 */ |
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101 | #define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24) |
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102 | |
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103 | /* field: BUSY0B - Busy Flag for CP B of DCP 0 */ |
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104 | #define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16) |
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105 | |
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106 | /* field: BUSY1A - Busy Flag for CP A of DCP 1 */ |
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107 | #define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8) |
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108 | |
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109 | /* field: BUSY1B - Busy Flag for CP B of DCP 1 */ |
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110 | #define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0) |
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111 | |
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112 | |
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113 | /*----------------------TMS570_HTUBUSY1----------------------*/ |
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114 | /* field: BUSY2A - Busy Flag for CP A of DCP 2 */ |
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115 | #define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24) |
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116 | |
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117 | /* field: BUSY2B - Busy Flag for CP B of DCP 2 */ |
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118 | #define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16) |
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119 | |
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120 | /* field: BUSY3A - Busy Flag for CP A of DCP 3 */ |
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121 | #define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8) |
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122 | |
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123 | /* field: BUSY3B - Busy Flag for CP B of DCP 3 */ |
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124 | #define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0) |
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125 | |
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126 | |
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127 | /*----------------------TMS570_HTUBUSY2----------------------*/ |
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128 | /* field: BUSY4A - Busy Flag for CP A of DCP 4 */ |
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129 | #define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24) |
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130 | |
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131 | /* field: BUSY4B - Busy Flag for CP B of DCP 4 */ |
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132 | #define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16) |
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133 | |
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134 | /* field: BUSY5A - Busy Flag for CP A of DCP 5 */ |
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135 | #define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8) |
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136 | |
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137 | /* field: BUSY5B - Busy Flag for CP B of DCP 5 */ |
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138 | #define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0) |
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139 | |
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140 | |
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141 | /*----------------------TMS570_HTUBUSY3----------------------*/ |
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142 | /* field: BUSY6A - Busy Flag for CP A of DCP 6 */ |
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143 | #define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24) |
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144 | |
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145 | /* field: BUSY6B - Busy Flag for CP B of DCP 6 */ |
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146 | #define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16) |
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147 | |
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148 | /* field: BUSY7A - Busy Flag for CP A of DCP 7 */ |
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149 | #define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8) |
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150 | |
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151 | /* field: BUSY7B - Busy Flag for CP B of DCP 7 */ |
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152 | #define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0) |
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153 | |
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154 | |
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155 | /*-----------------------TMS570_HTUACPE-----------------------*/ |
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156 | /* field: ERRF - Error Flag */ |
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157 | #define TMS570_HTU_ACPE_ERRF BSP_FLD32(31) |
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158 | |
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159 | |
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160 | /*---------------------TMS570_HTURLBECTRL---------------------*/ |
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161 | /* field: BERINTENA - Bus Error Interrupt Enable Bit */ |
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162 | #define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16) |
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163 | |
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164 | /* field: CORL - Continue On Request Lost Error */ |
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165 | #define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8) |
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166 | |
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167 | /* field: RLINTENA - Request Lost Interrupt Enable Bit */ |
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168 | #define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0) |
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169 | |
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170 | |
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171 | /*----------------------TMS570_HTUBFINTS----------------------*/ |
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172 | /* field: BFINTENA - Bus Full Interrupt Enable Bits. */ |
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173 | #define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15) |
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174 | #define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) |
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175 | #define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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176 | |
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177 | |
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178 | /*----------------------TMS570_HTUBFINTC----------------------*/ |
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179 | /* field: BFINTDIS - */ |
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180 | #define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15) |
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181 | #define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) |
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182 | #define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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183 | |
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184 | |
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185 | /*---------------------TMS570_HTUINTOFF0---------------------*/ |
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186 | /* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */ |
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187 | #define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10) |
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188 | #define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10) |
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189 | #define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) |
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190 | |
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191 | /* field: CPOFF0 - CP Offset. */ |
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192 | #define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4) |
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193 | #define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4) |
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194 | #define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) |
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195 | |
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196 | |
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197 | /*---------------------TMS570_HTUINTOFF1---------------------*/ |
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198 | /* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */ |
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199 | #define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10) |
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200 | #define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10) |
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201 | #define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) |
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202 | |
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203 | /* field: CPOFF1 - CP Offset. */ |
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204 | #define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4) |
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205 | #define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4) |
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206 | #define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) |
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207 | |
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208 | |
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209 | /*-----------------------TMS570_HTUBIM-----------------------*/ |
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210 | /* field: BIM - Buffer Initialization Mode */ |
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211 | #define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7) |
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212 | #define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7) |
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213 | #define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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214 | |
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215 | |
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216 | /*---------------------TMS570_HTURLOSTFL---------------------*/ |
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217 | /* field: CPRLFL - CP Request Lost Flags */ |
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218 | #define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15) |
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219 | #define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15) |
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220 | #define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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221 | |
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222 | |
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223 | /*---------------------TMS570_HTUBFINTFL---------------------*/ |
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224 | /* field: BFINTFL - Buffer Full Interrupt Flags */ |
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225 | #define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15) |
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226 | #define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) |
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227 | #define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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228 | |
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229 | |
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230 | /*---------------------TMS570_HTUBERINTFL---------------------*/ |
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231 | /* field: BERINTFL - Bus Error Interrupt Flags */ |
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232 | #define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15) |
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233 | #define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) |
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234 | #define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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235 | |
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236 | |
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237 | /*-----------------------TMS570_HTUMP1S-----------------------*/ |
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238 | /* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */ |
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239 | #define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31) |
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240 | #define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31) |
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241 | #define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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242 | |
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243 | |
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244 | /*-----------------------TMS570_HTUMP1E-----------------------*/ |
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245 | /* field: ENDADDRESS1 - The end address defines at which address the region ends. */ |
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246 | #define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31) |
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247 | #define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31) |
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248 | #define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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249 | |
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250 | |
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251 | /*----------------------TMS570_HTUDCTRL----------------------*/ |
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252 | /* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */ |
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253 | #define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27) |
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254 | #define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27) |
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255 | #define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
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256 | |
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257 | /* field: HTUDBGS - HTU Debug Status. */ |
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258 | #define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16) |
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259 | |
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260 | /* field: DBREN - Debug Request Enable */ |
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261 | #define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0) |
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262 | |
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263 | |
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264 | /*-----------------------TMS570_HTUWPR-----------------------*/ |
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265 | /* field: WP - Watch Point Register */ |
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266 | #define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31) |
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267 | #define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31) |
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268 | #define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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269 | |
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270 | |
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271 | /*-----------------------TMS570_HTUWMR-----------------------*/ |
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272 | /* field: WM - Watch Mask Register */ |
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273 | #define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31) |
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274 | #define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31) |
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275 | #define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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276 | |
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277 | |
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278 | /*------------------------TMS570_HTUID------------------------*/ |
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279 | /* field: CLASS - Module Class */ |
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280 | #define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23) |
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281 | #define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23) |
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282 | #define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) |
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283 | |
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284 | /* field: TYPE - Subtype within a Class */ |
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285 | #define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15) |
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286 | #define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15) |
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287 | #define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) |
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288 | |
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289 | /* field: REV - Module Revision Number */ |
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290 | #define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7) |
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291 | #define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7) |
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292 | #define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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293 | |
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294 | |
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295 | /*-----------------------TMS570_HTUPCR-----------------------*/ |
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296 | /* field: COPE - Continue on Parity Error */ |
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297 | #define TMS570_HTU_PCR_COPE BSP_FLD32(16) |
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298 | |
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299 | /* field: TEST - Test. */ |
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300 | #define TMS570_HTU_PCR_TEST BSP_FLD32(8) |
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301 | |
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302 | /* field: PARITY_ENA - Enable/Disable Parity Checking. */ |
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303 | #define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) |
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304 | #define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) |
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305 | #define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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306 | |
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307 | |
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308 | /*-----------------------TMS570_HTUPAR-----------------------*/ |
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309 | /* field: PEFT - Parity Error Fault Flag. */ |
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310 | #define TMS570_HTU_PAR_PEFT BSP_FLD32(16) |
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311 | |
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312 | /* field: PAOFF - PAOFF */ |
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313 | #define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8) |
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314 | #define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8) |
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315 | #define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) |
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316 | |
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317 | |
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318 | /*-----------------------TMS570_HTUMPCS-----------------------*/ |
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319 | /* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */ |
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320 | #define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27) |
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321 | #define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27) |
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322 | #define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
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323 | |
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324 | /* field: MPEFT1 - MPEFT1 */ |
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325 | #define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17) |
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326 | |
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327 | /* field: MPEFT0 - Memory Protection Error Fault Flag 0. */ |
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328 | #define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16) |
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329 | |
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330 | /* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */ |
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331 | #define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11) |
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332 | #define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11) |
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333 | #define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) |
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334 | |
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335 | |
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336 | /*-----------------------TMS570_HTUMP0S-----------------------*/ |
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337 | /* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */ |
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338 | #define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31) |
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339 | #define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31) |
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340 | #define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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341 | |
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342 | |
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343 | /*-----------------------TMS570_HTUMP0E-----------------------*/ |
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344 | /* field: ENDADDRESS0 - The end address defines at which address the region ends. */ |
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345 | #define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31) |
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346 | #define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31) |
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347 | #define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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348 | |
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349 | |
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350 | |
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351 | #endif /* LIBBSP_ARM_tms570_HTU */ |
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