source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 14.7 KB
Line 
1/* The header file is generated by make_header.py from HTU.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_HTU
40#define LIBBSP_ARM_tms570_HTU
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t GC;                /*Global Control Register*/
46  uint32_t CPENA;             /*Control Packet Enable Register*/
47  uint32_t BUSY0;             /*Control Packet Busy Register 0*/
48  uint32_t BUSY1;             /*Control Packet Busy Register 1*/
49  uint32_t BUSY2;             /*Control Packet Busy Register 2*/
50  uint32_t BUSY3;             /*Control Packet Busy Register 3*/
51  uint32_t ACPE;              /*Active Control Packet and Error Register*/
52  uint8_t reserved1 [4];
53  uint32_t RLBECTRL;          /*Request Lost and Bus Error Control Register*/
54  uint32_t BFINTS;            /*Buffer Full Interrupt Enable Set Register*/
55  uint32_t BFINTC;            /*Buffer Full Interrupt Enable Clear Register*/
56  uint8_t reserved2 [8];
57  uint32_t INTOFF0;           /*Interrupt Offset Register 0*/
58  uint32_t INTOFF1;           /*Interrupt Offset Register 1*/
59  uint32_t BIM;               /*Buffer Initialization Mode Register*/
60  uint32_t RLOSTFL;           /*Request Lost Flag Register*/
61  uint32_t BFINTFL;           /*Buffer Full Interrupt Flag Register*/
62  uint32_t BERINTFL;          /*BER Interrupt Flag Register*/
63  uint32_t MP1S;              /*Memory Protection 1 Start Address Register*/
64  uint32_t MP1E;              /*Memory Protection 1 End Address Register*/
65  uint32_t DCTRL;             /*Debug Control Register*/
66  uint32_t WPR;               /*Watch Point Register*/
67  uint32_t WMR;               /*Watch Mask Register*/
68  uint32_t ID;                /*Module Identification Register*/
69  uint32_t PCR;               /*Parity Control Register*/
70  uint32_t PAR;               /*Parity Address Register*/
71  uint8_t reserved3 [4];
72  uint32_t MPCS;              /*Memory Protection Control and Status Register*/
73  uint32_t MP0S;              /*Memory Protection 0 Start Address Register*/
74  uint32_t MP0E;              /*Memory Protection 0 End Address Register*/
75} tms570_htu_t;
76
77
78/*------------------------TMS570_HTUGC------------------------*/
79/* field: VBUSHOLD - Hold the VBUS bus */
80#define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24)
81
82/* field: HTUEN - Transfer Unit Enable Bit */
83#define TMS570_HTU_GC_HTUEN BSP_FLD32(16)
84
85/* field: DEBM - Debug Mode */
86#define TMS570_HTU_GC_DEBM BSP_FLD32(8)
87
88/* field: HTURES - HTU Software Reset Request */
89#define TMS570_HTU_GC_HTURES BSP_FLD32(0)
90
91
92/*----------------------TMS570_HTUCPENA----------------------*/
93/* field: CPENA - CP Enable Bits */
94#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
95#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
96#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
97
98
99/*----------------------TMS570_HTUBUSY0----------------------*/
100/* field: BUSY0A - Busy Flag for CP A of DCP 0 */
101#define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24)
102
103/* field: BUSY0B - Busy Flag for CP B of DCP 0 */
104#define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16)
105
106/* field: BUSY1A - Busy Flag for CP A of DCP 1 */
107#define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8)
108
109/* field: BUSY1B - Busy Flag for CP B of DCP 1 */
110#define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0)
111
112
113/*----------------------TMS570_HTUBUSY1----------------------*/
114/* field: BUSY2A - Busy Flag for CP A of DCP 2 */
115#define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24)
116
117/* field: BUSY2B - Busy Flag for CP B of DCP 2 */
118#define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16)
119
120/* field: BUSY3A - Busy Flag for CP A of DCP 3 */
121#define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8)
122
123/* field: BUSY3B - Busy Flag for CP B of DCP 3 */
124#define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0)
125
126
127/*----------------------TMS570_HTUBUSY2----------------------*/
128/* field: BUSY4A - Busy Flag for CP A of DCP 4 */
129#define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24)
130
131/* field: BUSY4B - Busy Flag for CP B of DCP 4 */
132#define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16)
133
134/* field: BUSY5A - Busy Flag for CP A of DCP 5 */
135#define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8)
136
137/* field: BUSY5B - Busy Flag for CP B of DCP 5 */
138#define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0)
139
140
141/*----------------------TMS570_HTUBUSY3----------------------*/
142/* field: BUSY6A - Busy Flag for CP A of DCP 6 */
143#define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24)
144
145/* field: BUSY6B - Busy Flag for CP B of DCP 6 */
146#define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16)
147
148/* field: BUSY7A - Busy Flag for CP A of DCP 7 */
149#define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8)
150
151/* field: BUSY7B - Busy Flag for CP B of DCP 7 */
152#define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0)
153
154
155/*-----------------------TMS570_HTUACPE-----------------------*/
156/* field: ERRF - Error Flag */
157#define TMS570_HTU_ACPE_ERRF BSP_FLD32(31)
158
159
160/*---------------------TMS570_HTURLBECTRL---------------------*/
161/* field: BERINTENA - Bus Error Interrupt Enable Bit */
162#define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16)
163
164/* field: CORL - Continue On Request Lost Error */
165#define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8)
166
167/* field: RLINTENA - Request Lost Interrupt Enable Bit */
168#define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0)
169
170
171/*----------------------TMS570_HTUBFINTS----------------------*/
172/* field: BFINTENA - Bus Full Interrupt Enable Bits. */
173#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
174#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
175#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
176
177
178/*----------------------TMS570_HTUBFINTC----------------------*/
179/* field: BFINTDIS -  */
180#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
181#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
182#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
183
184
185/*---------------------TMS570_HTUINTOFF0---------------------*/
186/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
187#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
188#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
189#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
190
191/* field: CPOFF0 - CP Offset. */
192#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4)
193#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4)
194#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
195
196
197/*---------------------TMS570_HTUINTOFF1---------------------*/
198/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
199#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
200#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
201#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
202
203/* field: CPOFF1 - CP Offset. */
204#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4)
205#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4)
206#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
207
208
209/*-----------------------TMS570_HTUBIM-----------------------*/
210/* field: BIM - Buffer Initialization Mode */
211#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
212#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
213#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
214
215
216/*---------------------TMS570_HTURLOSTFL---------------------*/
217/* field: CPRLFL - CP Request Lost Flags */
218#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
219#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
220#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
221
222
223/*---------------------TMS570_HTUBFINTFL---------------------*/
224/* field: BFINTFL - Buffer Full Interrupt Flags */
225#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
226#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
227#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
228
229
230/*---------------------TMS570_HTUBERINTFL---------------------*/
231/* field: BERINTFL - Bus Error Interrupt Flags */
232#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
233#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
234#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
235
236
237/*-----------------------TMS570_HTUMP1S-----------------------*/
238/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
239#define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31)
240#define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
241#define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
242
243
244/*-----------------------TMS570_HTUMP1E-----------------------*/
245/* field: ENDADDRESS1 - The end address defines at which address the region ends. */
246#define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31)
247#define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
248#define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
249
250
251/*----------------------TMS570_HTUDCTRL----------------------*/
252/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
253#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
254#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
255#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
256
257/* field: HTUDBGS - HTU Debug Status. */
258#define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16)
259
260/* field: DBREN - Debug Request Enable */
261#define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0)
262
263
264/*-----------------------TMS570_HTUWPR-----------------------*/
265/* field: WP - Watch Point Register */
266#define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31)
267#define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
268#define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
269
270
271/*-----------------------TMS570_HTUWMR-----------------------*/
272/* field: WM - Watch Mask Register */
273#define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31)
274#define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
275#define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
276
277
278/*------------------------TMS570_HTUID------------------------*/
279/* field: CLASS - Module Class */
280#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
281#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
282#define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
283
284/* field: TYPE - Subtype within a Class */
285#define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15)
286#define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
287#define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
288
289/* field: REV - Module Revision Number */
290#define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7)
291#define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7)
292#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
293
294
295/*-----------------------TMS570_HTUPCR-----------------------*/
296/* field: COPE - Continue on Parity Error */
297#define TMS570_HTU_PCR_COPE BSP_FLD32(16)
298
299/* field: TEST - Test. */
300#define TMS570_HTU_PCR_TEST BSP_FLD32(8)
301
302/* field: PARITY_ENA - Enable/Disable Parity Checking. */
303#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
304#define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
305#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
306
307
308/*-----------------------TMS570_HTUPAR-----------------------*/
309/* field: PEFT - Parity Error Fault Flag. */
310#define TMS570_HTU_PAR_PEFT BSP_FLD32(16)
311
312/* field: PAOFF - PAOFF */
313#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
314#define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8)
315#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
316
317
318/*-----------------------TMS570_HTUMPCS-----------------------*/
319/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
320#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
321#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
322#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
323
324/* field: MPEFT1 - MPEFT1 */
325#define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17)
326
327/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
328#define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16)
329
330/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
331#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
332#define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11)
333#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
334
335
336/*-----------------------TMS570_HTUMP0S-----------------------*/
337/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
338#define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31)
339#define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
340#define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
341
342
343/*-----------------------TMS570_HTUMP0E-----------------------*/
344/* field: ENDADDRESS0 - The end address defines at which address the region ends. */
345#define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31)
346#define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
347#define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
348
349
350
351#endif /* LIBBSP_ARM_tms570_HTU */
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