source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 10.0 KB
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1/* The header file is generated by make_header.py from ESM.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_ESM
40#define LIBBSP_ARM_tms570_ESM
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t EEPAPR1;           /*ESM Enable ERROR Pin Action/Response Register 1*/
46  uint32_t DEPAPR1;           /*ESM Disable ERROR Pin Action/Response Register 1*/
47  uint32_t IESR1;             /*ESM Interrupt Enable Set/Status Register 1*/
48  uint32_t IECR1;             /*ESM Interrupt Enable Clear/Status Register 1*/
49  uint32_t ILSR1;             /*Interrupt Level Set/Status Register 1*/
50  uint32_t ILCR1;             /*Interrupt Level Clear/Status Register 1*/
51  uint32_t SR[3];             /*ESM Status Register*/
52  uint32_t EPSR;              /*ESM ERROR Pin Status Register*/
53  uint32_t IOFFHR;            /*ESM Interrupt Offset High Register*/
54  uint32_t IOFFLR;            /*ESM Interrupt Offset Low Register*/
55  uint32_t LTCR;              /*ESM Low-Time Counter Register*/
56  uint32_t LTCPR;             /*ESM Low-Time Counter Preload Register*/
57  uint32_t EKR;               /*ESM Error Key Register*/
58  uint32_t SSR2;              /*ESM Status Shadow Register 2*/
59  uint32_t IEPSR4;            /*ESM Influence ERROR Pin Set/Status Register 4*/
60  uint32_t IEPCR4;            /*ESM Influence ERROR Pin Clear/Status Register 4*/
61  uint32_t IESR4;             /*ESM Interrupt Enable Set/Status Register 4*/
62  uint32_t IECR4;             /*ESM Interrupt Enable Clear/Status Register 4*/
63  uint32_t ILSR4;             /*Interrupt Level Set/Status Register 4*/
64  uint32_t ILCR4;             /*Interrupt Level Clear/Status Register 4*/
65  uint32_t SR4;               /*ESM Status Register 4*/
66} tms570_esm_t;
67
68
69/*---------------------TMS570_ESMEEPAPR1---------------------*/
70/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
71#define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
72#define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
73#define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
74
75
76/*---------------------TMS570_ESMDEPAPR1---------------------*/
77/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
78#define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
79#define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
80#define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
81
82
83/*----------------------TMS570_ESMIESR1----------------------*/
84/* field: INTENSET - Set interrupt Enable */
85#define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
86#define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
87#define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
88
89
90/*----------------------TMS570_ESMIECR1----------------------*/
91/* field: INTENCLR - Clear Interrupt Enable */
92#define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
93#define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
94#define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
95
96
97/*----------------------TMS570_ESMILSR1----------------------*/
98/* field: INTLVLSET - Set Interrupt Priority */
99#define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
100#define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
101#define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
102
103
104/*----------------------TMS570_ESMILCR1----------------------*/
105/* field: INTLVLCLR - Clear Interrupt Priority. */
106#define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
107#define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
108#define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
109
110
111/*------------------------TMS570_ESMSR------------------------*/
112/* field: ESF - Error Status Flag. Provides status information on a pending error. */
113#define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
114#define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
115#define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
116
117
118/*-----------------------TMS570_ESMEPSR-----------------------*/
119/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
120#define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
121
122
123/*----------------------TMS570_ESMIOFFHR----------------------*/
124/* field: INTOFFH - Offset High Level Interrupt. */
125#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
126#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6)
127#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
128
129
130/*----------------------TMS570_ESMIOFFLR----------------------*/
131/* field: INTOFFL - Offset Low Level Interrupt. */
132#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
133#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6)
134#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
135
136
137/*-----------------------TMS570_ESMLTCR-----------------------*/
138/* field: LTC - ERROR Pin Low-Time Counter */
139#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
140#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15)
141#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
142
143
144/*----------------------TMS570_ESMLTCPR----------------------*/
145/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
146#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
147#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15)
148#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
149
150
151/*-----------------------TMS570_ESMEKR-----------------------*/
152/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
153#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
154#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
155#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
156
157
158/*-----------------------TMS570_ESMSSR2-----------------------*/
159/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
160#define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
161#define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
162#define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
163
164
165/*----------------------TMS570_ESMIEPSR4----------------------*/
166/* field: IEPSET - Set Influence on ERROR Pin */
167#define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
168#define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
169#define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
170
171
172/*----------------------TMS570_ESMIEPCR4----------------------*/
173/* field: IEPCLR - Clear Influence on ERROR Pin */
174#define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
175#define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
176#define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
177
178
179/*----------------------TMS570_ESMIESR4----------------------*/
180/* field: INTENSET - Set Interrupt Enable */
181#define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
182#define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
183#define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
184
185
186/*----------------------TMS570_ESMIECR4----------------------*/
187/* field: INTENCLR - Clear Interrupt Enable */
188#define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
189#define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
190#define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
191
192
193/*----------------------TMS570_ESMILSR4----------------------*/
194/* field: INTLVLSET - Set Interrupt Level */
195#define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
196#define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
197#define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
198
199
200/*----------------------TMS570_ESMILCR4----------------------*/
201/* field: INTLVLCLR - Clear Interrupt Level */
202#define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
203#define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
204#define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
205
206
207/*-----------------------TMS570_ESMSR4-----------------------*/
208/* field: ESF - Error Status Flag. Provides status information on a pending error. */
209#define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
210#define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
211#define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
212
213
214
215#endif /* LIBBSP_ARM_tms570_ESM */
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