source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h @ e56090ef

5
Last change on this file since e56090ef was d6c67ad5, checked in by Premysl Houdek <kom541000@…>, on 07/17/15 at 15:04:05

bsp/tms570: skipped 32bit field definitions and corrected single bit fields

there is no need to define access macros for field covering
whole registers. In addition, BSP_FLD32 does not work right
for field 32bit length.

Signed-off-by: Premysl Houdek <kom541000@…>
  • Property mode set to 100644
File size: 44.0 KB
Line 
1/* The header file is generated by make_header.py from EMACM.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_EMACM
40#define LIBBSP_ARM_TMS570_EMACM
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t TXREVID;           /*Transmit Revision ID Register*/
46  uint32_t TXCONTROL;         /*Transmit Control Register*/
47  uint32_t TXTEARDOWN;        /*Transmit Teardown Register*/
48  uint8_t reserved1 [4];
49  uint32_t RXREVID;           /*Receive Revision ID Register*/
50  uint32_t RXCONTROL;         /*Receive Control Register*/
51  uint32_t RXTEARDOWN;        /*Receive Teardown Register*/
52  uint8_t reserved2 [100];
53  uint32_t TXINTSTATRAW;      /*Transmit Interrupt Status (Unmasked) Register*/
54  uint32_t TXINTSTATMASKED;   /*Transmit Interrupt Status (Masked) Register*/
55  uint32_t TXINTMASKSET;      /*Transmit Interrupt Mask Set Register*/
56  uint32_t TXINTMASKCLEAR;    /*Transmit Interrupt Clear Register*/
57  uint32_t MACINVECTOR;       /*MAC Input Vector Register*/
58  uint32_t MACEOIVECTOR;      /*MAC End Of Interrupt Vector Register*/
59  uint8_t reserved3 [8];
60  uint32_t RXINTSTATRAW;      /*Receive Interrupt Status (Unmasked) Register*/
61  uint32_t RXINTSTATMASKED;   /*Receive Interrupt Status (Masked) Register*/
62  uint32_t RXINTMASKSET;      /*Receive Interrupt Mask Set Register*/
63  uint32_t RXINTMASKCLEAR;    /*Receive Interrupt Mask Clear Register*/
64  uint32_t MACINTSTATRAW;     /*MAC Interrupt Status (Unmasked) Register*/
65  uint32_t MACINTSTATMASKED;  /*MAC Interrupt Status (Masked) Register*/
66  uint32_t MACINTMASKSET;     /*MAC Interrupt Mask Set Register*/
67  uint32_t MACINTMASKCLEAR;   /*MAC Interrupt Mask Clear Register*/
68  uint8_t reserved4 [64];
69  uint32_t RXMBPENABLE;       /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/
70  uint32_t RXUNICASTSET;      /*Receive Unicast Enable Set Register*/
71  uint32_t RXUNICASTCLEAR;    /*Receive Unicast Clear Register*/
72  uint32_t RXMAXLEN;          /*Receive Maximum Length Register*/
73  uint32_t RXBUFFEROFFSET;    /*Receive Buffer Offset Register*/
74  uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/
75  uint8_t reserved5 [8];
76  uint32_t RXFLOWTHRESH[8];   /*Receive Channel Flow Control Threshold Register*/
77  uint32_t RXFREEBUFFER[8];   /*Receive Channel Free Buffer Count Register*/
78  uint32_t MACCONTROL;        /*MAC Control Register*/
79  uint32_t MACSTATUS;         /*MAC Status Register*/
80  uint32_t EMCONTROL;         /*Emulation Control Register*/
81  uint32_t FIFOCONTROL;       /*FIFO Control Register*/
82  uint32_t MACCONFIG;         /*MAC Configuration Register*/
83  uint32_t SOFTRESET;         /*Soft Reset Register*/
84  uint8_t reserved6 [88];
85  uint32_t MACSRCADDRLO;      /*MAC Source Address Low Bytes Register*/
86  uint32_t MACSRCADDRHI;      /*MAC Source Address High Bytes Register*/
87  uint32_t MACHASH1;          /*MAC Hash Address Register 1*/
88  uint32_t MACHASH2;          /*MAC Hash Address Register 2*/
89  uint32_t BOFFTEST;          /*Back Off Test Register*/
90  uint32_t TPACETEST;         /*Transmit Pacing Algorithm Test Register*/
91  uint32_t RXPAUSE;           /*Receive Pause Timer Register*/
92  uint32_t TXPAUSE;           /*Transmit Pause Timer Register*/
93  uint8_t reserved7 [784];
94  uint32_t MACADDRLO;         /*MAC Address Low Bytes Register*/
95  uint32_t MACADDRHI;         /*MAC Address High Bytes Register*/
96  uint32_t MACINDEX;          /*MAC Index Register*/
97  uint8_t reserved8 [244];
98  uint32_t TXHDP[8];          /*Transmit Channel DMA Head Descriptor Pointer Register*/
99  uint32_t RXHDP[8];          /*Receive Channel DMA Head Descriptor Pointer Register*/
100  uint32_t TXCP[8];           /*Transmit Channel Completion Pointer Register*/
101  uint32_t RXCP[8];           /*Receive Channel Completion Pointer Register*/
102} tms570_emacm_t;
103
104
105/*--------------------TMS570_EMACM_TXREVID--------------------*/
106/* field: TXREV - Transmit module revision */
107/* Whole 32 bits */
108
109/*-------------------TMS570_EMACM_TXCONTROL-------------------*/
110/* field: TXEN - Transmit enable */
111#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
112
113
114/*------------------TMS570_EMACM_TXTEARDOWN------------------*/
115/* field: TXTDNCH - Transmit teardown channel. */
116#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
117#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
118#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
119
120
121/*--------------------TMS570_EMACM_RXREVID--------------------*/
122/* field: RXREV - Receive module revision */
123/* Whole 32 bits */
124
125/*-------------------TMS570_EMACM_RXCONTROL-------------------*/
126/* field: RXEN - Receive enable */
127#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
128
129
130/*------------------TMS570_EMACM_RXTEARDOWN------------------*/
131/* field: RXTDNCH - Receive teardown channel. */
132#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
133#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
134#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
135
136
137/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
138/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
139#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
140
141/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
142#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
143
144/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
145#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
146
147/* field: TX4PEND - X4PEND raw interrupt read (before mask) */
148#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
149
150/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
151#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
152
153/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
154#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
155
156/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
157#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
158
159/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
160#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
161
162
163/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
164/* field: TX7PEND - TX7PEND masked interrupt read */
165#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
166
167/* field: TX6PEND - TX6PEND masked interrupt read */
168#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
169
170/* field: TX5PEND - TX5PEND masked interrupt read */
171#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
172
173/* field: TX4PEND - TX4PEND masked interrupt read */
174#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
175
176/* field: TX3PEND - TX3PEND masked interrupt read */
177#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
178
179/* field: TX2PEND - TX2PEND masked interrupt read */
180#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
181
182/* field: TX1PEND - TX1PEND masked interrupt read */
183#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
184
185/* field: TX0PEND - TX0PEND masked interrupt read */
186#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
187
188
189/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
190/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
191#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
192
193/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
194#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
195
196/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
197#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
198
199/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
200#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
201
202/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
203#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
204
205/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
206#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
207
208/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
209#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
210
211/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
212#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
213
214
215/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
216/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
217#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
218
219/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
220#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
221
222/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
223#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
224
225/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
226#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
227
228/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
229#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
230
231/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
232#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
233
234/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
235#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
236
237/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
238#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
239
240
241/*------------------TMS570_EMACM_MACINVECTOR------------------*/
242/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
243#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
244
245/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
246#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
247
248/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
249#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
250
251/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
252#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
253
254/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
255#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
256#define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23)
257#define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
258
259/* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */
260#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15)
261#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15)
262#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
263
264/* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */
265#define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7)
266#define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7)
267#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
268
269
270/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
271/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
272#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
273#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
274#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
275
276
277/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
278/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
279#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
280
281/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
282#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
283
284/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
285#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
286
287/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
288#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
289
290/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
291#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
292
293/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
294#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
295
296/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
297#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
298
299/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
300#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
301
302/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
303#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
304
305/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
306#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
307
308/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
309#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
310
311/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
312#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
313
314/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
315#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
316
317/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
318#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
319
320/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
321#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
322
323/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
324#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
325
326
327/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
328/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
329#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
330
331/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
332#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
333
334/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
335#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
336
337/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
338#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
339
340/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
341#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
342
343/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
344#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
345
346/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
347#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
348
349/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
350#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
351
352/* field: RX7PEND - RX7PEND masked interrupt read */
353#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
354
355/* field: RX6PEND - RX6PEND masked interrupt read */
356#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
357
358/* field: RX5PEND - RX5PEND masked interrupt read */
359#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
360
361/* field: RX4PEND - RX4PEND masked interrupt read */
362#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
363
364/* field: RX3PEND - RX3PEND masked interrupt read */
365#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
366
367/* field: RX2PEND - RX2PEND masked interrupt read */
368#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
369
370/* field: RX1PEND - RX1PEND masked interrupt read */
371#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
372
373/* field: RX0PEND - RX0PEND masked interrupt read */
374#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
375
376
377/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
378/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
379#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
380
381/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
382#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
383
384/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
385#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
386
387/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
388#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
389
390/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
391#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
392
393/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
394#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
395
396/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
397#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
398
399/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
400#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
401
402/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
403#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
404
405/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
406#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
407
408/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
409#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
410
411/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
412#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
413
414/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
415#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
416
417/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
418#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
419
420/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
421#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
422
423/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
424#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
425
426
427/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
428/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
429#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
430
431/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
432#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
433
434/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
435#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
436
437/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
438#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
439
440/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
441#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
442
443/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
444#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
445
446/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
447#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
448
449/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
450#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
451
452/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
453#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
454
455/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
456#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
457
458/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
459#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
460
461/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
462#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
463
464/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
465#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
466
467/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
468#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
469
470/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
471#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
472
473/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
474#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
475
476
477/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
478/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
479#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
480
481/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
482#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
483
484
485/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
486/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
487#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
488
489/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
490#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
491
492
493/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
494/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
495#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
496
497/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
498#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
499
500
501/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
502/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
503#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
504
505/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
506#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
507
508
509/*------------------TMS570_EMACM_RXMBPENABLE------------------*/
510/* field: RXPASSCRC - Pass receive CRC enable bit */
511#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
512
513/* field: RXQOSEN - Receive quality of service enable bit */
514#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
515
516/* field: RXNOCHAIN - Receive no buffer chaining bit */
517#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
518
519/* field: RXCMFEN - Receive copy MAC control frames enable bit. */
520#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
521
522/* field: RXCSFEN - Receive copy short frames enable bit. */
523#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
524
525/* field: RXCEFEN - Receive copy error frames enable bit. */
526#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
527
528/* field: RXCAFEN - Receive copy all frames enable bit. */
529#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
530
531/* field: RXPROMCH - Receive promiscuous channel select */
532#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
533#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18)
534#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
535
536/* field: RXBROADEN - Receive broadcast enable. */
537#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
538
539/* field: RXBROADCH - Receive broadcast channel select */
540#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
541#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10)
542#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
543
544/* field: RXMULTEN - RX multicast enable. */
545#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
546
547
548/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
549/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
550#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
551
552/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
553#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
554
555/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
556#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
557
558/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
559#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
560
561/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
562#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
563
564/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
565#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
566
567/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
568#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
569
570/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
571#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
572
573
574/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
575/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
576#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
577
578/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
579#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
580
581/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
582#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
583
584/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
585#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
586
587/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
588#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
589
590/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
591#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
592
593/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
594#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
595
596/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
597#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
598
599
600/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
601/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
602#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
603#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
604#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
605
606
607/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
608/* field: RXBUFFEROFFSET - Receive buffer offset value. */
609#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
610#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
611#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
612
613
614/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
615/* field: RXFILTERTHRESH - Receive filter low threshold. */
616#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
617#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
618#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
619
620
621/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
622/* field: RXnFLOWTHRESH - Receive flow threshold. */
623#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
624#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
625#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
626
627
628/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
629/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
630#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
631#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
632#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
633
634
635/*------------------TMS570_EMACM_MACCONTROL------------------*/
636/* field: RMIISPEED - RMII interface transmit and receive speed select. */
637#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
638
639/* field: RXOFFLENBLOCK - Receive offset / length word write block. */
640#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
641
642/* field: RXOWNERSHIP - Receive ownership write bit value. */
643#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
644
645/* field: CMDIDLE - Command Idle bit */
646#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
647
648/* field: TXSHORTGAPEN - Transmit Short Gap Enable */
649#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
650
651/* field: TXPTYPE - Transmit queue priority type */
652#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
653
654/* field: TXPACE - Transmit pacing enable bit */
655#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
656
657/* field: GMIIEN - GMII enable bit */
658#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
659
660/* field: TXFLOWEN - Transmit flow control enable bit. */
661#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
662
663/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
664#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
665
666/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
667#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
668
669/* field: FULLDUPLEX - Full duplex mode. */
670#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
671
672
673/*-------------------TMS570_EMACM_MACSTATUS-------------------*/
674/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
675#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
676
677/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
678#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
679#define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23)
680#define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
681
682/* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */
683#define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18)
684#define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18)
685#define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
686
687/* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */
688#define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15)
689#define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15)
690#define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
691
692/* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */
693#define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10)
694#define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10)
695#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
696
697/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
698#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
699
700/* field: RXFLOWACT - Receive flow control active bit. */
701#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
702
703/* field: TXFLOWACT - Transmit flow control active bit. */
704#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
705
706
707/*-------------------TMS570_EMACM_EMCONTROL-------------------*/
708/* field: SOFT - Emulation soft bit. */
709#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
710
711/* field: FREE - Emulation free bit. */
712#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
713
714
715/*------------------TMS570_EMACM_FIFOCONTROL------------------*/
716/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
717#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
718#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
719#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
720
721
722/*-------------------TMS570_EMACM_MACCONFIG-------------------*/
723/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
724#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
725#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
726#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
727
728/* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */
729#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23)
730#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23)
731#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
732
733/* field: ADDRESSTYPE - Address type */
734#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15)
735#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
736#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
737
738/* field: MACCFIG - MAC configuration value */
739#define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7)
740#define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7)
741#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
742
743
744/*-------------------TMS570_EMACM_SOFTRESET-------------------*/
745/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
746#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
747
748
749/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
750/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
751#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
752#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
753#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
754
755/* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */
756#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7)
757#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
758#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
759
760
761/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
762/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
763#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
764#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
765#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
766
767/* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */
768#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23)
769#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
770#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
771
772/* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */
773#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15)
774#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
775#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
776
777/* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */
778#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7)
779#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
780#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
781
782
783/*-------------------TMS570_EMACM_MACHASH1-------------------*/
784/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
785/* Whole 32 bits */
786
787/*-------------------TMS570_EMACM_MACHASH2-------------------*/
788/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
789/* Whole 32 bits */
790
791/*-------------------TMS570_EMACM_BOFFTEST-------------------*/
792/* field: RNDNUM - Backoff random number generator. */
793#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
794#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
795#define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
796
797/* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */
798#define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15)
799#define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15)
800#define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
801
802/* field: TXBACKOFF - Backoff count. */
803#define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9)
804#define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9)
805#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
806
807
808/*-------------------TMS570_EMACM_TPACETEST-------------------*/
809/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
810#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
811#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
812#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
813
814
815/*--------------------TMS570_EMACM_RXPAUSE--------------------*/
816/* field: PAUSETIMER - Receive pause timer value. */
817#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
818#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
819#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
820
821
822/*--------------------TMS570_EMACM_TXPAUSE--------------------*/
823/* field: PAUSETIMER - Transmit pause timer value. */
824#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
825#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
826#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
827
828
829/*-------------------TMS570_EMACM_MACADDRLO-------------------*/
830/* field: VALID - Address valid bit. */
831#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
832
833/* field: MATCHFILT - Match or filter bit */
834#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
835
836/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
837#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
838#define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18)
839#define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
840
841/* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */
842#define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15)
843#define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
844#define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
845
846/* field: MACADDR1 - MAC address bits 15-8 (byte 1) */
847#define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7)
848#define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
849#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
850
851
852/*-------------------TMS570_EMACM_MACADDRHI-------------------*/
853/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
854#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
855#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
856#define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
857
858/* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */
859#define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23)
860#define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
861#define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
862
863/* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */
864#define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15)
865#define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
866#define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
867
868/* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */
869#define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7)
870#define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
871#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
872
873
874/*-------------------TMS570_EMACM_MACINDEX-------------------*/
875/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
876#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
877#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
878#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
879
880
881/*---------------------TMS570_EMACM_TXHDP---------------------*/
882/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
883/* Whole 32 bits */
884
885/*---------------------TMS570_EMACM_RXHDP---------------------*/
886/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
887/* Whole 32 bits */
888
889/*---------------------TMS570_EMACM_TXCP---------------------*/
890/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
891/* Whole 32 bits */
892
893/*---------------------TMS570_EMACM_RXCP---------------------*/
894/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
895/* Whole 32 bits */
896
897
898#endif /* LIBBSP_ARM_TMS570_EMACM */
Note: See TracBrowser for help on using the repository browser.