1 | /* The header file is generated by make_header.py from EMACC.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_TMS570_EMACC |
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40 | #define LIBBSP_ARM_TMS570_EMACC |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t REVID; /*EMAC Control Module Revision ID Register*/ |
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46 | uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/ |
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47 | uint8_t reserved1 [4]; |
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48 | uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/ |
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49 | uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/ |
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50 | uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ |
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51 | uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ |
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52 | uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/ |
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53 | uint8_t reserved2 [32]; |
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54 | uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/ |
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55 | uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/ |
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56 | uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/ |
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57 | uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/ |
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58 | uint8_t reserved3 [32]; |
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59 | uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/ |
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60 | uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/ |
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61 | } tms570_emacc_t; |
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62 | |
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63 | |
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64 | /*---------------------TMS570_EMACC_REVID---------------------*/ |
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65 | /* field: REV - Identifies the EMAC Control Module revision. */ |
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66 | /* Whole 32 bits */ |
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67 | |
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68 | /*-------------------TMS570_EMACC_SOFTRESET-------------------*/ |
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69 | /* field: RESET - Software reset bit for the EMAC Control Module. */ |
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70 | #define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0) |
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71 | |
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72 | |
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73 | /*------------------TMS570_EMACC_INTCONTROL------------------*/ |
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74 | /* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */ |
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75 | #define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17) |
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76 | |
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77 | /* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */ |
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78 | #define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16) |
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79 | |
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80 | /* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */ |
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81 | #define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11) |
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82 | #define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11) |
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83 | #define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) |
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84 | |
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85 | |
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86 | /*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/ |
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87 | /* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */ |
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88 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7) |
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89 | |
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90 | /* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */ |
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91 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6) |
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92 | |
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93 | /* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */ |
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94 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5) |
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95 | |
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96 | /* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */ |
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97 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4) |
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98 | |
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99 | /* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */ |
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100 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3) |
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101 | |
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102 | /* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */ |
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103 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2) |
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104 | |
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105 | /* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */ |
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106 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1) |
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107 | |
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108 | /* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */ |
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109 | #define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0) |
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110 | |
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111 | |
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112 | /*--------------------TMS570_EMACC_C0RXEN--------------------*/ |
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113 | /* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */ |
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114 | #define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7) |
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115 | |
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116 | /* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */ |
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117 | #define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6) |
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118 | |
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119 | /* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */ |
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120 | #define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5) |
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121 | |
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122 | /* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */ |
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123 | #define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4) |
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124 | |
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125 | /* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */ |
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126 | #define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3) |
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127 | |
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128 | /* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */ |
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129 | #define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2) |
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130 | |
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131 | /* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */ |
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132 | #define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1) |
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133 | |
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134 | /* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */ |
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135 | #define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0) |
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136 | |
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137 | |
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138 | /*--------------------TMS570_EMACC_C0TXEN--------------------*/ |
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139 | /* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */ |
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140 | #define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7) |
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141 | |
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142 | /* field: TXCH6EN - TXCH6EN */ |
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143 | #define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6) |
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144 | |
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145 | /* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */ |
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146 | #define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5) |
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147 | |
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148 | /* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */ |
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149 | #define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4) |
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150 | |
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151 | /* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */ |
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152 | #define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3) |
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153 | |
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154 | /* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */ |
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155 | #define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2) |
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156 | |
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157 | /* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */ |
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158 | #define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1) |
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159 | |
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160 | /* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */ |
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161 | #define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0) |
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162 | |
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163 | |
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164 | /*-------------------TMS570_EMACC_C0MISCEN-------------------*/ |
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165 | /* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */ |
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166 | #define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3) |
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167 | |
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168 | /* field: HOSTPENDEN - HOSTPENDEN */ |
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169 | #define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2) |
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170 | |
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171 | /* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */ |
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172 | #define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1) |
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173 | |
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174 | /* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */ |
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175 | #define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0) |
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176 | |
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177 | |
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178 | /*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/ |
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179 | /* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */ |
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180 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7) |
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181 | |
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182 | /* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */ |
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183 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6) |
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184 | |
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185 | /* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */ |
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186 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5) |
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187 | |
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188 | /* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */ |
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189 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4) |
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190 | |
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191 | /* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */ |
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192 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3) |
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193 | |
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194 | /* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */ |
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195 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2) |
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196 | |
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197 | /* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */ |
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198 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1) |
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199 | |
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200 | /* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */ |
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201 | #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0) |
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202 | |
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203 | |
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204 | /*-------------------TMS570_EMACC_C0RXSTAT-------------------*/ |
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205 | /* field: RXCH7STAT - RXCH7STAT */ |
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206 | #define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7) |
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207 | |
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208 | /* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */ |
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209 | #define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6) |
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210 | |
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211 | /* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */ |
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212 | #define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5) |
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213 | |
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214 | /* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */ |
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215 | #define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4) |
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216 | |
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217 | /* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */ |
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218 | #define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3) |
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219 | |
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220 | /* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */ |
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221 | #define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2) |
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222 | |
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223 | /* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */ |
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224 | #define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1) |
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225 | |
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226 | /* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */ |
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227 | #define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0) |
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228 | |
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229 | |
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230 | /*-------------------TMS570_EMACC_C0TXSTAT-------------------*/ |
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231 | /* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */ |
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232 | #define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7) |
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233 | |
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234 | /* field: TXCH6STAT - TXCH6STAT */ |
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235 | #define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6) |
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236 | |
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237 | /* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */ |
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238 | #define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5) |
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239 | |
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240 | /* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */ |
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241 | #define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4) |
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242 | |
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243 | /* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */ |
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244 | #define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3) |
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245 | |
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246 | /* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */ |
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247 | #define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2) |
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248 | |
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249 | /* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */ |
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250 | #define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1) |
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251 | |
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252 | /* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */ |
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253 | #define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0) |
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254 | |
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255 | |
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256 | /*------------------TMS570_EMACC_C0MISCSTAT------------------*/ |
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257 | /* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */ |
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258 | #define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3) |
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259 | |
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260 | /* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */ |
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261 | #define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2) |
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262 | |
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263 | /* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */ |
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264 | #define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1) |
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265 | |
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266 | /* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */ |
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267 | #define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0) |
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268 | |
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269 | |
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270 | /*-------------------TMS570_EMACC_C0RXIMAX-------------------*/ |
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271 | /* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */ |
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272 | #define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5) |
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273 | #define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) |
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274 | #define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) |
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275 | |
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276 | |
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277 | /*-------------------TMS570_EMACC_C0TXIMAX-------------------*/ |
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278 | /* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */ |
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279 | #define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5) |
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280 | #define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) |
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281 | #define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) |
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282 | |
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283 | |
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284 | |
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285 | #endif /* LIBBSP_ARM_TMS570_EMACC */ |
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