| 1 | /* The header file is generated by make_header.py from DMM.json */ |
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| 2 | /* Current script's version can be found at: */ |
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| 3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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| 4 | |
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| 5 | /* |
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| 6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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| 7 | * |
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| 8 | * Czech Technical University in Prague |
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| 9 | * Zikova 1903/4 |
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| 10 | * 166 36 Praha 6 |
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| 11 | * Czech Republic |
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| 12 | * |
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| 13 | * All rights reserved. |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions are met: |
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| 17 | * |
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| 18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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| 19 | * list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 21 | * this list of conditions and the following disclaimer in the documentation |
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| 22 | * and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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| 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | * The views and conclusions contained in the software and documentation are those |
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| 36 | * of the authors and should not be interpreted as representing official policies, |
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| 37 | * either expressed or implied, of the FreeBSD Project. |
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| 38 | */ |
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| 39 | #ifndef LIBBSP_ARM_TMS570_DMM |
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| 40 | #define LIBBSP_ARM_TMS570_DMM |
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| 41 | |
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| 42 | #include <bsp/utility.h> |
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| 43 | |
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| 44 | typedef struct{ |
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| 45 | uint32_t GLBCTRL; /*DMM Global Control Register*/ |
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| 46 | uint32_t INTSET; /*DMM Interrupt Set Register*/ |
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| 47 | uint32_t INTCLR; /*DMM Interrupt Clear Register*/ |
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| 48 | uint32_t INTLVL; /*DMM Interrupt Level Register*/ |
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| 49 | uint32_t INTFLG; /*DMM Interrupt Flag Register*/ |
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| 50 | uint32_t OFF1; /*DMM Interrupt Offset 1 Register*/ |
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| 51 | uint32_t OFF2; /*DMM Interrupt Offset 2 Register*/ |
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| 52 | uint32_t DDMDEST; /*DMM Direct Data Mode Destination Register*/ |
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| 53 | uint32_t DDMBL; /*DMM Direct Data Mode Blocksize Register*/ |
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| 54 | uint32_t DDMPT; /*DMM Direct Data Mode Pointer Register*/ |
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| 55 | uint32_t INTPT; /*DMM Direct Data Mode Interrupt Pointer Register*/ |
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| 56 | uint32_t DEST0REG1; /*DMM Destination 0 Region 1*/ |
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| 57 | uint32_t DEST0BL1; /*DMM Destination 0 Blocksize 1*/ |
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| 58 | uint32_t DEST0REG2; /*DMM Destination 0 Region 2*/ |
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| 59 | uint32_t DEST0BL2; /*DMM Destination 0 Blocksize 2*/ |
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| 60 | uint32_t DEST1REG1; /*DMM Destination 1 Region 1*/ |
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| 61 | uint32_t DEST1BL1; /*DMM Destination 1 Blocksize 1*/ |
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| 62 | uint32_t DEST1REG2; /*DMM Destination 1 Region 2*/ |
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| 63 | uint32_t DEST1BL2; /*DMM Destination 1 Blocksize 2*/ |
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| 64 | uint32_t DEST2REG1; /*DMM Destination 2 Region 1*/ |
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| 65 | uint32_t DEST2BL1; /*DMM Destination 2 Blocksize 1*/ |
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| 66 | uint32_t DEST2REG2; /*DMM Destination 2 Region 2*/ |
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| 67 | uint32_t DEST2BL2; /*DMM Destination 2 Blocksize 2*/ |
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| 68 | uint32_t DEST3REG1; /*DMM Destination 3 Region 1*/ |
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| 69 | uint32_t DEST3BL1; /*DMM Destination 3 Blocksize 1*/ |
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| 70 | uint32_t DEST3REG2; /*DMM Destination 3 Region 2*/ |
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| 71 | uint32_t DEST3BL2; /*DMM Destination 3 Blocksize 2*/ |
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| 72 | uint32_t PC0; /*DMM Pin Control 0*/ |
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| 73 | uint32_t PC1; /*DMM Pin Control 1*/ |
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| 74 | uint32_t PC2; /*DMM Pin Control 2*/ |
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| 75 | uint32_t PC3; /*DMM Pin Control 3*/ |
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| 76 | uint32_t PC4; /*DMM Pin Control 4*/ |
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| 77 | uint32_t PC5; /*DMM Pin Control 5*/ |
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| 78 | uint32_t PC6; /*DMM Pin Control 6*/ |
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| 79 | uint32_t PC7; /*DMM Pin Control 7*/ |
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| 80 | uint32_t PC8; /*DMM Pin Control 8*/ |
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| 81 | } tms570_dmm_t; |
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| 82 | |
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| 83 | |
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| 84 | /*---------------------TMS570_DMM_GLBCTRL---------------------*/ |
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| 85 | /* field: BUSY - Busy indicator. */ |
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| 86 | #define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24) |
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| 87 | |
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| 88 | /* field: CONTCLK - Continuous DMMCLK input. */ |
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| 89 | #define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18) |
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| 90 | |
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| 91 | /* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */ |
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| 92 | #define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17) |
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| 93 | |
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| 94 | /* field: RESET - Reset. */ |
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| 95 | #define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16) |
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| 96 | |
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| 97 | /* field: DDM_WIDTH - Packet Width in direct data mode. */ |
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| 98 | #define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10) |
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| 99 | #define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10) |
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| 100 | #define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) |
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| 101 | |
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| 102 | /* field: TM_DMM - Packet Format. */ |
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| 103 | #define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8) |
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| 104 | |
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| 105 | /* field: ON_OFF - Switch module on or off */ |
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| 106 | #define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) |
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| 107 | #define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 108 | #define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 109 | |
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| 110 | |
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| 111 | /*---------------------TMS570_DMM_INTSET---------------------*/ |
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| 112 | /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ |
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| 113 | #define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17) |
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| 114 | |
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| 115 | /* field: EO_BUFF - EO_BUFF */ |
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| 116 | #define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16) |
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| 117 | |
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| 118 | /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */ |
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| 119 | #define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15) |
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| 120 | |
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| 121 | /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ |
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| 122 | #define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14) |
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| 123 | |
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| 124 | /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ |
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| 125 | #define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13) |
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| 126 | |
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| 127 | /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ |
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| 128 | #define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12) |
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| 129 | |
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| 130 | /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ |
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| 131 | #define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11) |
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| 132 | |
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| 133 | /* field: DEST1REG1 - DEST1REG1 */ |
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| 134 | #define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10) |
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| 135 | |
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| 136 | /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ |
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| 137 | #define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9) |
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| 138 | |
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| 139 | /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ |
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| 140 | #define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8) |
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| 141 | |
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| 142 | /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ |
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| 143 | #define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7) |
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| 144 | |
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| 145 | /* field: BUFF_OVF - Buffer Overflow. */ |
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| 146 | #define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6) |
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| 147 | |
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| 148 | /* field: SRC_OVF - Source Overflow. */ |
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| 149 | #define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5) |
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| 150 | |
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| 151 | /* field: DEST3_ERR - Destination 3 Error. */ |
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| 152 | #define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4) |
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| 153 | |
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| 154 | /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ |
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| 155 | #define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3) |
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| 156 | |
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| 157 | /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ |
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| 158 | #define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2) |
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| 159 | |
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| 160 | /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ |
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| 161 | #define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1) |
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| 162 | |
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| 163 | /* field: PACKET_ERR_INT - Packet Error. */ |
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| 164 | #define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0) |
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| 165 | |
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| 166 | |
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| 167 | /*---------------------TMS570_DMM_INTCLR---------------------*/ |
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| 168 | /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ |
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| 169 | #define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17) |
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| 170 | |
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| 171 | /* field: EO_BUFF - End of Buffer Interrupt Set. */ |
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| 172 | #define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16) |
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| 173 | |
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| 174 | /* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */ |
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| 175 | #define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15) |
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| 176 | |
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| 177 | /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ |
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| 178 | #define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14) |
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| 179 | |
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| 180 | /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ |
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| 181 | #define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13) |
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| 182 | |
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| 183 | /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ |
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| 184 | #define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12) |
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| 185 | |
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| 186 | /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ |
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| 187 | #define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11) |
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| 188 | |
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| 189 | /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */ |
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| 190 | #define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10) |
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| 191 | |
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| 192 | /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ |
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| 193 | #define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9) |
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| 194 | |
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| 195 | /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ |
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| 196 | #define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8) |
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| 197 | |
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| 198 | /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ |
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| 199 | #define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7) |
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| 200 | |
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| 201 | /* field: BUFF_OVF - Buffer Overflow. */ |
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| 202 | #define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6) |
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| 203 | |
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| 204 | /* field: SRC_OVF - Source Overflow. */ |
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| 205 | #define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5) |
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| 206 | |
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| 207 | /* field: DEST3_ERR - Destination 3 Error. */ |
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| 208 | #define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4) |
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| 209 | |
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| 210 | /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ |
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| 211 | #define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3) |
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| 212 | |
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| 213 | /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ |
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| 214 | #define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2) |
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| 215 | |
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| 216 | /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ |
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| 217 | #define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1) |
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| 218 | |
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| 219 | /* field: PACKET_ERR_INT - Packet Error. */ |
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| 220 | #define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0) |
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| 221 | |
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| 222 | |
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| 223 | /*---------------------TMS570_DMM_INTLVL---------------------*/ |
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| 224 | /* field: PROG_BUFF - Programmable Buffer Interrupt Level */ |
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| 225 | #define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17) |
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| 226 | |
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| 227 | /* field: EO_BUFF - End of Buffer Interrupt Level */ |
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| 228 | #define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16) |
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| 229 | |
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| 230 | /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */ |
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| 231 | #define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15) |
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| 232 | |
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| 233 | /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */ |
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| 234 | #define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14) |
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| 235 | |
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| 236 | /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */ |
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| 237 | #define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13) |
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| 238 | |
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| 239 | /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */ |
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| 240 | #define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12) |
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| 241 | |
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| 242 | /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */ |
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| 243 | #define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11) |
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| 244 | |
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| 245 | /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */ |
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| 246 | #define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10) |
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| 247 | |
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| 248 | /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */ |
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| 249 | #define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9) |
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| 250 | |
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| 251 | /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */ |
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| 252 | #define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8) |
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| 253 | |
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| 254 | /* field: BUSERROR - BMM Bus Error Response */ |
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| 255 | #define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7) |
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| 256 | |
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| 257 | /* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */ |
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| 258 | #define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6) |
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| 259 | |
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| 260 | /* field: SRC_OVF - Source Overflow Interrupt Level */ |
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| 261 | #define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5) |
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| 262 | |
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| 263 | /* field: DEST3_ERR - Destination 3 Error Interrupt Level */ |
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| 264 | #define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4) |
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| 265 | |
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| 266 | /* field: DEST2_ERR - Destination 2 Error Interrupt Level */ |
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| 267 | #define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3) |
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| 268 | |
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| 269 | /* field: DEST1_ERR - Destination 1 Error Interrupt Level */ |
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| 270 | #define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2) |
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| 271 | |
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| 272 | /* field: DEST0_ERR - Destination 0 Error Interrupt Level */ |
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| 273 | #define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1) |
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| 274 | |
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| 275 | /* field: PACKET_ERR_INT - Packet Error Interrupt Level */ |
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| 276 | #define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0) |
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| 277 | |
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| 278 | |
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| 279 | /*---------------------TMS570_DMM_INTFLG---------------------*/ |
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| 280 | /* field: PROG_BUFF - Programmable Buffer Interrupt Flag */ |
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| 281 | #define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17) |
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| 282 | |
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| 283 | /* field: EO_BUFF - End of Buffer Interrupt Flag */ |
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| 284 | #define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16) |
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| 285 | |
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| 286 | /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */ |
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| 287 | #define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15) |
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| 288 | |
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| 289 | /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */ |
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| 290 | #define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14) |
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| 291 | |
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| 292 | /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */ |
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| 293 | #define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13) |
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| 294 | |
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| 295 | /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */ |
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| 296 | #define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12) |
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| 297 | |
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| 298 | /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */ |
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| 299 | #define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11) |
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| 300 | |
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| 301 | /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */ |
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| 302 | #define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10) |
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| 303 | |
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| 304 | /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */ |
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| 305 | #define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9) |
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| 306 | |
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| 307 | /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */ |
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| 308 | #define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8) |
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| 309 | |
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| 310 | /* field: BUSERROR - BMM Bus Error Response. */ |
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| 311 | #define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7) |
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| 312 | |
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| 313 | /* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */ |
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| 314 | #define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6) |
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| 315 | |
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| 316 | /* field: SRC_OVF - Source Overflow Interrupt Flag */ |
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| 317 | #define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5) |
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| 318 | |
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| 319 | /* field: DEST3_ERR - Destination 3 Error Interrupt Flag */ |
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| 320 | #define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4) |
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| 321 | |
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| 322 | /* field: DEST2_ERR - Destination 2 Error Interrupt Flag */ |
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| 323 | #define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3) |
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| 324 | |
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| 325 | /* field: DEST1_ERR - Destination 1 Error Interrupt Flag */ |
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| 326 | #define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2) |
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| 327 | |
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| 328 | /* field: DEST0_ERR - Destination 0 Error Interrupt Flag */ |
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| 329 | #define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1) |
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| 330 | |
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| 331 | /* field: PACKET_ERR_INT - Packet Error Interrupt Flag */ |
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| 332 | #define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0) |
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| 333 | |
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| 334 | |
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| 335 | /*----------------------TMS570_DMM_OFF1----------------------*/ |
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| 336 | /* field: OFFSET - User and privilege mode (read): */ |
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| 337 | #define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4) |
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| 338 | #define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) |
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| 339 | #define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) |
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| 340 | |
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| 341 | |
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| 342 | /*----------------------TMS570_DMM_OFF2----------------------*/ |
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| 343 | /* field: OFFSET - User and privilege mode (read): */ |
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| 344 | #define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4) |
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| 345 | #define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) |
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| 346 | #define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) |
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| 347 | |
|---|
| 348 | |
|---|
| 349 | /*---------------------TMS570_DMM_DDMDEST---------------------*/ |
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| 350 | /* field: STARTADDR - These bits define the starting address of the buffer. */ |
|---|
| 351 | /* Whole 32 bits */ |
|---|
| 352 | |
|---|
| 353 | /*----------------------TMS570_DMM_DDMBL----------------------*/ |
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| 354 | /* field: BLOCKSIZE - These bits define the size of the buffer region */ |
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| 355 | #define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3) |
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| 356 | #define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 357 | #define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 358 | |
|---|
| 359 | |
|---|
| 360 | /*----------------------TMS570_DMM_DDMPT----------------------*/ |
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| 361 | /* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */ |
|---|
| 362 | #define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14) |
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| 363 | #define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14) |
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| 364 | #define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) |
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| 365 | |
|---|
| 366 | |
|---|
| 367 | /*----------------------TMS570_DMM_INTPT----------------------*/ |
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| 368 | /* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */ |
|---|
| 369 | #define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14) |
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| 370 | #define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14) |
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| 371 | #define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) |
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| 372 | |
|---|
| 373 | |
|---|
| 374 | /*--------------------TMS570_DMM_DESTxREG1--------------------*/ |
|---|
| 375 | /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ |
|---|
| 376 | #define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31) |
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| 377 | #define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) |
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| 378 | #define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) |
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| 379 | |
|---|
| 380 | /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ |
|---|
| 381 | #define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17) |
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| 382 | #define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) |
|---|
| 383 | #define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) |
|---|
| 384 | |
|---|
| 385 | |
|---|
| 386 | /*--------------------TMS570_DMM_DESTxBL1--------------------*/ |
|---|
| 387 | /* field: BLOCKSIZE - These bits define the length of the buffer region. */ |
|---|
| 388 | #define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3) |
|---|
| 389 | #define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) |
|---|
| 390 | #define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
|---|
| 391 | |
|---|
| 392 | |
|---|
| 393 | /*--------------------TMS570_DMM_DESTxREG2--------------------*/ |
|---|
| 394 | /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ |
|---|
| 395 | #define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31) |
|---|
| 396 | #define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) |
|---|
| 397 | #define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) |
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| 398 | |
|---|
| 399 | /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ |
|---|
| 400 | #define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17) |
|---|
| 401 | #define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) |
|---|
| 402 | #define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) |
|---|
| 403 | |
|---|
| 404 | |
|---|
| 405 | /*--------------------TMS570_DMM_DESTxBL2--------------------*/ |
|---|
| 406 | /* field: BLOCKSIZE - These bits define the length of the buffer region. */ |
|---|
| 407 | #define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3) |
|---|
| 408 | #define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) |
|---|
| 409 | #define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
|---|
| 410 | |
|---|
| 411 | |
|---|
| 412 | /*-----------------------TMS570_DMM_PC0-----------------------*/ |
|---|
| 413 | /* field: ENAFUNC - Functional mode of DMMENA pin. */ |
|---|
| 414 | #define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18) |
|---|
| 415 | |
|---|
| 416 | /* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */ |
|---|
| 417 | #define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17) |
|---|
| 418 | #define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 419 | #define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 420 | |
|---|
| 421 | /* field: CLKFUNC - Functional mode of DMMCLK pin. */ |
|---|
| 422 | #define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1) |
|---|
| 423 | |
|---|
| 424 | /* field: SYNCFUNC - Functional mode of DMMSYNC pin. */ |
|---|
| 425 | #define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0) |
|---|
| 426 | |
|---|
| 427 | |
|---|
| 428 | /*-----------------------TMS570_DMM_PC1-----------------------*/ |
|---|
| 429 | /* field: ENADIR - Direction of DMMENA pin. */ |
|---|
| 430 | #define TMS570_DMM_PC1_ENADIR BSP_BIT32(18) |
|---|
| 431 | |
|---|
| 432 | /* field: DATAxDIR - Direction of DMMDATA[x] pin. */ |
|---|
| 433 | #define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17) |
|---|
| 434 | #define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 435 | #define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 436 | |
|---|
| 437 | /* field: CLKDIR - Direction of DMMCLK pin. */ |
|---|
| 438 | #define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1) |
|---|
| 439 | |
|---|
| 440 | /* field: SYNCDIR - Direction of DMMSYNC pin. */ |
|---|
| 441 | #define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0) |
|---|
| 442 | |
|---|
| 443 | |
|---|
| 444 | /*-----------------------TMS570_DMM_PC2-----------------------*/ |
|---|
| 445 | /* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */ |
|---|
| 446 | #define TMS570_DMM_PC2_ENAIN BSP_BIT32(18) |
|---|
| 447 | |
|---|
| 448 | /* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */ |
|---|
| 449 | #define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17) |
|---|
| 450 | #define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 451 | #define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 452 | |
|---|
| 453 | /* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */ |
|---|
| 454 | #define TMS570_DMM_PC2_CLKIN BSP_BIT32(1) |
|---|
| 455 | |
|---|
| 456 | /* field: SYNCIN - DMMSYNC input. */ |
|---|
| 457 | #define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0) |
|---|
| 458 | |
|---|
| 459 | |
|---|
| 460 | /*-----------------------TMS570_DMM_PC3-----------------------*/ |
|---|
| 461 | /* field: ENAOUT - Output state of DMMENA pin. */ |
|---|
| 462 | #define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18) |
|---|
| 463 | |
|---|
| 464 | /* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */ |
|---|
| 465 | #define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17) |
|---|
| 466 | #define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 467 | #define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 468 | |
|---|
| 469 | /* field: CLKOUT - Output state of DMMCLK pin. */ |
|---|
| 470 | #define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1) |
|---|
| 471 | |
|---|
| 472 | /* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */ |
|---|
| 473 | #define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0) |
|---|
| 474 | |
|---|
| 475 | |
|---|
| 476 | /*-----------------------TMS570_DMM_PC4-----------------------*/ |
|---|
| 477 | /* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */ |
|---|
| 478 | #define TMS570_DMM_PC4_ENASET BSP_BIT32(18) |
|---|
| 479 | |
|---|
| 480 | /* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */ |
|---|
| 481 | #define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17) |
|---|
| 482 | #define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 483 | #define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 484 | |
|---|
| 485 | /* field: CLKSET - Sets output state of DMMCLK pin to logic high. */ |
|---|
| 486 | #define TMS570_DMM_PC4_CLKSET BSP_BIT32(1) |
|---|
| 487 | |
|---|
| 488 | /* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */ |
|---|
| 489 | #define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0) |
|---|
| 490 | |
|---|
| 491 | |
|---|
| 492 | /*-----------------------TMS570_DMM_PC5-----------------------*/ |
|---|
| 493 | /* field: ENACLR - Sets output state of DMMENA pin to logic low. */ |
|---|
| 494 | #define TMS570_DMM_PC5_ENACLR BSP_BIT32(18) |
|---|
| 495 | |
|---|
| 496 | /* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */ |
|---|
| 497 | #define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17) |
|---|
| 498 | #define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 499 | #define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 500 | |
|---|
| 501 | /* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */ |
|---|
| 502 | #define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1) |
|---|
| 503 | |
|---|
| 504 | /* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */ |
|---|
| 505 | #define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0) |
|---|
| 506 | |
|---|
| 507 | |
|---|
| 508 | /*-----------------------TMS570_DMM_PC6-----------------------*/ |
|---|
| 509 | /* field: ENAPDR - Open Drain enable. */ |
|---|
| 510 | #define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18) |
|---|
| 511 | |
|---|
| 512 | /* field: DATAxPDR - Open Drain enable. */ |
|---|
| 513 | #define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17) |
|---|
| 514 | #define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 515 | #define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 516 | |
|---|
| 517 | /* field: CLKPDR - Open Drain enable. */ |
|---|
| 518 | #define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1) |
|---|
| 519 | |
|---|
| 520 | /* field: SYNCPDR - Open Drain enable. */ |
|---|
| 521 | #define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0) |
|---|
| 522 | |
|---|
| 523 | |
|---|
| 524 | /*-----------------------TMS570_DMM_PC7-----------------------*/ |
|---|
| 525 | /* field: ENAPDIS - Pull disable. */ |
|---|
| 526 | #define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18) |
|---|
| 527 | |
|---|
| 528 | /* field: DATAxPDIS - Pull disable. */ |
|---|
| 529 | #define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17) |
|---|
| 530 | #define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 531 | #define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 532 | |
|---|
| 533 | /* field: CLKPDIS - Pull disable. */ |
|---|
| 534 | #define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1) |
|---|
| 535 | |
|---|
| 536 | /* field: SYNCPDIS - Pull disable. */ |
|---|
| 537 | #define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0) |
|---|
| 538 | |
|---|
| 539 | |
|---|
| 540 | /*-----------------------TMS570_DMM_PC8-----------------------*/ |
|---|
| 541 | /* field: ENAPSEL - Pull disable. */ |
|---|
| 542 | #define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18) |
|---|
| 543 | |
|---|
| 544 | /* field: DATAxPSEL - Pull disable. */ |
|---|
| 545 | #define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17) |
|---|
| 546 | #define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17) |
|---|
| 547 | #define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) |
|---|
| 548 | |
|---|
| 549 | /* field: CLKPSEL - Pull disable. */ |
|---|
| 550 | #define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1) |
|---|
| 551 | |
|---|
| 552 | /* field: SYNCPSEL - Pull disable. */ |
|---|
| 553 | #define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0) |
|---|
| 554 | |
|---|
| 555 | |
|---|
| 556 | |
|---|
| 557 | #endif /* LIBBSP_ARM_TMS570_DMM */ |
|---|
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