source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h @ 602e395

4.115
Last change on this file since 602e395 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on 07/16/15 at 14:26:09

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

​https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>
  • Property mode set to 100644
File size: 34.1 KB
Line 
1/* The header file is generated by make_header.py from DMA.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_DMA
40#define LIBBSP_ARM_tms570_DMA
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t STARTADD;          /*DMA Memory Protection Region start Address Register*/
46  uint32_t ENDADD;            /*DMA Memory Protection Region End Address Register*/
47} tms570_memory_prot_t;
48
49typedef struct{
50  uint32_t GCTRL;             /*Global Control Register*/
51  uint32_t PEND;              /*Channel Pending Register*/
52  uint8_t reserved1 [4];
53  uint32_t DMASTAT;           /*DMA Status Register*/
54  uint8_t reserved2 [4];
55  uint32_t HWCHENAS;          /*HW Channel Enable Set and Status Register*/
56  uint8_t reserved3 [4];
57  uint32_t HWCHENAR;          /*HW Channel Enable Reset and Status Register*/
58  uint8_t reserved4 [4];
59  uint32_t SWCHENAS;          /*SW Channel Enable Set and Status Register*/
60  uint8_t reserved5 [4];
61  uint32_t SWCHENAR;          /*SW Channel Enable Reset and Status Register*/
62  uint8_t reserved6 [4];
63  uint32_t CHPRIOS;           /*Channel Priority Set Register*/
64  uint8_t reserved7 [4];
65  uint32_t CHPRIOR;           /*Channel Priority Reset Register*/
66  uint8_t reserved8 [4];
67  uint32_t GCHIENAS;          /*Global Channel Interrupt Enable Set Register*/
68  uint8_t reserved9 [4];
69  uint32_t GCHIENAR;          /*Global Channel Interrupt Enable Reset Register*/
70  uint8_t reserved10 [4];
71  uint32_t DREQASI[4];        /*DMA Request Assignment Register 0*/
72  uint8_t reserved11 [48];
73  uint32_t PAR0;              /*Port Assignment Register 0*/
74  uint32_t PAR1;              /*Port Assignment Register 1*/
75  uint8_t reserved12 [24];
76  uint32_t FTCMAP;            /*FTC Interrupt Mapping Register*/
77  uint8_t reserved13 [4];
78  uint32_t LFSMAP;            /*LFS Interrupt Mapping Register*/
79  uint8_t reserved14 [4];
80  uint32_t HBCMAP;            /*HBC Interrupt Mapping Register*/
81  uint8_t reserved15 [4];
82  uint32_t BTCMAP;            /*BTC Interrupt Mapping Register*/
83  uint8_t reserved16 [4];
84  uint32_t BERMAP;            /*BER Interrupt Mapping Register*/
85  uint8_t reserved17 [4];
86  uint32_t FTCINTENAS;        /*FTC Interrupt Enable Set*/
87  uint8_t reserved18 [4];
88  uint32_t FTCINTENAR;        /*FTC Interrupt Enable Reset*/
89  uint8_t reserved19 [4];
90  uint32_t LFSINTENAS;        /*LFS Interrupt Enable Set*/
91  uint8_t reserved20 [4];
92  uint32_t LFSINTENAR;        /*LFS Interrupt Enable Reset*/
93  uint8_t reserved21 [4];
94  uint32_t HBCINTENAS;        /*HBC Interrupt Enable Set*/
95  uint8_t reserved22 [4];
96  uint32_t HBCINTENAR;        /*HBC Interrupt Enable Reset*/
97  uint8_t reserved23 [4];
98  uint32_t BTCINTENAS;        /*BTC Interrupt Enable Set*/
99  uint8_t reserved24 [4];
100  uint32_t BTCINTENAR;        /*BTC Interrupt Enable Reset*/
101  uint8_t reserved25 [4];
102  uint32_t GINTFLAG;          /*Global Interrupt Flag Register*/
103  uint8_t reserved26 [4];
104  uint32_t FTCFLAG;           /*FTC Interrupt Flag Register*/
105  uint8_t reserved27 [4];
106  uint32_t LFSFLAG;           /*LFS Interrupt Flag Register*/
107  uint8_t reserved28 [4];
108  uint32_t HBCFLAG;           /*HBC Interrupt Flag Register*/
109  uint8_t reserved29 [4];
110  uint32_t BTCFLAG;           /*BTC Interrupt Flag Register*/
111  uint8_t reserved30 [4];
112  uint32_t BERFLAG;           /*BER Interrupt Flag Register*/
113  uint8_t reserved31 [4];
114  uint32_t FTCAOFFSET;        /*FTCA Interrupt Channel Offset Register*/
115  uint32_t LFSAOFFSET;        /*LFSA Interrupt Channel Offset Register*/
116  uint32_t HBCAOFFSET;        /*HBCA Interrupt Channel Offset Register*/
117  uint32_t BTCAOFFSET;        /*BTCA Interrupt Channel Offset Register*/
118  uint32_t BERAOFFSET;        /*BERA Interrupt Channel Offset Register*/
119  uint32_t FTCBOFFSET;        /*FTCB Interrupt Channel Offset Register*/
120  uint32_t LFSBOFFSET;        /*LFSB Interrupt Channel Offset Register*/
121  uint32_t HBCBOFFSET;        /*HBCB Interrupt Channel Offset Register*/
122  uint32_t BTCBOFFSET;        /*BTCB Interrupt Channel Offset Register*/
123  uint32_t BERBOFFSET;        /*BERB Interrupt Channel Offset Register*/
124  uint8_t reserved32 [4];
125  uint32_t PTCRL;             /*Port Control Register*/
126  uint32_t RTCTRL;            /*RAM Test Control Register*/
127  uint32_t DCTRL;             /*Debug Control*/
128  uint32_t WPR;               /*Watch Point Register*/
129  uint32_t WMR;               /*Watch Mask Register*/
130  uint8_t reserved33 [12];
131  uint32_t PBACSADDR;         /*Port B Active Channel Source Address Register*/
132  uint32_t PBACDADDR;         /*Port B Active Channel Destination Address Register*/
133  uint32_t PBACTC;            /*Port B Active Channel Transfer Count Register*/
134  uint8_t reserved34 [4];
135  uint32_t DMAPCR;            /*Parity Control Register*/
136  uint32_t DMAPAR;            /*DMA Parity Error Address Register*/
137  uint32_t DMAMPCTRL;         /*DMA Memory Protection Control Register*/
138  uint32_t DMAMPST;           /*DMA Memory Protection Status Register*/
139  tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/
140} tms570_dma_t;
141
142
143/*---------------------TMS570_DMASTARTADD---------------------*/
144/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
145#define TMS570_DMA_STARTADD_STARTADDRESS(val) BSP_FLD32(val,0, 31)
146#define TMS570_DMA_STARTADD_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
147#define TMS570_DMA_STARTADD_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
148
149
150/*----------------------TMS570_DMAENDADD----------------------*/
151/* field: ENDADDRESS - End Address defines the address at which the region ends. */
152#define TMS570_DMA_ENDADD_ENDADDRESS(val) BSP_FLD32(val,0, 31)
153#define TMS570_DMA_ENDADD_ENDADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
154#define TMS570_DMA_ENDADD_ENDADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
155
156
157/*----------------------TMS570_DMAGCTRL----------------------*/
158/* field: DMA_EN - DMA enable bit. */
159#define TMS570_DMA_GCTRL_DMA_EN BSP_FLD32(16)
160
161/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
162#define TMS570_DMA_GCTRL_BUS_BUSY BSP_FLD32(14)
163
164/* field: DEBUG_MODE - Debug Mode. */
165#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
166#define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
167#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
168
169/* field: DMA_RES - DMA software reset */
170#define TMS570_DMA_GCTRL_DMA_RES BSP_FLD32(0)
171
172
173/*-----------------------TMS570_DMAPEND-----------------------*/
174/* field: PEND - Channel pending register. */
175#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
176#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
177#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
178
179
180/*---------------------TMS570_DMADMASTAT---------------------*/
181/* field: STCH - Status of DMA channels. */
182#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
183#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
184#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
185
186
187/*---------------------TMS570_DMAHWCHENAS---------------------*/
188/* field: HWCHENA - Hardware channel enable bit. */
189#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
190#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
191#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
192
193
194/*---------------------TMS570_DMAHWCHENAR---------------------*/
195/* field: HWCHDIS - HW channel disable bit. */
196#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
197#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
198#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
199
200
201/*---------------------TMS570_DMASWCHENAS---------------------*/
202/* field: SWCHENA - SW channel enable bit. */
203#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
204#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
205#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
206
207
208/*---------------------TMS570_DMASWCHENAR---------------------*/
209/* field: SWCHDIS - SW channel disable bit. */
210#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
211#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
212#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
213
214
215/*---------------------TMS570_DMACHPRIOS---------------------*/
216/* field: CPS - Channel priority set bit. */
217#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
218#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
219#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
220
221
222/*---------------------TMS570_DMACHPRIOR---------------------*/
223/* field: CPR - Channel priority reset bit. */
224#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
225#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
226#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
227
228
229/*---------------------TMS570_DMAGCHIENAS---------------------*/
230/* field: GCHIE - Global channel interrupt enable bit. */
231#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
232#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
233#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
234
235
236/*---------------------TMS570_DMAGCHIENAR---------------------*/
237/* field: GCHID - Global channel interrupt disable bit. */
238#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
239#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
240#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
241
242
243/*---------------------TMS570_DMADREQASI---------------------*/
244/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
245#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
246#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
247#define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29)
248
249/* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */
250#define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21)
251#define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21)
252#define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
253
254/* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */
255#define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13)
256#define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13)
257#define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
258
259/* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */
260#define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5)
261#define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5)
262#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
263
264
265/*-----------------------TMS570_DMAPAR0-----------------------*/
266/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
267#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
268#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
269#define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
270
271/* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */
272#define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26)
273#define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26)
274#define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
275
276/* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */
277#define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22)
278#define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22)
279#define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
280
281/* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */
282#define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18)
283#define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18)
284#define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
285
286/* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */
287#define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14)
288#define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14)
289#define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
290
291/* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */
292#define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10)
293#define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10)
294#define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
295
296/* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */
297#define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6)
298#define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6)
299#define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
300
301/* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */
302#define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2)
303#define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2)
304#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
305
306
307/*-----------------------TMS570_DMAPAR1-----------------------*/
308/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
309#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
310#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
311#define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
312
313/* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */
314#define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26)
315#define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26)
316#define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
317
318/* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */
319#define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22)
320#define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22)
321#define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
322
323/* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */
324#define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18)
325#define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18)
326#define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
327
328/* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */
329#define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14)
330#define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14)
331#define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
332
333/* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */
334#define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10)
335#define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10)
336#define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
337
338/* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */
339#define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6)
340#define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6)
341#define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
342
343/* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */
344#define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2)
345#define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2)
346#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
347
348
349/*----------------------TMS570_DMAFTCMAP----------------------*/
350/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
351#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
352#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
353#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
354
355
356/*----------------------TMS570_DMALFSMAP----------------------*/
357/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
358#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
359#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
360#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
361
362
363/*----------------------TMS570_DMAHBCMAP----------------------*/
364/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
365#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
366#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
367#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
368
369
370/*----------------------TMS570_DMABTCMAP----------------------*/
371/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
372#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
373#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
374#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
375
376
377/*----------------------TMS570_DMABERMAP----------------------*/
378/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
379#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
380#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
381#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
382
383
384/*--------------------TMS570_DMAFTCINTENAS--------------------*/
385/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
386#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
387#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
388#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
389
390
391/*--------------------TMS570_DMAFTCINTENAR--------------------*/
392/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
393#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
394#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
395#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
396
397
398/*--------------------TMS570_DMALFSINTENAS--------------------*/
399/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
400#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
401#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
402#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
403
404
405/*--------------------TMS570_DMALFSINTENAR--------------------*/
406/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
407#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
408#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
409#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
410
411
412/*--------------------TMS570_DMAHBCINTENAS--------------------*/
413/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
414#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
415#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
416#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
417
418
419/*--------------------TMS570_DMAHBCINTENAR--------------------*/
420/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
421#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
422#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
423#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
424
425
426/*--------------------TMS570_DMABTCINTENAS--------------------*/
427/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
428#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
429#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
430#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
431
432
433/*--------------------TMS570_DMABTCINTENAR--------------------*/
434/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
435#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
436#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
437#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
438
439
440/*---------------------TMS570_DMAGINTFLAG---------------------*/
441/* field: GINT - Global interrupt flags. */
442#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
443#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
444#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
445
446
447/*---------------------TMS570_DMAFTCFLAG---------------------*/
448/* field: FTCI - Frame transfer complete (FTC) flags. */
449#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
450#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
451#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
452
453
454/*---------------------TMS570_DMALFSFLAG---------------------*/
455/* field: LFSI - Last frame started (LFS) flags. */
456#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
457#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
458#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
459
460
461/*---------------------TMS570_DMAHBCFLAG---------------------*/
462/* field: HBCI - Half block transfer (HBC) complete flags. */
463#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
464#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
465#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
466
467
468/*---------------------TMS570_DMABTCFLAG---------------------*/
469/* field: BTCI - Block transfer complete (BTC) flags. */
470#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
471#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
472#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
473
474
475/*---------------------TMS570_DMABERFLAG---------------------*/
476/* field: BERI - Bus error (BER) flags. */
477#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
478#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
479#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
480
481
482/*--------------------TMS570_DMAFTCAOFFSET--------------------*/
483/* field: sbz - These bits should always be programmed as zero. */
484#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
485#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
486#define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
487
488/* field: FTCA - Channel causing FTC interrupt Group A. */
489#define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5)
490#define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
491#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
492
493
494/*--------------------TMS570_DMALFSAOFFSET--------------------*/
495/* field: LFSA - Channel causing LFS interrupt Group A. */
496#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
497#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
498#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
499
500
501/*--------------------TMS570_DMAHBCAOFFSET--------------------*/
502/* field: HBCA - Channel causing HBC interrupt Group A. */
503#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
504#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
505#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
506
507
508/*--------------------TMS570_DMABTCAOFFSET--------------------*/
509/* field: BTCA - Channel causing BTC interrupt Group A. */
510#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
511#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
512#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
513
514
515/*--------------------TMS570_DMABERAOFFSET--------------------*/
516/* field: BERA - Channel causing BER interrupt Group A. */
517#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
518#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
519#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
520
521
522/*--------------------TMS570_DMAFTCBOFFSET--------------------*/
523/* field: FTCB - Channel causing FTC interrupt Group B. */
524#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
525#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
526#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
527
528
529/*--------------------TMS570_DMALFSBOFFSET--------------------*/
530/* field: LFSB - Channel causing LFS interrupt Group B. */
531#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
532#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
533#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
534
535
536/*--------------------TMS570_DMAHBCBOFFSET--------------------*/
537/* field: HBCB - Channel causing HBC interrupt Group B. */
538#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
539#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
540#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
541
542
543/*--------------------TMS570_DMABTCBOFFSET--------------------*/
544/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
545#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
546#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
547#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
548
549
550/*--------------------TMS570_DMABERBOFFSET--------------------*/
551/* field: BERB - Channel causing BER interrupt Group B. */
552#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
553#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
554#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
555
556
557/*----------------------TMS570_DMAPTCRL----------------------*/
558/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
559#define TMS570_DMA_PTCRL_PENDB BSP_FLD32(24)
560
561/* field: BYB - Bypass FIFO B. */
562#define TMS570_DMA_PTCRL_BYB BSP_FLD32(18)
563
564/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
565#define TMS570_DMA_PTCRL_PSFRHQPB BSP_FLD32(17)
566
567/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
568#define TMS570_DMA_PTCRL_PSFRLQPB BSP_FLD32(16)
569
570
571/*----------------------TMS570_DMARTCTRL----------------------*/
572/* field: RTC - RAM Test Control. */
573#define TMS570_DMA_RTCTRL_RTC BSP_FLD32(0)
574
575
576/*----------------------TMS570_DMADCTRL----------------------*/
577/* field: CHNUM - Channel Number. */
578#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
579#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
580#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
581
582/* field: DMADBGS - DMA debug status. */
583#define TMS570_DMA_DCTRL_DMADBGS BSP_FLD32(16)
584
585/* field: DBGEN - Debug Enable. */
586#define TMS570_DMA_DCTRL_DBGEN BSP_FLD32(0)
587
588
589/*-----------------------TMS570_DMAWPR-----------------------*/
590/* field: WP - Watch point. */
591#define TMS570_DMA_WPR_WP(val) BSP_FLD32(val,0, 31)
592#define TMS570_DMA_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
593#define TMS570_DMA_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
594
595
596/*-----------------------TMS570_DMAWMR-----------------------*/
597/* field: WM - Watch mask. */
598#define TMS570_DMA_WMR_WM(val) BSP_FLD32(val,0, 31)
599#define TMS570_DMA_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
600#define TMS570_DMA_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
601
602
603/*--------------------TMS570_DMAPBACSADDR--------------------*/
604/* field: PBACSA - Port B Active Channel Source Address. */
605#define TMS570_DMA_PBACSADDR_PBACSA(val) BSP_FLD32(val,0, 31)
606#define TMS570_DMA_PBACSADDR_PBACSA_GET(reg) BSP_FLD32GET(reg,0, 31)
607#define TMS570_DMA_PBACSADDR_PBACSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
608
609
610/*--------------------TMS570_DMAPBACDADDR--------------------*/
611/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
612#define TMS570_DMA_PBACDADDR_PBACDA(val) BSP_FLD32(val,0, 31)
613#define TMS570_DMA_PBACDADDR_PBACDA_GET(reg) BSP_FLD32GET(reg,0, 31)
614#define TMS570_DMA_PBACDADDR_PBACDA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
615
616
617/*----------------------TMS570_DMAPBACTC----------------------*/
618/* field: PBFTCOUNT - Port B active channel frame count. */
619#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
620#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
621#define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28)
622
623/* field: PBETCOUNT - Port B active channel element count. */
624#define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12)
625#define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12)
626#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
627
628
629/*----------------------TMS570_DMADMAPCR----------------------*/
630/* field: ERRA - Error action. */
631#define TMS570_DMA_DMAPCR_ERRA BSP_FLD32(16)
632
633/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
634#define TMS570_DMA_DMAPCR_TEST BSP_FLD32(8)
635
636/* field: PARITY_ENA - Parity error detection enable. */
637#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
638#define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
639#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
640
641
642/*----------------------TMS570_DMADMAPAR----------------------*/
643/* field: EDFLAG - Parity Error Detection Flag. */
644#define TMS570_DMA_DMAPAR_EDFLAG BSP_FLD32(24)
645
646/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
647#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
648#define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11)
649#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
650
651
652/*--------------------TMS570_DMADMAMPCTRL--------------------*/
653/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
654#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_FLD32(28)
655
656/* field: INT3ENA - Interrupt enable of region 3. */
657#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_FLD32(27)
658
659/* field: REG3AP - Region 3 access permission. */
660#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
661#define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26)
662#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
663
664/* field: REG3ENA - Region 3 enable. */
665#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_FLD32(24)
666
667/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
668#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_FLD32(20)
669
670/* field: INT2ENA - Interrupt enable of region 2. */
671#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_FLD32(19)
672
673/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
674#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
675#define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18)
676#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
677
678/* field: REG2ENA - Region 2 enable. */
679#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_FLD32(16)
680
681/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
682#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_FLD32(12)
683
684/* field: INT1ENA - Interrupt enable of region 1. */
685#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_FLD32(11)
686
687/* field: REG1AP - Region 1 access permission. */
688#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
689#define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10)
690#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
691
692/* field: REG1ENA - Region 1 enable. */
693#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_FLD32(8)
694
695/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
696#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_FLD32(4)
697
698/* field: INT0ENA - Interrupt enable of region 0. */
699#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_FLD32(3)
700
701/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
702#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
703#define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2)
704#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
705
706/* field: REG0ENA - Region 0 enable. */
707#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_FLD32(0)
708
709
710/*---------------------TMS570_DMADMAMPST---------------------*/
711/* field: REG3FT - Region 3 fault. */
712#define TMS570_DMA_DMAMPST_REG3FT BSP_FLD32(24)
713
714/* field: REG2FT - Region 2 fault. */
715#define TMS570_DMA_DMAMPST_REG2FT BSP_FLD32(16)
716
717/* field: REG1FT - Region 1 fault. */
718#define TMS570_DMA_DMAMPST_REG1FT BSP_FLD32(8)
719
720/* field: REG0FT - Region 0 fault. */
721#define TMS570_DMA_DMAMPST_REG0FT BSP_FLD32(0)
722
723
724/*---------------------TMS570_DMADMAMPROS---------------------*/
725/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
726#define TMS570_DMA_DMAMPROS_STARTADDRESS(val) BSP_FLD32(val,0, 31)
727#define TMS570_DMA_DMAMPROS_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
728#define TMS570_DMA_DMAMPROS_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
729
730
731
732#endif /* LIBBSP_ARM_tms570_DMA */
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