source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 20.3 KB
Line 
1/* The header file is generated by make_header.py from CRC.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_CRC
40#define LIBBSP_ARM_tms570_CRC
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t CTRL0;             /*CRC Global Control Register*/
46  uint8_t reserved1 [4];
47  uint32_t CTRL1;             /*CRC Global Control Register 1*/
48  uint8_t reserved2 [4];
49  uint32_t CTRL2;             /*CRC Global Control Register 2*/
50  uint8_t reserved3 [4];
51  uint32_t INTS;              /*CRC Interrupt Enable Set Register*/
52  uint8_t reserved4 [4];
53  uint32_t INTR;              /*CRC Interrupt Enable Reset Register*/
54  uint8_t reserved5 [4];
55  uint32_t STATUS;            /*CRC Interrupt Status Register*/
56  uint8_t reserved6 [4];
57  uint32_t INT_OFFS_REG;      /*CRC Interrupt Offset Register*/
58  uint8_t reserved7 [4];
59  uint32_t BUSY;              /*CRC Busy Register*/
60  uint8_t reserved8 [4];
61  uint32_t PCOUNT_REG1;       /*CRC Channel 1 Pattern Counter Preload Register*/
62  uint32_t SCOUNT_REG1;       /*CRC Channel 1 Sector Counter Preload Register*/
63  uint32_t CURSEC_REG1;       /*CRC Channel 1 Current Sector Register*/
64  uint32_t WDTOPLD1;          /*CRC Channel 1 Watchdog Timeout Preload Register*/
65  uint32_t BCTOPLD1;          /*CRC Channel 1 Block Complete Timeout Preload Register*/
66  uint8_t reserved9 [12];
67  uint32_t PSA_SIGREGL1;      /*Channel 1 PSA Signature Low Register*/
68  uint32_t PSA_SIGREGH1;      /*Channel 1 PSA Signature High Register*/
69  uint32_t REGL1;             /*Channel 1 CRC Value Low Register*/
70  uint32_t REGH1;             /*Channel 1 CRC Value High Register*/
71  uint32_t PSA_SECSIGREGL1;   /*Channel 1 PSA Sector Signature Low Register*/
72  uint32_t PSA_SECSIGREGH1;   /*Channel 1 PSA Sector Signature High Register*/
73  uint32_t RAW_DATAREGL1;     /*Channel 1 Raw Data Low Register*/
74  uint32_t RAW_DATAREGH1;     /*Channel 1 Raw Data High Register*/
75  uint32_t PCOUNT_REG2;       /*CRC Channel 2 Pattern Counter Preload Register*/
76  uint32_t SCOUNT_REG2;       /*CRC Channel 2 Sector Counter Preload Register*/
77  uint32_t CURSEC_REG2;       /*CRC Current Sector Register 2*/
78  uint32_t WDTOPLD2;          /*CRC Channel 2 Watchdog Timeout Preload Register A*/
79  uint32_t BCTOPLD2;          /*CRC Channel 2 Block Complete Timeout Preload Register B*/
80  uint8_t reserved10 [12];
81  uint32_t PSA_SIGREGL2;      /*Channel 2 PSA Signature Low Register*/
82  uint32_t PSA_SIGREGH2;      /*Channel 2 PSA Signature High Register*/
83  uint32_t REGL2;             /*Channel 2 CRC Value Low Register*/
84  uint32_t REGH2;             /*Channel 2 CRC Value High Register*/
85  uint32_t PSA_SECSIGREGL2;   /*Channel 2 PSA Sector Signature Low Register*/
86  uint32_t PSA_SECSIGREGH2;   /*Channel 2 PSA Sector Signature High Register*/
87  uint32_t RAW_DATAREGL2;     /*Channel 2 Raw Data Low Register*/
88  uint32_t RAW_DATAREGH2;     /*Channel 2 Raw Data High Register*/
89  uint8_t reserved11 [128];
90  uint32_t BUS_SEL;           /*Data Bus Selection Register*/
91} tms570_crc_t;
92
93
94/*----------------------TMS570_CRCCTRL0----------------------*/
95/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
96#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
97
98/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
99#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
100
101
102/*----------------------TMS570_CRCCTRL1----------------------*/
103/* field: PWDN - Power Down. */
104#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
105
106
107/*----------------------TMS570_CRCCTRL2----------------------*/
108/* field: CH2_MODE - Channel 2 Mode Selection */
109#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
110#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
111#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
112
113/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
114#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
115
116/* field: CH1_MODE - Channel 1 Mode Selection */
117#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
118#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1)
119#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
120
121
122/*-----------------------TMS570_CRCINTS-----------------------*/
123/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
124#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
125
126/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
127#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
128
129/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
130#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
131
132/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
133#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
134
135/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
136#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
137
138/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
139#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
140
141/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
142#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
143
144/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
145#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
146
147/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
148#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
149
150/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
151#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
152
153
154/*-----------------------TMS570_CRCINTR-----------------------*/
155/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
156#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
157
158/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
159#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
160
161/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
162#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
163
164/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
165#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
166
167/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
168#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
169
170/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
171#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
172
173/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
174#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
175
176/* field: CH1_OVERENR - CH1_OVERENR */
177#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
178
179/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
180#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
181
182/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
183#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
184
185
186/*----------------------TMS570_CRCSTATUS----------------------*/
187/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
188#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
189
190/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
191#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
192
193/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
194#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
195
196/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
197#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
198
199/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
200#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
201
202/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
203#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
204
205/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
206#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
207
208/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
209#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
210
211/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
212#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
213
214/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
215#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
216
217
218/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
219/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
220#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
221#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
222#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
223
224
225/*-----------------------TMS570_CRCBUSY-----------------------*/
226/* field: CH2_BUSY - CH2_BUSY. */
227#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
228
229/* field: CH1_BUSY - CH1_BUSY. */
230#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
231
232
233/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
234/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
235#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
236#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
237#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
238
239
240/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
241/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
242#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
243#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
244#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
245
246
247/*-------------------TMS570_CRCCURSEC_REG1-------------------*/
248/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
249#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
250#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
251#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
252
253
254/*---------------------TMS570_CRCWDTOPLD1---------------------*/
255/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
256#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
257#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
258#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
259
260
261/*---------------------TMS570_CRCBCTOPLD1---------------------*/
262/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
263#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
264#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
265#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
266
267
268/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
269/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
270#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
271#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
272#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
273
274
275/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
276/* field: PSASIG1 - register. */
277#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
278#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
279#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
280
281
282/*----------------------TMS570_CRCREGL1----------------------*/
283/* field: CRC1 - Channel 1 CRC Value Low Register. */
284#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
285#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
286#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
287
288
289/*----------------------TMS570_CRCREGH1----------------------*/
290/* field: CRC1 - Channel 1 CRC Value Low Register. */
291#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
292#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
293#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
294
295
296/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
297/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
298#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
299#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
300#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
301
302
303/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
304/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
305#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
306#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
307#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
308
309
310/*------------------TMS570_CRCRAW_DATAREGL1------------------*/
311/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
312#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
313#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
314#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
315
316
317/*------------------TMS570_CRCRAW_DATAREGH1------------------*/
318/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
319#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
320#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
321#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
322
323
324/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
325/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
326#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
327#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
328#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
329
330
331/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
332/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
333#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
334#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
335#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
336
337
338/*-------------------TMS570_CRCCURSEC_REG2-------------------*/
339/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
340#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
341#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
342#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
343
344
345/*---------------------TMS570_CRCWDTOPLD2---------------------*/
346/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
347#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
348#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
349#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
350
351
352/*---------------------TMS570_CRCBCTOPLD2---------------------*/
353/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
354#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
355#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
356#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
357
358
359/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
360/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
361#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
362#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
363#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
364
365
366/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
367/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
368#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
369#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
370#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
371
372
373/*----------------------TMS570_CRCREGL2----------------------*/
374/* field: CRC2 - stored at CRC2[31:0] register. */
375#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
376#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
377#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
378
379
380/*----------------------TMS570_CRCREGH2----------------------*/
381/* field: CRC2 - Channel 2 CRC Value High Register. */
382#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
383#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
384#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
385
386
387/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
388/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
389#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
390#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
391#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
392
393
394/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
395/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
396#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
397#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
398#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
399
400
401/*------------------TMS570_CRCRAW_DATAREGL2------------------*/
402/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
403#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
404#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
405#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
406
407
408/*------------------TMS570_CRCRAW_DATAREGH2------------------*/
409/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
410#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
411#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
412#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
413
414
415/*---------------------TMS570_CRCBUS_SEL---------------------*/
416/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
417#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
418
419/* field: DTCMEn - Enable/disables the tracing of data TCM */
420#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
421
422/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
423#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
424
425
426
427#endif /* LIBBSP_ARM_tms570_CRC */
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