source: rtems/c/src/lib/libbsp/arm/tms570/include/irq.h @ cf4dfc1

4.11
Last change on this file since cf4dfc1 was 4407ee6, checked in by Premysl Houdek <kom541000@…>, on Aug 20, 2014 at 3:24:23 PM

BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)

Included variants:

tms570ls3137_hdk_intram - place code and data into internal SRAM
tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication

stored and running directly from flash. Not working yet.

Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen? was used for
testing and debugging.

More information about TMS570 BSP can be found at

http://www.rtems.org/wiki/index.php/Tms570

Patch version 2

  • most of the formatting suggestion applied.
  • BSP converted to use clock shell
  • console driver "set attributes" tested. Baudrate change working

Patch version 3

  • more formatting changes.
  • removed leftover defines and test functions

Todo:

refactor header files (name register fields)

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/**
2 * @file irq.h
3 *
4 * @ingroup tms570
5 *
6 * @brief TMS570 interrupt definitions.
7 */
8
9/*
10 * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com>
11 *
12 * Google Summer of Code 2014 at
13 * Czech Technical University in Prague
14 * Zikova 1903/4
15 * 166 36 Praha 6
16 * Czech Republic
17 *
18 * Based on LPC24xx and LPC1768 BSP
19 * by embedded brains GmbH and others
20 *
21 * The license and distribution terms for this file may be
22 * found in the file LICENSE in this distribution or at
23 * http://www.rtems.org/license/LICENSE.
24 */
25
26#ifndef LIBBSP_ARM_TMS570_IRQ_H
27#define LIBBSP_ARM_TMS570_IRQ_H
28
29#ifndef ASM
30#include <rtems.h>
31#include <rtems/irq.h>
32#include <rtems/irq-extension.h>
33#endif
34
35#define BSP_INTERRUPT_VECTOR_MIN 0U
36#define TMS570_IRQ_ESM_HIGH 0
37#define TMS570_IRQ_RESERVED 1
38#define TMS570_IRQ_TIMER_0 2
39#define TMS570_IRQ_TIMER_1 3
40#define TMS570_IRQ_TIMER_2 4
41#define TMS570_IRQ_TIMER_3 5
42#define TMS570_IRQ_RTI_OVERFLOW_0 6
43#define TMS570_IRQ_RTI_OVERFLOW_1 7
44#define TMS570_IRQ_RTI_TIMEBASE 8
45#define TMS570_IRQ_GIO_HIGH 9
46#define TMS570_IRQ_HET_HIGH 10
47#define TMS570_IRQ_HET_TU_HIGH 11
48#define TMS570_IRQ_MIBSPI1_HIGH 12
49#define TMS570_IRQ_SCI_LEVEL_0 13
50#define TMS570_IRQ_ADC1_EVENT 14
51#define TMS570_IRQ_ADC1_GROUP_1 15
52#define TMS570_IRQ_CAN1_HIGH 16
53#define TMS570_IRQ_RESERVED 17
54#define TMS570_IRQ_FLEXRAY_HIGH 18
55#define TMS570_IRQ_CRC_1 19
56#define TMS570_IRQ_ESM_LOW 20
57#define TMS570_IRQ_SSI 21
58#define TMS570_IRQ_PMU 22
59#define TMS570_IRQ_GIO_LOW 23
60#define TMS570_IRQ_HET_LOW 24
61#define TMS570_IRQ_HET_TU_LOW 25
62#define TMS570_IRQ_MIBSPI1_LOW 26
63#define TMS570_IRQ_SCI_LEVEL_1 27
64#define TMS570_IRQ_ADC1_GROUP_2 28
65#define TMS570_IRQ_CAN1_LOW 29
66#define TMS570_IRQ_RESERVED
67#define TMS570_IRQ_ADC1_MAG 31
68#define TMS570_IRQ_FLEXRAY_LOW 32
69#define TMS570_IRQ_DMA_FTCA 33
70#define TMS570_IRQ_DMA_LFSA 34
71#define TMS570_IRQ_CAN2_HIGH 35
72#define TMS570_IRQ_DMM_HIGH 36
73#define TMS570_IRQ_MIBSPI3_HIGH 37
74#define TMS570_IRQ_MIBSPI3_LOW 38
75#define TMS570_IRQ_DMA_HBCA 39
76#define TMS570_IRQ_DMA_BTCA 40
77#define TMS570_IRQ_DMA_BERA 41
78#define TMS570_IRQ_CAN2_LOW 42
79#define TMS570_IRQ_DMM_LOW 43
80#define TMS570_IRQ_CAN1_IF3 44
81#define TMS570_IRQ_CAN3_HIGH 45
82#define TMS570_IRQ_CAN2_IF3 46
83#define TMS570_IRQ_FPU 47
84#define TMS570_IRQ_FLEXRAY_TU 48
85#define TMS570_IRQ_SPI4_HIGH 49
86#define TMS570_IRQ_ADC2_EVENT 50
87#define TMS570_IRQ_ADC2_GROUP_1 51
88#define TMS570_IRQ_FLEXRAY_T0C 52
89#define TMS570_IRQ_MIBSPIP5_HIGH 53
90#define TMS570_IRQ_SPI4_LOW 54
91#define TMS570_IRQ_CAN3_LOW 55
92#define TMS570_IRQ_MIBSPIP5_LOW 56
93#define TMS570_IRQ_ADC2_GROUP_2 57
94#define TMS570_IRQ_FLEXRAY_TU_ERROR 58
95#define TMS570_IRQ_ADC2_MAG 59
96#define TMS570_IRQ_CAN3_IF3 60
97#define TMS570_IRQ_FSM_DONE 61
98#define TMS570_IRQ_FLEXRAY_T1C 62
99#define TMS570_IRQ_HET2_LEVEL_0 63
100#define TMS570_IRQ_SCI2_LEVEL_0 64
101#define TMS570_IRQ_HET_TU2_LEVEL_0 65
102#define TMS570_IRQ_IC2_INTERRUPT 66
103#define TMS570_IRQ_HET2_LEVEL_1 73
104#define TMS570_IRQ_SCI2_LEVEL_1 74
105#define TMS570_IRQ_HET_TU2_LEVEL_1 75
106#define TMS570_IRQ_HWA_INT_REQ_H 80
107#define TMS570_IRQ_HWA_INT_REQ_H 81
108#define TMS570_IRQ_DCC_DONE_INTERRUPT 82
109#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83
110#define TMS570_IRQ_HWAG1_INT_REQ_L 88
111#define TMS570_IRQ_HWAG2_INT_REQ_L 89
112#define BSP_INTERRUPT_VECTOR_MAX 94
113
114#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U
115#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U
116
117#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U )
118#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN
119#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX
120
121#ifndef ASM
122
123/**
124 * @brief Set priority of the interrupt vector.
125 *
126 * This function is here because of compability. It should set
127 * priority of the interrupt vector.
128 * @warning It does not set any priority at HW layer. It is nearly imposible to
129 * @warning set priority of the interrupt on TMS570 in a nice way.
130 * @param[in] vector vector of isr
131 * @param[in] priority new priority assigned to the vector
132 * @return Void
133 */
134void tms570_irq_set_priority(
135  rtems_vector_number vector,
136  unsigned            priority
137);
138
139/**
140 * @brief Gets priority of the interrupt vector.
141 *
142 * This function is here because of compability. It returns priority
143 * of the isr vector last set by tms570_irq_set_priority function.
144 *
145 * @warning It does not return any real priority of the HW layer.
146 * @param[in] vector vector of isr
147 * @retval 0 vector is invalid.
148 * @retval priority priority of the interrupt
149 */
150unsigned tms570_irq_get_priority( rtems_vector_number vector );
151
152#endif /* ASM */
153
154/** @} */
155
156#endif /* LIBBSP_ARM_TMS570_IRQ_H */
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