1 | /** |
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2 | * @file irq.h |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief TMS570 interrupt definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> |
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11 | * |
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12 | * Google Summer of Code 2014 at |
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13 | * Czech Technical University in Prague |
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14 | * Zikova 1903/4 |
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15 | * 166 36 Praha 6 |
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16 | * Czech Republic |
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17 | * |
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18 | * Based on LPC24xx and LPC1768 BSP |
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19 | * by embedded brains GmbH and others |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in the file LICENSE in this distribution or at |
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23 | * http://www.rtems.org/license/LICENSE. |
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24 | */ |
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25 | |
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26 | #ifndef LIBBSP_ARM_TMS570_IRQ_H |
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27 | #define LIBBSP_ARM_TMS570_IRQ_H |
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28 | |
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29 | #ifndef ASM |
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30 | #include <rtems.h> |
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31 | #include <rtems/irq.h> |
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32 | #include <rtems/irq-extension.h> |
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33 | #endif |
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34 | |
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35 | #define BSP_INTERRUPT_VECTOR_MIN 0U |
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36 | #define TMS570_IRQ_ESM_HIGH 0 |
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37 | #define TMS570_IRQ_RESERVED 1 |
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38 | #define TMS570_IRQ_TIMER_0 2 |
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39 | #define TMS570_IRQ_TIMER_1 3 |
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40 | #define TMS570_IRQ_TIMER_2 4 |
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41 | #define TMS570_IRQ_TIMER_3 5 |
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42 | #define TMS570_IRQ_RTI_OVERFLOW_0 6 |
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43 | #define TMS570_IRQ_RTI_OVERFLOW_1 7 |
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44 | #define TMS570_IRQ_RTI_TIMEBASE 8 |
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45 | #define TMS570_IRQ_GIO_HIGH 9 |
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46 | #define TMS570_IRQ_HET_HIGH 10 |
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47 | #define TMS570_IRQ_HET_TU_HIGH 11 |
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48 | #define TMS570_IRQ_MIBSPI1_HIGH 12 |
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49 | #define TMS570_IRQ_SCI_LEVEL_0 13 |
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50 | #define TMS570_IRQ_ADC1_EVENT 14 |
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51 | #define TMS570_IRQ_ADC1_GROUP_1 15 |
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52 | #define TMS570_IRQ_CAN1_HIGH 16 |
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53 | #define TMS570_IRQ_RESERVED 17 |
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54 | #define TMS570_IRQ_FLEXRAY_HIGH 18 |
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55 | #define TMS570_IRQ_CRC_1 19 |
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56 | #define TMS570_IRQ_ESM_LOW 20 |
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57 | #define TMS570_IRQ_SSI 21 |
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58 | #define TMS570_IRQ_PMU 22 |
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59 | #define TMS570_IRQ_GIO_LOW 23 |
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60 | #define TMS570_IRQ_HET_LOW 24 |
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61 | #define TMS570_IRQ_HET_TU_LOW 25 |
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62 | #define TMS570_IRQ_MIBSPI1_LOW 26 |
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63 | #define TMS570_IRQ_SCI_LEVEL_1 27 |
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64 | #define TMS570_IRQ_ADC1_GROUP_2 28 |
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65 | #define TMS570_IRQ_CAN1_LOW 29 |
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66 | #define TMS570_IRQ_RESERVED |
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67 | #define TMS570_IRQ_ADC1_MAG 31 |
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68 | #define TMS570_IRQ_FLEXRAY_LOW 32 |
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69 | #define TMS570_IRQ_DMA_FTCA 33 |
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70 | #define TMS570_IRQ_DMA_LFSA 34 |
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71 | #define TMS570_IRQ_CAN2_HIGH 35 |
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72 | #define TMS570_IRQ_DMM_HIGH 36 |
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73 | #define TMS570_IRQ_MIBSPI3_HIGH 37 |
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74 | #define TMS570_IRQ_MIBSPI3_LOW 38 |
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75 | #define TMS570_IRQ_DMA_HBCA 39 |
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76 | #define TMS570_IRQ_DMA_BTCA 40 |
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77 | #define TMS570_IRQ_DMA_BERA 41 |
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78 | #define TMS570_IRQ_CAN2_LOW 42 |
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79 | #define TMS570_IRQ_DMM_LOW 43 |
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80 | #define TMS570_IRQ_CAN1_IF3 44 |
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81 | #define TMS570_IRQ_CAN3_HIGH 45 |
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82 | #define TMS570_IRQ_CAN2_IF3 46 |
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83 | #define TMS570_IRQ_FPU 47 |
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84 | #define TMS570_IRQ_FLEXRAY_TU 48 |
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85 | #define TMS570_IRQ_SPI4_HIGH 49 |
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86 | #define TMS570_IRQ_ADC2_EVENT 50 |
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87 | #define TMS570_IRQ_ADC2_GROUP_1 51 |
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88 | #define TMS570_IRQ_FLEXRAY_T0C 52 |
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89 | #define TMS570_IRQ_MIBSPIP5_HIGH 53 |
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90 | #define TMS570_IRQ_SPI4_LOW 54 |
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91 | #define TMS570_IRQ_CAN3_LOW 55 |
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92 | #define TMS570_IRQ_MIBSPIP5_LOW 56 |
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93 | #define TMS570_IRQ_ADC2_GROUP_2 57 |
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94 | #define TMS570_IRQ_FLEXRAY_TU_ERROR 58 |
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95 | #define TMS570_IRQ_ADC2_MAG 59 |
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96 | #define TMS570_IRQ_CAN3_IF3 60 |
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97 | #define TMS570_IRQ_FSM_DONE 61 |
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98 | #define TMS570_IRQ_FLEXRAY_T1C 62 |
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99 | #define TMS570_IRQ_HET2_LEVEL_0 63 |
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100 | #define TMS570_IRQ_SCI2_LEVEL_0 64 |
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101 | #define TMS570_IRQ_HET_TU2_LEVEL_0 65 |
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102 | #define TMS570_IRQ_IC2_INTERRUPT 66 |
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103 | #define TMS570_IRQ_HET2_LEVEL_1 73 |
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104 | #define TMS570_IRQ_SCI2_LEVEL_1 74 |
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105 | #define TMS570_IRQ_HET_TU2_LEVEL_1 75 |
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106 | #define TMS570_IRQ_EMAC_MISC 76 |
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107 | #define TMS570_IRQ_EMAC_TX 77 |
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108 | #define TMS570_IRQ_EMAC_THRESH 78 |
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109 | #define TMS570_IRQ_EMAC_RX 79 |
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110 | #define TMS570_IRQ_HWA_INT_REQ_H 80 |
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111 | #define TMS570_IRQ_HWA_INT_REQ_H 81 |
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112 | #define TMS570_IRQ_DCC_DONE_INTERRUPT 82 |
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113 | #define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 |
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114 | #define TMS570_IRQ_HWAG1_INT_REQ_L 88 |
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115 | #define TMS570_IRQ_HWAG2_INT_REQ_L 89 |
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116 | #define BSP_INTERRUPT_VECTOR_MAX 94 |
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117 | |
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118 | #define TMS570_IRQ_PRIORITY_VALUE_MIN 0U |
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119 | #define TMS570_IRQ_PRIORITY_VALUE_MAX 0U |
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120 | |
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121 | #define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) |
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122 | #define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN |
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123 | #define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX |
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124 | |
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125 | #ifndef ASM |
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126 | |
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127 | /** |
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128 | * @brief Set priority of the interrupt vector. |
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129 | * |
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130 | * This function is here because of compability. It should set |
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131 | * priority of the interrupt vector. |
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132 | * @warning It does not set any priority at HW layer. It is nearly imposible to |
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133 | * @warning set priority of the interrupt on TMS570 in a nice way. |
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134 | * @param[in] vector vector of isr |
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135 | * @param[in] priority new priority assigned to the vector |
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136 | * @return Void |
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137 | */ |
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138 | void tms570_irq_set_priority( |
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139 | rtems_vector_number vector, |
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140 | unsigned priority |
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141 | ); |
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142 | |
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143 | /** |
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144 | * @brief Gets priority of the interrupt vector. |
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145 | * |
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146 | * This function is here because of compability. It returns priority |
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147 | * of the isr vector last set by tms570_irq_set_priority function. |
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148 | * |
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149 | * @warning It does not return any real priority of the HW layer. |
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150 | * @param[in] vector vector of isr |
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151 | * @retval 0 vector is invalid. |
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152 | * @retval priority priority of the interrupt |
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153 | */ |
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154 | unsigned tms570_irq_get_priority( rtems_vector_number vector ); |
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155 | |
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156 | #endif /* ASM */ |
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157 | |
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158 | /** @} */ |
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159 | |
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160 | #endif /* LIBBSP_ARM_TMS570_IRQ_H */ |
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