source: rtems/c/src/lib/libbsp/arm/tms570/hwinit/tms570_tcram_tests.c @ b2ed712

Last change on this file since b2ed712 was 29430a3, checked in by Pavel Pisa <pisa@…>, on Sep 22, 2016 at 7:50:59 AM

arm/tms570: include hardware initialization and selftest based on Ti HalCoGen? generated files.

The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in

rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c

file.

The list tms570_selftest_par_list in the file

rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c

specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.

  • Property mode set to 100644
File size: 6.2 KB
Line 
1/**
2 * @file tms570_tcram_tests.c
3 *
4 * @ingroup tms570
5 *
6 * @brief TCRAM selftest function.
7 */
8/*
9 * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
10 *
11 * Czech Technical University in Prague
12 * Zikova 1903/4
13 * 166 36 Praha 6
14 * Czech Republic
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 *
20 * Algorithms are based on Ti manuals and Ti HalCoGen generated
21 * code available under following copyright.
22 */
23/*
24 * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
25 *
26 *
27 *  Redistribution and use in source and binary forms, with or without
28 *  modification, are permitted provided that the following conditions
29 *  are met:
30 *
31 *    Redistributions of source code must retain the above copyright
32 *    notice, this list of conditions and the following disclaimer.
33 *
34 *    Redistributions in binary form must reproduce the above copyright
35 *    notice, this list of conditions and the following disclaimer in the
36 *    documentation and/or other materials provided with the
37 *    distribution.
38 *
39 *    Neither the name of Texas Instruments Incorporated nor the names of
40 *    its contributors may be used to endorse or promote products derived
41 *    from this software without specific prior written permission.
42 *
43 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 */
56
57#include <stdint.h>
58#include <bsp/tms570.h>
59#include "tms570_selftest.h"
60#include "tms570_hwinit.h"
61
62#define tcramA1bitError (*(volatile uint32_t *)(0x08400000U))
63#define tcramA2bitError (*(volatile uint32_t *)(0x08400010U))
64
65#define tcramB1bitError (*(volatile uint32_t *)(0x08400008U))
66#define tcramB2bitError (*(volatile uint32_t *)(0x08400018U))
67
68#define tcramA1bit      (*(volatile uint64_t *)(0x08000000U))
69#define tcramA2bit      (*(volatile uint64_t *)(0x08000010U))
70
71#define tcramB1bit      (*(volatile uint64_t *)(0x08000008U))
72#define tcramB2bit      (*(volatile uint64_t *)(0x08000018U))
73
74/**
75 * @brief Check TCRAM ECC error detection logic (HCG:checkRAMECC)
76 *
77 * This function checks TCRAM ECC error detection and correction logic.
78 * The function does not return in case of TCRAM error.
79 * It calls bsp_selftest_fail_notification() instead.
80 *
81 */
82/* SourceId : SELFTEST_SourceId_034 */
83/* DesignId : SELFTEST_DesignId_019 */
84/* Requirements : HL_SR408 */
85void  tms570_check_tcram_ecc( void )
86{
87  volatile uint64_t ramread;
88  volatile uint32_t regread;
89  uint32_t tcram1ErrStat, tcram2ErrStat = 0U;
90
91  uint64_t tcramA1_bk = tcramA1bit;
92  uint64_t tcramB1_bk = tcramB1bit;
93  uint64_t tcramA2_bk = tcramA2bit;
94  uint64_t tcramB2_bk = tcramB2bit;
95
96  /* Clear RAMOCUUR before setting RAMTHRESHOLD register */
97  TMS570_TCRAM1.RAMOCCUR = 0U;
98  TMS570_TCRAM2.RAMOCCUR = 0U;
99
100  /* Set Single-bit Error Threshold Count as 1 */
101  TMS570_TCRAM1.RAMTHRESHOLD = 1U;
102  TMS570_TCRAM2.RAMTHRESHOLD = 1U;
103
104  /* Enable single bit error generation */
105  TMS570_TCRAM1.RAMINTCTRL = 1U;
106  TMS570_TCRAM2.RAMINTCTRL = 1U;
107
108  /* Enable writes to ECC RAM, enable ECC error response */
109  TMS570_TCRAM1.RAMCTRL = 0x0005010AU;
110  TMS570_TCRAM2.RAMCTRL = 0x0005010AU;
111
112  /* Force a single bit error in both the banks */
113  _coreDisableRamEcc_();
114  tcramA1bitError ^= 1U;
115  tcramB1bitError ^= 1U;
116  _coreEnableRamEcc_();
117
118  /* Read the corrupted data to generate single bit error */
119  ramread = tcramA1bit;
120  ramread = tcramB1bit;
121  (void)ramread;
122
123  /* Check for error status */
124  tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U;
125  tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U;
126  /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
127  /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
128  if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) {
129        /* TCRAM module does not reflect 1-bit error reported by CPU */
130    bsp_selftest_fail_notification(CHECKRAMECC_FAIL1);
131  } else {
132    if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) {
133      /* TCRAM 1-bit error not flagged in ESM */
134      bsp_selftest_fail_notification(CHECKRAMECC_FAIL2);
135    } else {
136      /* Clear single bit error flag in TCRAM module */
137      TMS570_TCRAM1.RAMERRSTATUS = 0x1U;
138      TMS570_TCRAM2.RAMERRSTATUS = 0x1U;
139
140      /* Clear ESM status */
141      tms570_esm_channel_sr_clear(1, 26);
142      tms570_esm_channel_sr_clear(1, 28);
143    }
144  }
145
146#if 0
147  /*
148   * This test sequence requires that data abort exception
149   * handler checks for ECC test write enable in RAMCTR (bit 8)
150   * and if the access abort is intended then it should clear
151   * error status TCRAM status register and checks and clears
152   * ESM group3 uncorrectable TCRAM error channels.
153   *
154   * More modifications in BSP and RTEMS ARM support are
155   * required to make this code work.
156   */
157
158  /* Force a double bit error in both the banks */
159  _coreDisableRamEcc_();
160  tcramA2bitError ^= 3U;
161  tcramB2bitError ^= 3U;
162  _coreEnableRamEcc_();
163
164  /* Read the corrupted data to generate double bit error */
165  ramread = tcramA2bit;
166  ramread = tcramB2bit;
167  /* read from location with 2-bit ECC error this will cause a data abort to be generated */
168  /* See HalCoGen support src/sys/asm/dabort.asm */
169  /* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */
170#endif
171
172  regread = TMS570_TCRAM1.RAMUERRADDR;
173  regread = TMS570_TCRAM2.RAMUERRADDR;
174  (void)regread;
175
176  /* disable writes to ECC RAM */
177  TMS570_TCRAM1.RAMCTRL = 0x0005000AU;
178  TMS570_TCRAM2.RAMCTRL = 0x0005000AU;
179
180  /* Compute correct ECC */
181  tcramA1bit = tcramA1_bk;
182  tcramB1bit = tcramB1_bk;
183  tcramA2bit = tcramA2_bk;
184  tcramB2bit = tcramB2_bk;
185}
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