1 | /** |
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2 | * @file tms570_tcram_tests.c |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief TCRAM selftest function. |
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7 | */ |
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8 | /* |
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9 | * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> |
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10 | * |
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11 | * Czech Technical University in Prague |
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12 | * Zikova 1903/4 |
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13 | * 166 36 Praha 6 |
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14 | * Czech Republic |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | * |
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20 | * Algorithms are based on Ti manuals and Ti HalCoGen generated |
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21 | * code available under following copyright. |
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22 | */ |
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23 | /* |
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24 | * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com |
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25 | * |
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26 | * |
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27 | * Redistribution and use in source and binary forms, with or without |
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28 | * modification, are permitted provided that the following conditions |
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29 | * are met: |
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30 | * |
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31 | * Redistributions of source code must retain the above copyright |
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32 | * notice, this list of conditions and the following disclaimer. |
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33 | * |
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34 | * Redistributions in binary form must reproduce the above copyright |
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35 | * notice, this list of conditions and the following disclaimer in the |
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36 | * documentation and/or other materials provided with the |
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37 | * distribution. |
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38 | * |
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39 | * Neither the name of Texas Instruments Incorporated nor the names of |
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40 | * its contributors may be used to endorse or promote products derived |
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41 | * from this software without specific prior written permission. |
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42 | * |
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43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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54 | * |
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55 | */ |
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56 | |
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57 | #include <stdint.h> |
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58 | #include <bsp/tms570.h> |
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59 | #include "tms570_selftest.h" |
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60 | #include "tms570_hwinit.h" |
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61 | |
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62 | #define tcramA1bitError (*(volatile uint32_t *)(0x08400000U)) |
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63 | #define tcramA2bitError (*(volatile uint32_t *)(0x08400010U)) |
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64 | |
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65 | #define tcramB1bitError (*(volatile uint32_t *)(0x08400008U)) |
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66 | #define tcramB2bitError (*(volatile uint32_t *)(0x08400018U)) |
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67 | |
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68 | #define tcramA1bit (*(volatile uint64_t *)(0x08000000U)) |
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69 | #define tcramA2bit (*(volatile uint64_t *)(0x08000010U)) |
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70 | |
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71 | #define tcramB1bit (*(volatile uint64_t *)(0x08000008U)) |
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72 | #define tcramB2bit (*(volatile uint64_t *)(0x08000018U)) |
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73 | |
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74 | /** |
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75 | * @brief Check TCRAM ECC error detection logic (HCG:checkRAMECC) |
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76 | * |
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77 | * This function checks TCRAM ECC error detection and correction logic. |
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78 | * The function does not return in case of TCRAM error. |
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79 | * It calls bsp_selftest_fail_notification() instead. |
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80 | * |
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81 | */ |
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82 | /* SourceId : SELFTEST_SourceId_034 */ |
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83 | /* DesignId : SELFTEST_DesignId_019 */ |
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84 | /* Requirements : HL_SR408 */ |
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85 | void tms570_check_tcram_ecc( void ) |
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86 | { |
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87 | volatile uint64_t ramread; |
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88 | volatile uint32_t regread; |
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89 | uint32_t tcram1ErrStat, tcram2ErrStat = 0U; |
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90 | |
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91 | uint64_t tcramA1_bk = tcramA1bit; |
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92 | uint64_t tcramB1_bk = tcramB1bit; |
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93 | uint64_t tcramA2_bk = tcramA2bit; |
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94 | uint64_t tcramB2_bk = tcramB2bit; |
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95 | |
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96 | /* Clear RAMOCUUR before setting RAMTHRESHOLD register */ |
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97 | TMS570_TCRAM1.RAMOCCUR = 0U; |
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98 | TMS570_TCRAM2.RAMOCCUR = 0U; |
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99 | |
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100 | /* Set Single-bit Error Threshold Count as 1 */ |
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101 | TMS570_TCRAM1.RAMTHRESHOLD = 1U; |
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102 | TMS570_TCRAM2.RAMTHRESHOLD = 1U; |
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103 | |
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104 | /* Enable single bit error generation */ |
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105 | TMS570_TCRAM1.RAMINTCTRL = 1U; |
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106 | TMS570_TCRAM2.RAMINTCTRL = 1U; |
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107 | |
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108 | /* Enable writes to ECC RAM, enable ECC error response */ |
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109 | TMS570_TCRAM1.RAMCTRL = 0x0005010AU; |
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110 | TMS570_TCRAM2.RAMCTRL = 0x0005010AU; |
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111 | |
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112 | /* Force a single bit error in both the banks */ |
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113 | _coreDisableRamEcc_(); |
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114 | tcramA1bitError ^= 1U; |
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115 | tcramB1bitError ^= 1U; |
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116 | _coreEnableRamEcc_(); |
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117 | |
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118 | /* Read the corrupted data to generate single bit error */ |
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119 | ramread = tcramA1bit; |
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120 | ramread = tcramB1bit; |
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121 | (void)ramread; |
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122 | |
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123 | /* Check for error status */ |
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124 | tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U; |
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125 | tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U; |
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126 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ |
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127 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ |
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128 | if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) { |
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129 | /* TCRAM module does not reflect 1-bit error reported by CPU */ |
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130 | bsp_selftest_fail_notification(CHECKRAMECC_FAIL1); |
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131 | } else { |
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132 | if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) { |
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133 | /* TCRAM 1-bit error not flagged in ESM */ |
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134 | bsp_selftest_fail_notification(CHECKRAMECC_FAIL2); |
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135 | } else { |
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136 | /* Clear single bit error flag in TCRAM module */ |
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137 | TMS570_TCRAM1.RAMERRSTATUS = 0x1U; |
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138 | TMS570_TCRAM2.RAMERRSTATUS = 0x1U; |
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139 | |
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140 | /* Clear ESM status */ |
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141 | tms570_esm_channel_sr_clear(1, 26); |
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142 | tms570_esm_channel_sr_clear(1, 28); |
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143 | } |
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144 | } |
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145 | |
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146 | #if 0 |
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147 | /* |
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148 | * This test sequence requires that data abort exception |
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149 | * handler checks for ECC test write enable in RAMCTR (bit 8) |
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150 | * and if the access abort is intended then it should clear |
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151 | * error status TCRAM status register and checks and clears |
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152 | * ESM group3 uncorrectable TCRAM error channels. |
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153 | * |
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154 | * More modifications in BSP and RTEMS ARM support are |
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155 | * required to make this code work. |
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156 | */ |
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157 | |
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158 | /* Force a double bit error in both the banks */ |
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159 | _coreDisableRamEcc_(); |
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160 | tcramA2bitError ^= 3U; |
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161 | tcramB2bitError ^= 3U; |
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162 | _coreEnableRamEcc_(); |
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163 | |
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164 | /* Read the corrupted data to generate double bit error */ |
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165 | ramread = tcramA2bit; |
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166 | ramread = tcramB2bit; |
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167 | /* read from location with 2-bit ECC error this will cause a data abort to be generated */ |
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168 | /* See HalCoGen support src/sys/asm/dabort.asm */ |
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169 | /* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */ |
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170 | #endif |
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171 | |
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172 | regread = TMS570_TCRAM1.RAMUERRADDR; |
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173 | regread = TMS570_TCRAM2.RAMUERRADDR; |
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174 | (void)regread; |
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175 | |
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176 | /* disable writes to ECC RAM */ |
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177 | TMS570_TCRAM1.RAMCTRL = 0x0005000AU; |
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178 | TMS570_TCRAM2.RAMCTRL = 0x0005000AU; |
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179 | |
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180 | /* Compute correct ECC */ |
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181 | tcramA1bit = tcramA1_bk; |
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182 | tcramB1bit = tcramB1_bk; |
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183 | tcramA2bit = tcramA2_bk; |
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184 | tcramB2bit = tcramB2_bk; |
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185 | } |
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