source: rtems/c/src/lib/libbsp/arm/tms570/hwinit/tms570_sys_core.S @ b2ed712

5
Last change on this file since b2ed712 was 29430a3, checked in by Pavel Pisa <pisa@…>, on 09/22/16 at 07:50:59

arm/tms570: include hardware initialization and selftest based on Ti HalCoGen? generated files.

The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in

rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c

file.

The list tms570_selftest_par_list in the file

rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c

specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.
  • Property mode set to 100644
File size: 16.7 KB
Line 
1/*--------------------------------------------------------------------------
2 tms570_sys_core.S
3
4 Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
5
6
7  Redistribution and use in source and binary forms, with or without
8  modification, are permitted provided that the following conditions
9  are met:
10
11    Redistributions of source code must retain the above copyright
12    notice, this list of conditions and the following disclaimer.
13
14    Redistributions in binary form must reproduce the above copyright
15    notice, this list of conditions and the following disclaimer in the
16    documentation and/or other materials provided with the
17    distribution.
18
19    Neither the name of Texas Instruments Incorporated nor the names of
20    its contributors may be used to endorse or promote products derived
21    from this software without specific prior written permission.
22
23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
35-------------------------------------------------------------------------*/
36
37    .section .text
38    .syntax unified
39    .cpu cortex-r4
40    .arm
41
42/*-------------------------------------------------------------------------------*/
43@ Initialize CPU Registers
44@ SourceId : CORE_SourceId_001
45@ DesignId : CORE_DesignId_001
46@ Requirements: HL_SR477, HL_SR476, HL_SR492
47
48    .weak _coreInitRegisters_
49    .type _coreInitRegisters_, %function
50
51_coreInitRegisters_:
52
53    @ After reset, the CPU is in the Supervisor mode (M = 10011)
54        mov r0, lr
55        mov r1, #0x0000
56        mov r2, #0x0000
57        mov r3, #0x0000
58        mov r4, #0x0000
59        mov r5, #0x0000
60        mov r6, #0x0000
61        mov r7, #0x0000
62        mov r8, #0x0000
63        mov r9, #0x0000
64        mov r10, #0x0000
65        mov r11, #0x0000
66        mov r12, #0x0000
67        mov r13, #0x0000
68        mrs r1, cpsr
69        msr spsr_cxsf, r1
70        @ Switch to FIQ mode (M = 10001)
71        cps #17
72        mov lr, r0
73        mov r8, #0x0000
74        mov r9, #0x0000
75        mov r10, #0x0000
76        mov r11, #0x0000
77        mov r12, #0x0000
78        mrs r1, cpsr
79        msr spsr_cxsf, r1
80        @ Switch to IRQ mode (M = 10010)
81        cps #18
82        mov lr, r0
83        mrs r1,cpsr
84        msr spsr_cxsf, r1             @ Switch to Abort mode (M = 10111)
85        cps #23
86        mov lr, r0
87        mrs r1,cpsr
88        msr spsr_cxsf, r1             @ Switch to Undefined Instruction Mode (M = 11011)
89        cps #27
90        mov lr, r0
91        mrs r1,cpsr
92        msr spsr_cxsf, r1             @ Switch to System Mode ( Shares User Mode registers ) (M = 11111)
93        cps #31
94        mov lr, r0
95        mrs r1,cpsr
96        msr spsr_cxsf, r1
97
98        mrc   p15,     #0x00,      r2,       c1, c0, #0x02
99        orr   r2,      r2,         #0xF00000
100        mcr   p15,     #0x00,      r2,       c1, c0, #0x02
101        mov   r2,      #0x40000000
102        fmxr  fpexc,   r2
103
104        fmdrr d0, r1, r1
105        fmdrr d1, r1, r1
106        fmdrr d2, r1, r1
107        fmdrr d3, r1, r1
108        fmdrr d4, r1, r1
109        fmdrr d5, r1, r1
110        fmdrr d6, r1, r1
111        fmdrr d7, r1, r1
112        fmdrr d8, r1, r1
113        fmdrr d9, r1, r1
114        fmdrr d10, r1, r1
115        fmdrr d11, r1, r1
116        fmdrr d12, r1, r1
117        fmdrr d13, r1, r1
118        fmdrr d14, r1, r1
119        fmdrr d15, r1, r1
120
121    bl next1
122next1:
123    bl next2
124next2:
125    bl next3
126next3:
127    bl next4
128next4:
129    bx r0
130
131/*-------------------------------------------------------------------------------*/
132@ Take CPU to IDLE state
133@ SourceId : CORE_SourceId_004
134@ DesignId : CORE_DesignId_004
135@ Requirements: HL_SR493
136
137    .weak _gotoCPUIdle_
138    .type _gotoCPUIdle_, %function
139
140_gotoCPUIdle_:
141
142        WFI
143        nop
144        nop
145        nop
146        nop
147        bx    lr
148
149/*-------------------------------------------------------------------------------*/
150@ Enable VFP Unit
151@ SourceId : CORE_SourceId_005
152@ DesignId : CORE_DesignId_006
153@ Requirements: HL_SR492, HL_SR476
154
155    .weak _coreEnableVfp_
156    .type _coreEnableVfp_, %function
157
158_coreEnableVfp_:
159
160        stmfd sp!, {r0}
161        mrc   p15,     #0x00,      r0,       c1, c0, #0x02
162        orr   r0,      r0,         #0xF00000
163        mcr   p15,     #0x00,      r0,       c1, c0, #0x02
164        mov   r0,      #0x40000000
165        fmxr  fpexc,   r0
166        ldmfd sp!, {r0}
167        bx    lr
168
169/*-------------------------------------------------------------------------------*/
170@ Enable Event Bus Export
171@ SourceId : CORE_SourceId_006
172@ DesignId : CORE_DesignId_007
173@ Requirements: HL_SR479
174
175    .weak _coreEnableEventBusExport_
176    .type _coreEnableEventBusExport_, %function
177
178_coreEnableEventBusExport_:
179
180        stmfd sp!, {r0}
181        mrc   p15, #0x00, r0,         c9, c12, #0x00
182        orr   r0,  r0,    #0x10
183        mcr   p15, #0x00, r0,         c9, c12, #0x00
184        ldmfd sp!, {r0}
185        bx    lr
186
187/*-------------------------------------------------------------------------------*/
188@ Disable Event Bus Export
189@ SourceId : CORE_SourceId_007
190@ DesignId : CORE_DesignId_008
191@ Requirements: HL_SR481
192
193    .weak _coreDisableEventBusExport_
194    .type _coreDisableEventBusExport_, %function
195
196_coreDisableEventBusExport_:
197
198        stmfd sp!, {r0}
199        mrc   p15, #0x00, r0,         c9, c12, #0x00
200        bic   r0,  r0,    #0x10
201        mcr   p15, #0x00, r0,         c9, c12, #0x00
202        ldmfd sp!, {r0}
203        bx    lr
204
205/*-------------------------------------------------------------------------------*/
206@ Enable RAM ECC Support
207@ SourceId : CORE_SourceId_008
208@ DesignId : CORE_DesignId_009
209@ Requirements: HL_SR480
210
211    .weak _coreEnableRamEcc_
212    .type _coreEnableRamEcc_, %function
213
214_coreEnableRamEcc_:
215
216        stmfd sp!, {r0}
217        mrc   p15, #0x00, r0,         c1, c0,  #0x01
218        orr   r0,  r0,    #0x0C000000
219        mcr   p15, #0x00, r0,         c1, c0,  #0x01
220        ldmfd sp!, {r0}
221        bx    lr
222
223/*-------------------------------------------------------------------------------*/
224@ Disable RAM ECC Support
225@ SourceId : CORE_SourceId_009
226@ DesignId : CORE_DesignId_010
227@ Requirements: HL_SR482
228
229    .weak _coreDisableRamEcc_
230    .type _coreDisableRamEcc_, %function
231
232_coreDisableRamEcc_:
233
234        stmfd sp!, {r0}
235        mrc   p15, #0x00, r0,         c1, c0,  #0x01
236        bic   r0,  r0,    #0x0C000000
237        mcr   p15, #0x00, r0,         c1, c0,  #0x01
238        ldmfd sp!, {r0}
239        bx    lr
240
241/*-------------------------------------------------------------------------------*/
242@ Enable Flash ECC Support
243@ SourceId : CORE_SourceId_010
244@ DesignId : CORE_DesignId_011
245@ Requirements: HL_SR480
246
247    .weak _coreEnableFlashEcc_
248    .type _coreEnableFlashEcc_, %function
249
250_coreEnableFlashEcc_:
251
252        stmfd sp!, {r0}
253        mrc   p15, #0x00, r0,         c1, c0,  #0x01
254        orr   r0,  r0,    #0x02000000
255        dmb
256        mcr   p15, #0x00, r0,         c1, c0,  #0x01
257        ldmfd sp!, {r0}
258        bx    lr
259
260/*-------------------------------------------------------------------------------*/
261@ Disable Flash ECC Support
262@ SourceId : CORE_SourceId_011
263@ DesignId : CORE_DesignId_012
264@ Requirements: HL_SR482
265
266    .weak _coreDisableFlashEcc_
267    .type _coreDisableFlashEcc_, %function
268
269_coreDisableFlashEcc_:
270
271        stmfd sp!, {r0}
272        mrc   p15, #0x00, r0,         c1, c0,  #0x01
273        bic   r0,  r0,    #0x02000000
274        mcr   p15, #0x00, r0,         c1, c0,  #0x01
275        ldmfd sp!, {r0}
276        bx    lr
277
278/*-------------------------------------------------------------------------------*/
279@ Enable Offset via Vic controller
280@ SourceId : CORE_SourceId_012
281@ DesignId : CORE_DesignId_005
282@ Requirements: HL_SR483
283
284    .weak _coreEnableIrqVicOffset_
285    .type _coreEnableIrqVicOffset_, %function
286
287_coreEnableIrqVicOffset_:
288
289        stmfd sp!, {r0}
290        mrc   p15, #0, r0,         c1, c0,  #0
291        orr   r0,  r0,    #0x01000000
292        mcr   p15, #0, r0,         c1, c0,  #0
293        ldmfd sp!, {r0}
294        bx    lr
295
296/*-------------------------------------------------------------------------------*/
297@ Get data fault status register
298@ SourceId : CORE_SourceId_013
299@ DesignId : CORE_DesignId_013
300@ Requirements: HL_SR495
301
302    .weak _coreGetDataFault_
303    .type _coreGetDataFault_, %function
304
305_coreGetDataFault_:
306
307        mrc   p15, #0, r0, c5, c0,  #0
308        bx    lr
309
310/*-------------------------------------------------------------------------------*/
311@ Clear data fault status register
312@ SourceId : CORE_SourceId_014
313@ DesignId : CORE_DesignId_014
314@ Requirements: HL_SR495
315
316    .weak _coreClearDataFault_
317    .type _coreClearDataFault_, %function
318
319_coreClearDataFault_:
320
321        stmfd sp!, {r0}
322        mov   r0,  #0
323        mcr   p15, #0, r0, c5, c0,  #0
324        ldmfd sp!, {r0}
325        bx    lr
326
327/*-------------------------------------------------------------------------------*/
328@ Get instruction fault status register
329@ SourceId : CORE_SourceId_015
330@ DesignId : CORE_DesignId_015
331@ Requirements: HL_SR495
332
333    .weak _coreGetInstructionFault_
334    .type _coreGetInstructionFault_, %function
335
336_coreGetInstructionFault_:
337
338        mrc   p15, #0, r0, c5, c0, #1
339        bx    lr
340
341/*-------------------------------------------------------------------------------*/
342@ Clear instruction fault status register
343@ SourceId : CORE_SourceId_016
344@ DesignId : CORE_DesignId_016
345@ Requirements: HL_SR495
346
347    .weak _coreClearInstructionFault_
348    .type _coreClearInstructionFault_, %function
349
350_coreClearInstructionFault_:
351
352        stmfd sp!, {r0}
353        mov   r0,  #0
354        mcr   p15, #0, r0, c5, c0, #1
355        ldmfd sp!, {r0}
356        bx    lr
357
358/*-------------------------------------------------------------------------------*/
359@ Get data fault address register
360@ SourceId : CORE_SourceId_017
361@ DesignId : CORE_DesignId_017
362@ Requirements: HL_SR495
363
364    .weak _coreGetDataFaultAddress_
365    .type _coreGetDataFaultAddress_, %function
366
367_coreGetDataFaultAddress_:
368
369        mrc   p15, #0, r0, c6, c0,  #0
370        bx    lr
371
372/*-------------------------------------------------------------------------------*/
373@ Clear data fault address register
374@ SourceId : CORE_SourceId_018
375@ DesignId : CORE_DesignId_018
376@ Requirements: HL_SR495
377
378    .weak _coreClearDataFaultAddress_
379    .type _coreClearDataFaultAddress_, %function
380
381_coreClearDataFaultAddress_:
382
383        stmfd sp!, {r0}
384        mov   r0,  #0
385        mcr   p15, #0, r0, c6, c0,  #0
386        ldmfd sp!, {r0}
387        bx    lr
388
389/*-------------------------------------------------------------------------------*/
390@ Get instruction fault address register
391@ SourceId : CORE_SourceId_019
392@ DesignId : CORE_DesignId_019
393@ Requirements: HL_SR495
394
395    .weak _coreGetInstructionFaultAddress_
396    .type _coreGetInstructionFaultAddress_, %function
397
398_coreGetInstructionFaultAddress_:
399
400        mrc   p15, #0, r0, c6, c0, #2
401        bx    lr
402
403/*-------------------------------------------------------------------------------*/
404@ Clear instruction fault address register
405@ SourceId : CORE_SourceId_020
406@ DesignId : CORE_DesignId_020
407@ Requirements: HL_SR495
408
409    .weak _coreClearInstructionFaultAddress_
410    .type _coreClearInstructionFaultAddress_, %function
411
412_coreClearInstructionFaultAddress_:
413
414        stmfd sp!, {r0}
415        mov   r0,  #0
416        mcr   p15, #0, r0, c6, c0, #2
417        ldmfd sp!, {r0}
418        bx    lr
419
420/*-------------------------------------------------------------------------------*/
421@ Get auxiliary data fault status register
422@ SourceId : CORE_SourceId_021
423@ DesignId : CORE_DesignId_021
424@ Requirements: HL_SR496
425
426    .weak _coreGetAuxiliaryDataFault_
427    .type _coreGetAuxiliaryDataFault_, %function
428
429_coreGetAuxiliaryDataFault_:
430
431        mrc   p15, #0, r0, c5, c1, #0
432        bx    lr
433
434/*-------------------------------------------------------------------------------*/
435@ Clear auxiliary data fault status register
436@ SourceId : CORE_SourceId_022
437@ DesignId : CORE_DesignId_022
438@ Requirements: HL_SR496
439
440    .weak _coreClearAuxiliaryDataFault_
441    .type _coreClearAuxiliaryDataFault_, %function
442
443_coreClearAuxiliaryDataFault_:
444
445        stmfd sp!, {r0}
446        mov   r0,  #0
447        mcr   p15, #0, r0, c5, c1, #0
448        ldmfd sp!, {r0}
449        bx    lr
450
451/*-------------------------------------------------------------------------------*/
452@ Get auxiliary instruction fault status register
453@ SourceId : CORE_SourceId_023
454@ DesignId : CORE_DesignId_023
455@ Requirements: HL_SR496
456
457    .weak _coreGetAuxiliaryInstructionFault_
458    .type _coreGetAuxiliaryInstructionFault_, %function
459
460_coreGetAuxiliaryInstructionFault_:
461
462        mrc   p15, #0, r0, c5, c1, #1
463        bx    lr
464
465/*-------------------------------------------------------------------------------*/
466@ Clear auxiliary instruction fault status register
467@ SourceId : CORE_SourceId_024
468@ DesignId : CORE_DesignId_024
469@ Requirements: HL_SR496
470
471    .weak _coreClearAuxiliaryInstructionFault_
472    .type _coreClearAuxiliaryInstructionFault_, %function
473
474_coreClearAuxiliaryInstructionFault_:
475
476        stmfd sp!, {r0}
477        mov   r0,  #0
478        mrc   p15, #0, r0, c5, c1, #1
479        ldmfd sp!, {r0}
480        bx    lr
481
482/*-------------------------------------------------------------------------------*/
483@ Clear ESM CCM errorss
484
485    .weak _esmCcmErrorsClear_
486    .type _esmCcmErrorsClear_, %function
487
488_esmCcmErrorsClear_:
489
490        stmfd sp!, {r0-r2}
491        ldr   r0, ESMSR1_REG      @ load the ESMSR1 status register address
492        ldr   r2, ESMSR1_ERR_CLR
493        str   r2, [r0]            @ clear the ESMSR1 register
494
495        ldr   r0, ESMSR2_REG      @ load the ESMSR2 status register address
496        ldr   r2, ESMSR2_ERR_CLR
497        str   r2, [r0]            @ clear the ESMSR2 register
498
499        ldr   r0, ESMSSR2_REG     @ load the ESMSSR2 status register address
500        ldr   r2, ESMSSR2_ERR_CLR
501        str   r2, [r0]            @ clear the ESMSSR2 register
502
503        ldr   r0, ESMKEY_REG      @ load the ESMKEY register address
504        mov   r2, #0x5            @ load R2 with 0x5
505        str   r2, [r0]            @ clear the ESMKEY register
506
507        ldr   r0, VIM_INTREQ      @ load the INTREQ register address
508        ldr   r2, VIM_INT_CLR
509        str   r2, [r0]            @ clear the INTREQ register
510        ldr   r0, CCMR4_STAT_REG  @ load the CCMR4 status register address
511        ldr   r2, CCMR4_ERR_CLR
512        str   r2, [r0]            @ clear the CCMR4 status register
513        ldmfd sp!, {r0-r2}
514        bx    lr
515
516ESMSR1_REG:      .word 0xFFFFF518
517ESMSR2_REG:      .word 0xFFFFF51C
518ESMSR3_REG:      .word 0xFFFFF520
519ESMKEY_REG:      .word 0xFFFFF538
520ESMSSR2_REG:     .word 0xFFFFF53C
521CCMR4_STAT_REG:  .word 0xFFFFF600
522ERR_CLR_WRD:     .word 0xFFFFFFFF
523CCMR4_ERR_CLR:   .word 0x00010000
524ESMSR1_ERR_CLR:  .word 0x80000000
525ESMSR2_ERR_CLR:  .word 0x00000004
526ESMSSR2_ERR_CLR: .word 0x00000004
527VIM_INT_CLR:     .word 0x00000001
528VIM_INTREQ:      .word 0xFFFFFE20
529
530
531#if 1/*-------------------------------------------------------------------------------*/
532@ Work Around for Errata CORTEX-R4#57:
533@
534@ Errata Description:
535@            Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
536@ Workaround:
537@            Disable out-of-order single-precision floating point
538@            multiply-accumulate instruction completion
539
540    .weak _errata_CORTEXR4_57_
541    .type _errata_CORTEXR4_57_, %function
542
543_errata_CORTEXR4_57_:
544
545        push {r0}
546        mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
547        orr r0, r0, #0x10000         @ Set BIT 16 (Set DOOFMACS)
548        mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
549        pop {r0}
550        bx lr
551#endif
552
553/*-------------------------------------------------------------------------------*/
554@ Work Around for Errata CORTEX-R4#66:
555@
556@ Errata Description:
557@            Register Corruption During A Load-Multiple Instruction At
558@            an Exception Vector
559@ Workaround:
560@            Disable out-of-order completion for divide instructions in
561@            Auxiliary Control register
562
563    .weak _errata_CORTEXR4_66_
564    .type _errata_CORTEXR4_66_, %function
565
566_errata_CORTEXR4_66_:
567
568        push {r0}
569        mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
570        orr r0, r0, #0x80           @ Set BIT 7 (Disable out-of-order completion
571                                    @ for divide instructions.)
572        mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
573        pop {r0}
574        bx lr
575/*-------------------------------------------------------------------------------*/
Note: See TracBrowser for help on using the repository browser.