1 | /** |
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2 | * @file tms570_selftest_parity.c |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief Check of module parity based protection logic to work. |
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7 | */ |
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8 | /* |
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9 | * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> |
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10 | * |
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11 | * Czech Technical University in Prague |
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12 | * Zikova 1903/4 |
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13 | * 166 36 Praha 6 |
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14 | * Czech Republic |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <stdint.h> |
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22 | #include <stddef.h> |
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23 | #include <bsp/tms570.h> |
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24 | #include <rtems.h> |
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25 | #include "tms570_selftest.h" |
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26 | #include "tms570_selftest_parity.h" |
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27 | |
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28 | /* HCG:het1ParityCheck */ |
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29 | const tms570_selftest_par_desc_t |
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30 | tms570_selftest_par_het1_desc = { |
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31 | .esm_prim_grp = 1, |
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32 | .esm_prim_chan = 7, |
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33 | .esm_sec_grp = 0, |
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34 | .esm_sec_chan = 0, |
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35 | .fail_code = HET1PARITYCHECK_FAIL1, |
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36 | .ram_loc = &NHET1RAMLOC, |
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37 | .par_loc = &NHET1RAMPARLOC, |
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38 | .par_xor = 0x00000001, |
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39 | .par_cr_reg = &TMS570_NHET1.PCR, |
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40 | .par_cr_test = TMS570_NHET_PCR_TEST, |
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41 | .par_st_reg = NULL, |
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42 | .par_st_clear = 0, |
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43 | .partest_fnc = tms570_selftest_par_check_std, |
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44 | .fnc_data = NULL |
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45 | }; |
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46 | |
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47 | /* HCG:htu1ParityCheck */ |
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48 | const tms570_selftest_par_desc_t |
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49 | tms570_selftest_par_htu1_desc = { |
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50 | .esm_prim_grp = 1, |
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51 | .esm_prim_chan = 8, |
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52 | .esm_sec_grp = 0, |
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53 | .esm_sec_chan = 0, |
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54 | .fail_code = HTU1PARITYCHECK_FAIL1, |
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55 | .ram_loc = &HTU1RAMLOC, |
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56 | .par_loc = &HTU1PARLOC, |
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57 | .par_xor = 0x00000001, |
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58 | .par_cr_reg = &TMS570_HTU1.PCR, |
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59 | .par_cr_test = TMS570_HTU_PCR_TEST, |
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60 | .par_st_reg = &TMS570_HTU1.PAR, |
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61 | .par_st_clear = TMS570_HTU_PAR_PEFT, |
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62 | .partest_fnc = tms570_selftest_par_check_std, |
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63 | .fnc_data = NULL |
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64 | }; |
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65 | |
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66 | /* HCG:het2ParityCheck */ |
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67 | const tms570_selftest_par_desc_t |
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68 | tms570_selftest_par_het2_desc = { |
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69 | .esm_prim_grp = 1, |
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70 | .esm_prim_chan = 7, |
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71 | .esm_sec_grp = 1, |
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72 | .esm_sec_chan = 34, |
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73 | .fail_code = HET2PARITYCHECK_FAIL1, |
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74 | .ram_loc = &NHET2RAMLOC, |
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75 | .par_loc = &NHET2RAMPARLOC, |
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76 | .par_xor = 0x00000001, |
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77 | .par_cr_reg = &TMS570_NHET2.PCR, |
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78 | .par_cr_test = TMS570_NHET_PCR_TEST, |
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79 | .par_st_reg = NULL, |
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80 | .par_st_clear = 0, |
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81 | .partest_fnc = tms570_selftest_par_check_std, |
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82 | .fnc_data = NULL |
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83 | }; |
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84 | |
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85 | /* HCG:htu2ParityCheck */ |
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86 | const tms570_selftest_par_desc_t |
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87 | tms570_selftest_par_htu2_desc = { |
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88 | .esm_prim_grp = 1, |
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89 | .esm_prim_chan = 8, |
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90 | .esm_sec_grp = 0, |
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91 | .esm_sec_chan = 0, |
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92 | .fail_code = HTU2PARITYCHECK_FAIL1, |
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93 | .ram_loc = &HTU2RAMLOC, |
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94 | .par_loc = &HTU2PARLOC, |
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95 | .par_xor = 0x00000001, |
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96 | .par_cr_reg = &TMS570_HTU2.PCR, |
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97 | .par_cr_test = TMS570_HTU_PCR_TEST, |
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98 | .par_st_reg = &TMS570_HTU2.PAR, |
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99 | .par_st_clear = TMS570_HTU_PAR_PEFT, |
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100 | .partest_fnc = tms570_selftest_par_check_std, |
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101 | .fnc_data = NULL |
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102 | }; |
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103 | |
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104 | /* HCG:adc1ParityCheck */ |
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105 | const tms570_selftest_par_desc_t |
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106 | tms570_selftest_par_adc1_desc = { |
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107 | .esm_prim_grp = 1, |
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108 | .esm_prim_chan = 19, |
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109 | .esm_sec_grp = 0, |
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110 | .esm_sec_chan = 0, |
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111 | .fail_code = ADC1PARITYCHECK_FAIL1, |
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112 | .ram_loc = &adcRAM1, |
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113 | .par_loc = &adcPARRAM1, |
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114 | .par_xor = 0xffffffff, |
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115 | .par_cr_reg = &TMS570_ADC1.PARCR, |
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116 | .par_cr_test = TMS570_ADC_PARCR_TEST, |
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117 | .par_st_reg = NULL, |
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118 | .par_st_clear = 0, |
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119 | .partest_fnc = tms570_selftest_par_check_std, |
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120 | .fnc_data = NULL |
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121 | }; |
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122 | |
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123 | /* HCG:adc2ParityCheck */ |
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124 | const tms570_selftest_par_desc_t |
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125 | tms570_selftest_par_adc2_desc = { |
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126 | .esm_prim_grp = 1, |
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127 | .esm_prim_chan = 1, |
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128 | .esm_sec_grp = 0, |
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129 | .esm_sec_chan = 0, |
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130 | .fail_code = ADC2PARITYCHECK_FAIL1, |
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131 | .ram_loc = &adcRAM2, |
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132 | .par_loc = &adcPARRAM2, |
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133 | .par_xor = 0xffffffff, |
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134 | .par_cr_reg = &TMS570_ADC2.PARCR, |
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135 | .par_cr_test = TMS570_ADC_PARCR_TEST, |
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136 | .par_st_reg = NULL, |
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137 | .par_st_clear = 0, |
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138 | .partest_fnc = tms570_selftest_par_check_std, |
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139 | .fnc_data = NULL |
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140 | }; |
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141 | |
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142 | /* HCG:can1ParityCheck */ |
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143 | const tms570_selftest_par_desc_t |
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144 | tms570_selftest_par_can1_desc = { |
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145 | .esm_prim_grp = 1, |
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146 | .esm_prim_chan = 21, |
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147 | .esm_sec_grp = 0, |
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148 | .esm_sec_chan = 0, |
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149 | .fail_code = CAN1PARITYCHECK_FAIL1, |
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150 | .ram_loc = &canRAM1, |
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151 | .par_loc = &canPARRAM1, |
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152 | .par_xor = 0x00001000, |
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153 | .par_cr_reg = NULL, |
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154 | .par_cr_test = 0, |
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155 | .par_st_reg = NULL, |
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156 | .par_st_clear = 0, |
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157 | .partest_fnc = tms570_selftest_par_check_can, |
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158 | .fnc_data = &TMS570_DCAN1 |
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159 | }; |
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160 | |
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161 | /* HCG:can2ParityCheck */ |
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162 | const tms570_selftest_par_desc_t |
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163 | tms570_selftest_par_can2_desc = { |
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164 | .esm_prim_grp = 1, |
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165 | .esm_prim_chan = 23, |
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166 | .esm_sec_grp = 0, |
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167 | .esm_sec_chan = 0, |
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168 | .fail_code = CAN2PARITYCHECK_FAIL1, |
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169 | .ram_loc = &canRAM2, |
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170 | .par_loc = &canPARRAM2, |
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171 | .par_xor = 0x00001000, |
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172 | .par_cr_reg = NULL, |
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173 | .par_cr_test = 0, |
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174 | .par_st_reg = NULL, |
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175 | .par_st_clear = 0, |
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176 | .partest_fnc = tms570_selftest_par_check_can, |
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177 | .fnc_data = &TMS570_DCAN2 |
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178 | }; |
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179 | |
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180 | /* HCG:can3ParityCheck */ |
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181 | const tms570_selftest_par_desc_t |
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182 | tms570_selftest_par_can3_desc = { |
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183 | .esm_prim_grp = 1, |
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184 | .esm_prim_chan = 22, |
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185 | .esm_sec_grp = 0, |
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186 | .esm_sec_chan = 0, |
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187 | .fail_code = CAN3PARITYCHECK_FAIL1, |
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188 | .ram_loc = &canRAM3, |
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189 | .par_loc = &canPARRAM3, |
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190 | .par_xor = 0x00001000, |
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191 | .par_cr_reg = NULL, |
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192 | .par_cr_test = 0, |
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193 | .par_st_reg = NULL, |
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194 | .par_st_clear = 0, |
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195 | .partest_fnc = tms570_selftest_par_check_can, |
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196 | .fnc_data = &TMS570_DCAN3 |
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197 | }; |
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198 | |
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199 | /* HCG:vimParityCheck */ |
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200 | const tms570_selftest_par_desc_t |
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201 | tms570_selftest_par_vim_desc = { |
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202 | .esm_prim_grp = 1, |
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203 | .esm_prim_chan = 15, |
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204 | .esm_sec_grp = 0, |
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205 | .esm_sec_chan = 0, |
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206 | .fail_code = VIMPARITYCHECK_FAIL1, |
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207 | .ram_loc = &VIMRAMLOC, |
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208 | .par_loc = &VIMRAMPARLOC, |
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209 | .par_xor = 0x00000001, |
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210 | .par_cr_reg = &TMS570_VIM.PARCTL, |
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211 | .par_cr_test = TMS570_VIM_PARCTL_TEST, |
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212 | .par_st_reg = &TMS570_VIM.PARFLG, |
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213 | .par_st_clear = TMS570_VIM_PARFLG_PARFLG, |
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214 | .partest_fnc = tms570_selftest_par_check_std, |
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215 | .fnc_data = NULL |
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216 | }; |
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217 | |
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218 | /* HCG:dmaParityCheck */ |
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219 | const tms570_selftest_par_desc_t |
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220 | tms570_selftest_par_dma_desc = { |
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221 | .esm_prim_grp = 1, |
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222 | .esm_prim_chan = 3, |
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223 | .esm_sec_grp = 0, |
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224 | .esm_sec_chan = 0, |
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225 | .fail_code = DMAPARITYCHECK_FAIL1, |
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226 | .ram_loc = &DMARAMLOC, |
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227 | .par_loc = &DMARAMPARLOC, |
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228 | .par_xor = 0x00000001, |
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229 | .par_cr_reg = &TMS570_DMA.DMAPCR, |
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230 | .par_cr_test = TMS570_DMA_DMAPCR_TEST, |
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231 | .par_st_reg = &TMS570_DMA.DMAPAR, |
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232 | .par_st_clear = TMS570_DMA_DMAPAR_EDFLAG, |
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233 | .partest_fnc = tms570_selftest_par_check_std, |
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234 | .fnc_data = NULL |
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235 | }; |
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236 | |
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237 | /* HCG:mibspi1ParityCheck */ |
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238 | const tms570_selftest_par_desc_t |
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239 | tms570_selftest_par_spi1_desc = { |
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240 | .esm_prim_grp = 1, |
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241 | .esm_prim_chan = 17, |
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242 | .esm_sec_grp = 0, |
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243 | .esm_sec_chan = 0, |
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244 | .fail_code = MIBSPI1PARITYCHECK_FAIL1, |
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245 | .ram_loc = &MIBSPI1RAMLOC, |
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246 | .par_loc = &mibspiPARRAM1, |
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247 | .par_xor = 0x00000001, |
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248 | .par_cr_reg = NULL, |
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249 | .par_cr_test = 0, |
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250 | .par_st_reg = NULL, |
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251 | .par_st_clear = 0, |
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252 | .partest_fnc = tms570_selftest_par_check_mibspi, |
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253 | .fnc_data = &TMS570_SPI1 |
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254 | }; |
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255 | |
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256 | /* HCG:mibspi3ParityCheck */ |
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257 | const tms570_selftest_par_desc_t |
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258 | tms570_selftest_par_spi3_desc = { |
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259 | .esm_prim_grp = 1, |
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260 | .esm_prim_chan = 18, |
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261 | .esm_sec_grp = 0, |
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262 | .esm_sec_chan = 0, |
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263 | .fail_code = MIBSPI3PARITYCHECK_FAIL1, |
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264 | .ram_loc = &MIBSPI3RAMLOC, |
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265 | .par_loc = &mibspiPARRAM3, |
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266 | .par_xor = 0x00000001, |
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267 | .par_cr_reg = NULL, |
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268 | .par_cr_test = 0, |
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269 | .par_st_reg = NULL, |
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270 | .par_st_clear = 0, |
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271 | .partest_fnc = tms570_selftest_par_check_mibspi, |
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272 | .fnc_data = &TMS570_SPI3 |
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273 | }; |
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274 | |
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275 | /* HCG:mibspi5ParityCheck */ |
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276 | const tms570_selftest_par_desc_t |
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277 | tms570_selftest_par_spi5_desc = { |
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278 | .esm_prim_grp = 1, |
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279 | .esm_prim_chan = 24, |
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280 | .esm_sec_grp = 0, |
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281 | .esm_sec_chan = 0, |
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282 | .fail_code = MIBSPI5PARITYCHECK_FAIL1, |
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283 | .ram_loc = &MIBSPI5RAMLOC, |
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284 | .par_loc = &mibspiPARRAM5, |
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285 | .par_xor = 0x00000001, |
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286 | .par_cr_reg = NULL, |
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287 | .par_cr_test = 0, |
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288 | .par_st_reg = NULL, |
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289 | .par_st_clear = 0, |
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290 | .partest_fnc = tms570_selftest_par_check_mibspi, |
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291 | .fnc_data = &TMS570_SPI5 |
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292 | }; |
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293 | |
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294 | /** |
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295 | * @brief run parity protection mechanism check for set of modules described by list. |
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296 | * |
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297 | * @param[in] desc_arr array of pointers to descriptors providing addresses |
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298 | * and ESM channels for individual peripherals. |
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299 | * @param[in] desc_cnt count of pointers in the array |
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300 | * |
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301 | * @return Void, in the case of error invokes bsp_selftest_fail_notification() |
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302 | */ |
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303 | void tms570_selftest_par_run( |
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304 | const tms570_selftest_par_desc_t * |
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305 | const *desc_arr, |
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306 | int desc_cnt |
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307 | ) |
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308 | { |
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309 | int i; |
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310 | const tms570_selftest_par_desc_t *desc; |
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311 | |
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312 | for ( i = 0; i < desc_cnt; i++ ) { |
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313 | desc = desc_arr[ i ]; |
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314 | desc->partest_fnc( desc ); |
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315 | } |
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316 | } |
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