source: rtems/c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_par_mibspi.c @ b2ed712

Last change on this file since b2ed712 was 29430a3, checked in by Pavel Pisa <pisa@…>, on Sep 22, 2016 at 7:50:59 AM

arm/tms570: include hardware initialization and selftest based on Ti HalCoGen? generated files.

The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in

rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c

file.

The list tms570_selftest_par_list in the file

rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c

specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/**
2 * @file tms570_selftest_par_can.c
3 *
4 * @ingroup tms570
5 *
6 * @brief Test MibSPI module parity based protection logic to work.
7 */
8/*
9 * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
10 *
11 * Czech Technical University in Prague
12 * Zikova 1903/4
13 * 166 36 Praha 6
14 * Czech Republic
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 *
20 * Algorithms are based on Ti manuals and Ti HalCoGen generated
21 * code.
22 */
23
24#include <stdint.h>
25#include <stddef.h>
26#include <bsp/tms570.h>
27#include "tms570_selftest.h"
28#include "tms570_selftest_parity.h"
29
30/**
31 * @brief run test to check that parity protection works for MibSPI modules RAM
32 *
33 * @param[in] desc module registers addresses end ESM channels descriptor
34 *
35 * @return Void, in the case of error invokes bsp_selftest_fail_notification()
36 *
37 * The descriptor provides address of the module registers and address
38 * of internal RAM memory and corresponding parity area test access window.
39 */
40void tms570_selftest_par_check_mibspi( const tms570_selftest_par_desc_t *desc )
41{
42  volatile uint32_t      test_read_data;
43  volatile tms570_spi_t *spi_regs = (volatile tms570_spi_t *) desc->fnc_data;
44  uint32_t               mibspie_bak;
45  uint32_t               uerrctl_bak;
46  int                    perr;
47  int                    wait_timeout = 10000;
48
49  /* wait for MibSPI RAM to complete initialization */
50  while ( ( spi_regs->FLG & TMS570_SPI_FLG_BUFINITACTIVE ) ==
51          TMS570_SPI_FLG_BUFINITACTIVE ) {
52    if ( !wait_timeout-- ) {
53      bsp_selftest_fail_notification( desc->fail_code );
54    }
55  }
56
57  /* Store previous configuration of MibSPI */
58  mibspie_bak = spi_regs->MIBSPIE;
59  uerrctl_bak = spi_regs->UERRCTRL;
60
61  /* enable multi-buffered mode */
62  spi_regs->MIBSPIE = TMS570_SPI_MIBSPIE_MSPIENA;
63
64  /* enable parity error detection */
65  spi_regs->UERRCTRL = TMS570_SPI_UERRCTRL_EDEN_SET( spi_regs->UERRCTRL,
66                                                    TMS570_SELFTEST_PAR_CR_KEY );
67
68  /* enable parity test mode */
69  spi_regs->UERRCTRL |= TMS570_SPI_UERRCTRL_PTESTEN;
70
71  /* flip parity bit */
72  *desc->par_loc ^= desc->par_xor;
73
74  /* disable parity TEST mode */
75  spi_regs->UERRCTRL &= ~TMS570_SPI_UERRCTRL_PTESTEN;
76
77  /* read to cause parity error */
78  test_read_data = *desc->ram_loc;
79  (void) test_read_data;
80
81  /* check if ESM channel is flagged */
82  perr = tms570_esm_channel_sr_get( desc->esm_prim_grp, desc->esm_prim_chan );
83
84  if ( !perr ) {
85    /* RAM parity error was not flagged to ESM. */
86    bsp_selftest_fail_notification( desc->fail_code );
87  } else {
88    /* clear parity error flags */
89    spi_regs->UERRSTAT = TMS570_SPI_UERRSTAT_EDFLG1 |
90                         TMS570_SPI_UERRSTAT_EDFLG0;
91
92    /* clear ESM flag */
93    tms570_esm_channel_sr_clear( desc->esm_prim_grp, desc->esm_prim_chan );
94
95    /* enable parity test mode */
96    spi_regs->UERRCTRL |= TMS570_SPI_UERRCTRL_PTESTEN;
97
98    /* Revert back to correct data by flipping parity location */
99    *desc->par_loc ^= desc->par_xor;
100  }
101
102  /* Restore MIBSPI control registers */
103  spi_regs->UERRCTRL = uerrctl_bak;
104  spi_regs->MIBSPIE = mibspie_bak;
105}
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