source: rtems/c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest.c @ 29430a3

Last change on this file since 29430a3 was 29430a3, checked in by Pavel Pisa <pisa@…>, on Sep 22, 2016 at 7:50:59 AM

arm/tms570: include hardware initialization and selftest based on Ti HalCoGen? generated files.

The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in

rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c

file.

The list tms570_selftest_par_list in the file

rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c

specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.

  • Property mode set to 100644
File size: 19.2 KB
Line 
1/**
2 * @file tms570_selftest.c
3 *
4 * @ingroup tms570
5 *
6 * @brief TMS570 selftest support functions implementation.
7 */
8/*
9 * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
10 *
11 *
12 *  Redistribution and use in source and binary forms, with or without
13 *  modification, are permitted provided that the following conditions
14 *  are met:
15 *
16 *    Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 *
19 *    Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the
22 *    distribution.
23 *
24 *    Neither the name of Texas Instruments Incorporated nor the names of
25 *    its contributors may be used to endorse or promote products derived
26 *    from this software without specific prior written permission.
27 *
28 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
41
42#include <stdint.h>
43#include <stdbool.h>
44#include <stddef.h>
45#include <bsp/tms570.h>
46#include "tms570_selftest.h"
47#include "tms570_hwinit.h"
48
49/**
50 * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest).
51 /
52 * @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
53 *
54 * Checks to see if the EFUSE Stuck at zero test is completed successfully.
55 */
56/* SourceId : SELFTEST_SourceId_012 */
57/* DesignId : SELFTEST_DesignId_014 */
58/* Requirements : HL_SR402 */
59bool tms570_efc_stuck_zero( void )
60{
61  uint32_t esm_estatus4, esm_estatus1;
62
63  bool result = false;
64
65  uint32_t output_enable = TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE |
66                           TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE |
67                           TMS570_EFUSE_EFCBOUND_Instruction_Error_OE |
68                           TMS570_EFUSE_EFCBOUND_Autoload_Error_OE;
69
70  uint32_t error_checks = TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error |
71                          TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error |
72                          TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error |
73                          TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error;
74
75  /* configure the output enable for auto load error , instruction info,
76       instruction error, and self test error using boundary register
77       and drive values one across all the errors */
78  TMS570_EFUSE.EFCBOUND = output_enable | error_checks;
79
80  /* Read from the pin register. This register holds the current values
81       of above errors. This value should be 0x5c00.If not at least one of
82       the above errors is stuck at 0. */
83  if ( ( TMS570_EFUSE.EFCPINS & 0x5C00U ) == 0x5C00U ) {
84    esm_estatus4 = TMS570_ESM.SR4;
85    esm_estatus1 = TMS570_ESM.SR[ 2U ];
86
87    /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
88    if ( ( ( esm_estatus4 & 0x200U ) == 0x200U ) &&
89         ( ( esm_estatus1 & 0x2U ) == 0x2U ) ) {
90      /* stuck-at-zero test passed */
91      result = true;
92    }
93  }
94
95  /* put the pins back low */
96  TMS570_EFUSE.EFCBOUND = output_enable;
97
98  /* clear group1 flag */
99  TMS570_ESM.SR4 = 0x200U;
100
101  /* clear group3 flag */
102  TMS570_ESM.SR[ 2U ] = 0x2U;
103
104  /* The nERROR pin will become inactive once the LTC counter expires */
105  TMS570_ESM.EKR = 0x5U;
106
107  return result;
108}
109
110/**
111 * @brief EFUSE module self check Driver (HCG:efcSelfTest)
112 *
113 * This function self checks the EFSUE module.
114 */
115/* SourceId : SELFTEST_SourceId_013 */
116/* DesignId : SELFTEST_DesignId_013 */
117/* Requirements : HL_SR402 */
118void tms570_efc_self_test( void )
119{
120  /* configure self-test cycles */
121  TMS570_EFUSE.EFC_ST_CY = 0x258U;
122
123  /* configure self-test signature */
124  TMS570_EFUSE.EFC_ST_SIG = 0x5362F97FU;
125
126  /* configure boundary register to start ECC self-test */
127  TMS570_EFUSE.EFCBOUND = 0x00002000 |
128                          TMS570_EFUSE_EFCBOUND_Input_Enable( 0xF );
129}
130
131/**
132 * @brief EFUSE module self check Driver (HCG:checkefcSelfTest)
133 *
134 * @return Returns TRUE if EFC Selftest was a PASS, else FALSE
135 *
136 * This function returns the status of efcSelfTest.
137 * Note: This function can be called only after calling efcSelfTest
138 */
139/* SourceId : SELFTEST_SourceId_014 */
140/* DesignId : SELFTEST_DesignId_015 */
141/* Requirements : HL_SR403 */
142bool tms570_efc_check_self_test( void )
143{
144  bool result = false;
145
146  uint32_t efc_pins, efc_error;
147  uint32_t esmCh40Stat, esmCh41Stat = 0U;
148
149  /* wait until EFC self-test is done */
150  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
151  while ( ( TMS570_EFUSE.EFCPINS & TMS570_EFUSE_EFCPINS_EFC_Selftest_Done ) ==
152          0U ) {
153  }                                                                               /* Wait */
154
155  /* check if EFC self-test error occurred */
156  efc_pins = TMS570_EFUSE.EFCPINS;
157  efc_error = TMS570_EFUSE.EFC_ERR_STAT;
158
159  if ( ( ( efc_pins & TMS570_EFUSE_EFCPINS_EFC_Selftest_Error ) == 0U ) &&
160       ( ( efc_error & 0x1FU ) == 0U ) ) {
161    /* check if EFC self-test error is set */
162    esmCh40Stat = TMS570_ESM.SR4 & 0x100U;
163    esmCh41Stat = TMS570_ESM.SR4 & 0x200U;
164
165    if ( ( esmCh40Stat == 0U ) && ( esmCh41Stat == 0U ) ) {
166      result = true;
167    }
168  }
169
170  return result;
171}
172
173/**
174 * @brief EFUSE module self check Driver (HCG:efcCheck)
175 * @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed
176 *                 1 if no error was detected during autoload but Stuck At Zero Test failed
177 *                 2 if there was a single-bit error detected during autoload
178 *                 3 if some other error occurred during autoload
179 *
180 *   This function self checks the EFUSE module.
181 */
182/* SourceId : SELFTEST_SourceId_011 */
183/* DesignId : SELFTEST_DesignId_012 */
184/* Requirements : HL_SR402 */
185uint32_t tms570_efc_check( void )
186{
187  uint32_t efc_status = 0U;
188  uint32_t status;
189
190  /* read the EFC Error Status Register */
191  efc_status = TMS570_EFUSE.EFC_ERR_STAT;
192
193  if ( efc_status == 0x0U ) {
194    /* run stuck-at-zero test and check if it passed */
195    if ( tms570_efc_stuck_zero() == true ) {
196      /* start EFC ECC logic self-test */
197      tms570_efc_self_test();
198      status = 0U;
199    } else {
200      /* EFC output is stuck-at-zero, device operation unreliable */
201      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
202      status = 1U;
203    }
204  }
205  /* EFC Error Register is not zero */
206  else {
207    /* one-bit error detected during autoload */
208    if ( efc_status == 0x15U ) {
209      /* start EFC ECC logic self-test */
210      tms570_efc_self_test();
211      status = 2U;
212    } else {
213      /* Some other EFC error was detected */
214      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
215      status = 3U;
216    }
217  }
218
219  return status;
220}
221
222/**
223 * @brief PBIST self test Driver (HCG:pbistSelfCheck)
224 *
225 * This function is called to perform PBIST self test.
226 */
227/* SourceId : SELFTEST_SourceId_005 */
228/* DesignId : SELFTEST_DesignId_005 */
229/* Requirements : HL_SR399 */
230void tms570_pbist_self_check( void )
231{
232  volatile uint32_t i = 0U;
233  uint32_t          PBIST_wait_done_loop = 0U;
234
235  /* Run a diagnostic check on the memory self-test controller */
236  /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
237
238  /* Disable PBIST clocks and ROM clock */
239  TMS570_PBIST.PACT = 0x0U;
240
241  /* PBIST ROM clock frequency = HCLK frequency /2 */
242  /* Disable memory self controller */
243  TMS570_SYS1.MSTGCR = 0x00000105U;
244
245  /* Disable Memory Initialization controller */
246  TMS570_SYS1.MINITGCR = 0x5U;
247
248  /* Enable memory self controller */
249  TMS570_SYS1.MSTGCR = 0x0000010AU;
250
251  /* Clear PBIST Done */
252  TMS570_SYS1.MSTCGSTAT = 0x1U;
253
254  /* Enable PBIST controller */
255  TMS570_SYS1.MSIENA = 0x1U;
256
257  /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
258  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
259  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
260  for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
261  }
262
263  /* Enable PBIST clocks and ROM clock */
264  TMS570_PBIST.PACT = 0x3U;
265
266  /* CPU control of PBIST */
267  TMS570_PBIST.DLR = 0x10U;
268
269  /* Custom always fail algo, this will not use the ROM and just set a fail */
270  TMS570_PBIST.RAMT = 0x00002000U;
271  *(volatile uint32_t *) 0xFFFFE400U = 0x4C000001U;
272  *(volatile uint32_t *) 0xFFFFE440U = 0x00000075U;
273  *(volatile uint32_t *) 0xFFFFE404U = 0x4C000002U;
274  *(volatile uint32_t *) 0xFFFFE444U = 0x00000075U;
275  *(volatile uint32_t *) 0xFFFFE408U = 0x4C000003U;
276  *(volatile uint32_t *) 0xFFFFE448U = 0x00000075U;
277  *(volatile uint32_t *) 0xFFFFE40CU = 0x4C000004U;
278  *(volatile uint32_t *) 0xFFFFE44CU = 0x00000075U;
279  *(volatile uint32_t *) 0xFFFFE410U = 0x4C000005U;
280  *(volatile uint32_t *) 0xFFFFE450U = 0x00000075U;
281  *(volatile uint32_t *) 0xFFFFE414U = 0x4C000006U;
282  *(volatile uint32_t *) 0xFFFFE454U = 0x00000075U;
283  *(volatile uint32_t *) 0xFFFFE418U = 0x00000000U;
284  *(volatile uint32_t *) 0xFFFFE458U = 0x00000001U;
285
286  /* PBIST_RUN */
287  ( &TMS570_PBIST.DLR )[ 2 ] = 1;
288
289  /* wait until memory self-test done is indicated */
290  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
291  while ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0x1U )
292    PBIST_wait_done_loop++;
293
294  /* Wait */
295
296  /* Check for the failure */
297  if ( ( TMS570_PBIST.FSRF0 & 0x1U ) != 0x1U ) {
298    /* No failure was indicated even if the always fail algorithm was run*/
299    bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL1 );
300  } else {
301    /* Check that the algorithm executed in the expected amount of time. */
302    /* This time is dependent on the ROMCLKDIV selected above            */
303    if ( PBIST_wait_done_loop >= 2U ) {
304      bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL2 );
305    }
306
307    /* Disable PBIST clocks and ROM clock */
308    TMS570_PBIST.PACT = 0x0U;
309
310    /* Disable PBIST */
311    TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
312    TMS570_SYS1.MSTGCR |= 0x5U;
313  }
314}
315
316/**
317 * @brief CPU self test Driver (HCG:pbistRun)
318 * @param[in] raminfoL   - Select the list of RAM to be tested.
319 * @param[in] algomask   - Select the list of Algorithm to be run.
320 *
321 * This function performs Memory Built-in Self test using PBIST module.
322 */
323/* SourceId : SELFTEST_SourceId_006 */
324/* DesignId : SELFTEST_DesignId_006 */
325/* Requirements : HL_SR400 */
326void tms570_pbist_run(
327  uint32_t raminfoL,
328  uint32_t algomask
329)
330{
331  volatile uint32_t i = 0U;
332
333  /* PBIST ROM clock frequency = HCLK frequency /2 */
334  /* Disable memory self controller */
335  TMS570_SYS1.MSTGCR = 0x00000105U;
336
337  /* Disable Memory Initialization controller */
338  TMS570_SYS1.MINITGCR = 0x5U;
339
340  /* Enable PBIST controller */
341  TMS570_SYS1.MSIENA = 0x1U;
342
343  /* Enable memory self controller */
344  TMS570_SYS1.MSTGCR = 0x0000010AU;
345
346  /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
347  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
348  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
349  for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
350  }
351
352  /* Enable PBIST clocks and ROM clock */
353  TMS570_PBIST.PACT = 0x3U;
354
355  /* Select all algorithms to be tested */
356  TMS570_PBIST.ALGO = algomask;
357
358  /* Select RAM groups */
359  TMS570_PBIST.RINFOL = raminfoL;
360
361  /* Select all RAM groups */
362  TMS570_PBIST.RINFOUL = 0x00000000U;
363
364  /* ROM contents will not override RINFOx settings */
365  TMS570_PBIST.OVER = 0x0U;
366
367  /* Algorithm code is loaded from ROM */
368  TMS570_PBIST.ROM = 0x3U;
369
370  /* Start PBIST */
371  TMS570_PBIST.DLR = 0x14U;
372}
373
374/**
375 *  @brief Routine to stop PBIST test enabled (HCG:pbistStop)
376 *
377 *  This function is called to stop PBIST after test is performed.
378 */
379/* SourceId : SELFTEST_SourceId_007 */
380/* DesignId : SELFTEST_DesignId_007 */
381/* Requirements : HL_SR523 */
382void tms570_pbist_stop( void )
383{
384  /* disable pbist clocks and ROM clock */
385  TMS570_PBIST.PACT = 0x0U;
386  TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
387  TMS570_SYS1.MSTGCR |= 0x5U;
388}
389
390/**
391 * @brief Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted)
392 * @return 1 if PBIST test completed, otherwise 0.
393 *
394 * Checks to see if the PBIST test is completed.
395 */
396/* SourceId : SELFTEST_SourceId_008 */
397/* DesignId : SELFTEST_DesignId_008 */
398/* Requirements : HL_SR401 */
399bool tms570_pbist_is_test_completed( void )
400{
401  return ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0U );
402}
403
404/**
405 * @brief Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed)
406 * @return 1 if PBIST test passed, otherwise 0.
407 *
408 * Checks to see if the PBIST test is completed successfully.
409 */
410/* SourceId : SELFTEST_SourceId_009 */
411/* DesignId : SELFTEST_DesignId_009 */
412/* Requirements : HL_SR401 */
413bool tms570_pbist_is_test_passed( void )
414{
415  bool status;
416
417  if ( TMS570_PBIST.FSRF0 == 0U ) {
418    status = true;
419  } else {
420    status = false;
421  }
422
423  return status;
424}
425
426/**
427 * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
428 * @param[in] port   - Select the port to get the status.
429 * @return 1 if PBIST Port test completed successfully, otherwise 0.
430 *
431 * Checks to see if the selected PBIST Port test is completed successfully.
432 */
433/* SourceId : SELFTEST_SourceId_010 */
434/* DesignId : SELFTEST_DesignId_010 */
435/* Requirements : HL_SR401 */
436bool tms570_pbist_port_test_status( uint32_t port )
437{
438  bool status;
439
440  if ( port == (uint32_t) PBIST_PORT0 ) {
441    status = ( TMS570_PBIST.FSRF0 == 0U );
442  } else {
443    /* Invalid Input */
444    status = false;
445  }
446
447  return status;
448}
449
450/**
451 * @brief Reaction to PBIST failure (HCG:pbistFail)
452 *
453 * @return Void.
454 */
455/* SourceId : SELFTEST_SourceId_042 */
456/* DesignId : SELFTEST_DesignId_011 */
457/* Requirements : HL_SR401 */
458void tms570_pbist_fail( void )
459{
460  uint32_t PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0;
461
462  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
463  PBIST_RAMT = TMS570_PBIST.RAMT;
464  PBIST_FSRA0 = TMS570_PBIST.FSRA0;
465  PBIST_FSRDL0 = TMS570_PBIST.FSRDL0;
466
467  if ( tms570_pbist_port_test_status( (uint32_t) PBIST_PORT0 ) != true ) {
468    uint32_t groupSelect = ( PBIST_RAMT & 0xFF000000U ) >> 24U;
469    uint32_t dataSelect = ( PBIST_RAMT & 0x00FF0000U ) >> 16U;
470    uint32_t address = PBIST_FSRA0;
471    uint32_t data = PBIST_FSRDL0;
472    tms570_memory_port0_fail_notification( groupSelect,
473      dataSelect,
474      address,
475      data );
476  } else {
477/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
478/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
479/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
480    for (;; ) {
481    }           /* Wait */
482  }
483}
484
485/**
486 * @brief Memory Initialization Driver (HCG:memoryInit)
487 *
488 * This function is called to perform Memory initialization of selected RAM's.
489 */
490/* SourceId : SELFTEST_SourceId_002 */
491/* DesignId : SELFTEST_DesignId_004 */
492/* Requirements : HL_SR396 */
493void tms570_memory_init( uint32_t ram )
494{
495  /* Enable Memory Hardware Initialization */
496  TMS570_SYS1.MINITGCR = 0xAU;
497
498  /* Enable Memory Hardware Initialization for selected RAM's */
499  TMS570_SYS1.MSIENA = ram;
500
501  /* Wait until Memory Hardware Initialization complete */
502  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
503  while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) {
504  }                                                              /* Wait */
505
506  /* Disable Memory Hardware Initialization */
507  TMS570_SYS1.MINITGCR = 0x5U;
508}
509
510volatile uint32_t *const
511tms570_esm_group_channel_to_sr_table[ 4 ][ 2 ] = {
512  { NULL, NULL },
513  { &TMS570_ESM.SR[ 0 ], &TMS570_ESM.SR4 },
514  { &TMS570_ESM.SR[ 1 ], NULL },
515  { &TMS570_ESM.SR[ 2 ], NULL },
516};
517
518/**
519 * @brief Routine to clear specified error channel signalling bit
520 * @param[in] grp   - ESM error channels group
521 * @param[in] chan  - ESM error channel number inside specified group
522 */
523void tms570_esm_channel_sr_clear(
524  unsigned grp,
525  unsigned chan
526)
527{
528  volatile uint32_t *sr_reg;
529
530  sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
531
532  if ( sr_reg != NULL )
533    *sr_reg = 1 << (chan & 0x1f);
534}
535
536/** tms570_esm_channel_sr_get
537 * @brief Routine to test is specified error channel is signalling error
538 * @param[in] grp   - ESM error channels group
539 * @param[in] chan  - ESM error channel number inside specified group
540 */
541int tms570_esm_channel_sr_get(
542  unsigned grp,
543  unsigned chan
544)
545{
546  volatile uint32_t *sr_reg;
547
548  sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
549
550  if ( sr_reg != NULL )
551    return *sr_reg & ( 1 << ( chan & 0x1f ) );
552  else
553    return 0;
554}
555
556/**
557 * @brief Enable peripheral RAM parity (HCG:enableParity)
558 *
559 * This function enables RAM parity for all peripherals for which RAM parity check is enabled.
560 * This function is called before memoryInit in the startup
561 *
562 */
563void tms570_enable_parity( void )
564{
565  TMS570_DMA.DMAPCR = 0xAU;                   /* Enable DMA RAM parity */
566  TMS570_VIM.PARCTL = 0xAU;                   /* Enable VIM RAM parity */
567  TMS570_DCAN1.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */
568  TMS570_DCAN2.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */
569  TMS570_DCAN3.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN3 RAM parity */
570  TMS570_ADC1.PARCR = 0xAU;                   /* Enable ADC1 RAM parity */
571  TMS570_ADC2.PARCR = 0xAU;                   /* Enable ADC2 RAM parity */
572  TMS570_NHET1.PCR  = 0xAU;                   /* Enable HET1 RAM parity */
573  TMS570_HTU1.PCR   = 0xAU;                   /* Enable HTU1 RAM parity */
574  TMS570_NHET2.PCR  = 0xAU;                   /* Enable HET2 RAM parity */
575  TMS570_HTU2.PCR   = 0xAU;                   /* Enable HTU2 RAM parity */
576}
577
578/**
579 * @brief Disable peripheral RAM parity (HCG:disableParity)
580 *
581 * This function disables RAM parity for all peripherals for which RAM parity check is enabled.
582 * This function is called after memoryInit in the startup
583 *
584 */
585void tms570_disable_parity( void )
586{
587  TMS570_DMA.DMAPCR = 0x5U;                   /* Disable DMA RAM parity */
588  TMS570_VIM.PARCTL = 0x5U;                   /* Disable VIM RAM parity */
589  TMS570_DCAN1.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */
590  TMS570_DCAN2.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */
591  TMS570_DCAN3.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN3 RAM parity */
592  TMS570_ADC1.PARCR = 0x5U;                   /* Disable ADC1 RAM parity */
593  TMS570_ADC2.PARCR = 0x5U;                   /* Disable ADC2 RAM parity */
594  TMS570_NHET1.PCR  = 0x5U;                   /* Disable HET1 RAM parity */
595  TMS570_HTU1.PCR   = 0x5U;                   /* Disable HTU1 RAM parity */
596  TMS570_NHET2.PCR  = 0x5U;                   /* Disable HET2 RAM parity */
597  TMS570_HTU2.PCR   = 0x5U;                   /* Disable HTU2 RAM parity */
598}
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