1 | #include <stdint.h> |
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2 | #include <bsp.h> |
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3 | #include <bsp/start.h> |
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4 | #include <bsp/tms570.h> |
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5 | |
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6 | #include "tms570_selftest.h" |
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7 | #include "tms570_selftest_parity.h" |
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8 | #include "tms570_hwinit.h" |
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9 | |
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10 | void bsp_start_hook_0_done( void ); |
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11 | |
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12 | static inline |
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13 | int tms570_running_from_tcram( void ) |
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14 | { |
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15 | void *fncptr = (void*)bsp_start_hook_0; |
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16 | return ( fncptr >= (void*)TMS570_TCRAM_START_PTR ) && |
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17 | ( fncptr < (void*)TMS570_TCRAM_WINDOW_END_PTR ); |
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18 | } |
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19 | |
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20 | static inline |
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21 | int tms570_running_from_sdram( void ) |
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22 | { |
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23 | void *fncptr = (void*)bsp_start_hook_0; |
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24 | return ( ( (void*)fncptr >= (void*)TMS570_SDRAM_START_PTR ) && |
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25 | ( (void*)fncptr < (void*)TMS570_SDRAM_WINDOW_END_PTR ) ); |
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26 | } |
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27 | |
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28 | #define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */ |
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29 | |
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30 | BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) |
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31 | { |
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32 | /* |
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33 | * Work Around for Errata DEVICE#140: ( Only on Rev A silicon) |
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34 | * |
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35 | * Errata Description: |
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36 | * The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on |
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37 | * Workaround: |
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38 | * Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register |
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39 | */ |
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40 | if ( TMS570_SYS1.DEVID == 0x802AAD05U ) { |
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41 | _esmCcmErrorsClear_(); |
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42 | } |
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43 | |
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44 | /* Enable CPU Event Export */ |
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45 | /* This allows the CPU to signal any single-bit or double-bit errors detected |
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46 | * by its ECC logic for accesses to program flash or data RAM. |
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47 | */ |
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48 | _coreEnableEventBusExport_(); |
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49 | |
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50 | /* Workaround for Errata CORTEXR4 66 */ |
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51 | _errata_CORTEXR4_66_(); |
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52 | |
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53 | /* Workaround for Errata CORTEXR4 57 */ |
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54 | _errata_CORTEXR4_57_(); |
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55 | |
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56 | /* check for power-on reset condition */ |
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57 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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58 | if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_PORST ) != 0U ) { |
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59 | /* clear all reset status flags */ |
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60 | TMS570_SYS1.SYSESR = 0xFFFFU; |
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61 | |
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62 | /* continue with normal start-up sequence */ |
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63 | } |
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64 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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65 | else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_OSCRST ) != 0U ) { |
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66 | /* Reset caused due to oscillator failure. |
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67 | Add user code here to handle oscillator failure */ |
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68 | } |
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69 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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70 | else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_WDRST ) != 0U ) { |
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71 | /* Reset caused due |
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72 | * 1) windowed watchdog violation - Add user code here to handle watchdog violation. |
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73 | * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS |
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74 | */ |
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75 | /* Check the WatchDog Status register */ |
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76 | if ( TMS570_RTI.WDSTATUS != 0U ) { |
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77 | /* Add user code here to handle watchdog violation. */ |
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78 | /* Clear the Watchdog reset flag in Exception Status register */ |
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79 | TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; |
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80 | } else { |
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81 | /* Clear the ICEPICK reset flag in Exception Status register */ |
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82 | TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; |
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83 | } |
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84 | } |
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85 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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86 | else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_CPURST ) != 0U ) { |
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87 | /* Reset caused due to CPU reset. |
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88 | CPU reset can be caused by CPU self-test completion, or |
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89 | by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ |
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90 | |
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91 | /* clear all reset status flags */ |
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92 | TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_CPURST; |
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93 | } |
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94 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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95 | else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_SWRST ) != 0U ) { |
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96 | /* Reset caused due to software reset. |
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97 | Add user code to handle software reset. */ |
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98 | } else { |
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99 | /* Reset caused by nRST being driven low externally. |
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100 | Add user code to handle external reset. */ |
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101 | } |
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102 | |
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103 | /* |
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104 | * Check if there were ESM group3 errors during power-up. |
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105 | * These could occur during eFuse auto-load or during reads from flash OTP |
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106 | * during power-up. Device operation is not reliable and not recommended |
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107 | * in this case. |
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108 | * An ESM group3 error only drives the nERROR pin low. An external circuit |
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109 | * that monitors the nERROR pin must take the appropriate action to ensure that |
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110 | * the system is placed in a safe state, as determined by the application. |
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111 | */ |
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112 | if ( ( TMS570_ESM.SR[ 2 ] ) != 0U ) { |
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113 | /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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114 | /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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115 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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116 | for (;; ) { |
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117 | } /* Wait */ |
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118 | } |
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119 | |
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120 | /* Initialize System - Clock, Flash settings with Efuse self check */ |
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121 | tms570_system_hw_init(); |
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122 | |
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123 | /* Workaround for Errata PBIST#4 */ |
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124 | /* FIXME */ |
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125 | //errata_PBIST_4(); |
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126 | |
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127 | /* |
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128 | * Run a diagnostic check on the memory self-test controller. |
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129 | * This function chooses a RAM test algorithm and runs it on an on-chip ROM. |
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130 | * The memory self-test is expected to fail. The function ensures that the PBIST controller |
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131 | * is capable of detecting and indicating a memory self-test failure. |
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132 | */ |
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133 | tms570_pbist_self_check(); |
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134 | |
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135 | /* Run PBIST on STC ROM */ |
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136 | tms570_pbist_run( (uint32_t) STC_ROM_PBIST_RAM_GROUP, |
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137 | ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); |
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138 | |
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139 | /* Wait for PBIST for STC ROM to be completed */ |
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140 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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141 | while ( tms570_pbist_is_test_completed() != TRUE ) { |
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142 | } /* Wait */ |
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143 | |
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144 | /* Check if PBIST on STC ROM passed the self-test */ |
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145 | if ( tms570_pbist_is_test_passed() != TRUE ) { |
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146 | /* PBIST and STC ROM failed the self-test. |
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147 | * Need custom handler to check the memory failure |
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148 | * and to take the appropriate next step. |
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149 | */ |
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150 | tms570_pbist_fail(); |
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151 | } |
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152 | |
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153 | /* Disable PBIST clocks and disable memory self-test mode */ |
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154 | tms570_pbist_stop(); |
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155 | |
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156 | /* Run PBIST on PBIST ROM */ |
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157 | tms570_pbist_run( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP, |
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158 | ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); |
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159 | |
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160 | /* Wait for PBIST for PBIST ROM to be completed */ |
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161 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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162 | while ( tms570_pbist_is_test_completed() != TRUE ) { |
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163 | } /* Wait */ |
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164 | |
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165 | /* Check if PBIST ROM passed the self-test */ |
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166 | if ( tms570_pbist_is_test_passed() != TRUE ) { |
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167 | /* PBIST and STC ROM failed the self-test. |
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168 | * Need custom handler to check the memory failure |
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169 | * and to take the appropriate next step. |
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170 | */ |
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171 | tms570_pbist_fail(); |
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172 | } |
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173 | |
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174 | /* Disable PBIST clocks and disable memory self-test mode */ |
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175 | tms570_pbist_stop(); |
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176 | |
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177 | if ( !tms570_running_from_tcram() ) { |
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178 | /* |
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179 | * The next sequence tests TCRAM, main TMS570 system operation RAM area. |
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180 | * The tests are destructive, lead the first to fill memory by 0xc5c5c5c5 |
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181 | * and then to clear it to zero. The sequence is obliviously incompatible |
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182 | * with RTEMS image running from TCRAM area (code clears itself). |
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183 | * |
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184 | * But TCRAM clear leads to overwrite of stack which is used to store |
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185 | * value of bsp_start_hook_0 call return address from link register. |
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186 | * |
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187 | * If the bsp_start_hook_0 by jump to bsp_start_hook_0_done |
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188 | * then generated C code does not use any variable which |
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189 | * is stores on stack and code works OK even that memory |
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190 | * is cleared during bsp_start_hook_0 execution. |
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191 | * |
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192 | * The last assumption is a little fragile in respect to |
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193 | * code and compiler changes. |
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194 | */ |
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195 | |
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196 | /* Disable RAM ECC before doing PBIST for Main RAM */ |
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197 | _coreDisableRamEcc_(); |
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198 | |
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199 | /* Run PBIST on CPU RAM. |
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200 | * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs. |
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201 | * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the |
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202 | * device datasheet. |
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203 | */ |
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204 | tms570_pbist_run( 0x08300020U, /* ESRAM Single Port PBIST */ |
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205 | (uint32_t) PBIST_March13N_SP ); |
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206 | |
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207 | /* Wait for PBIST for CPU RAM to be completed */ |
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208 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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209 | while ( tms570_pbist_is_test_completed() != TRUE ) { |
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210 | } /* Wait */ |
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211 | |
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212 | /* Check if CPU RAM passed the self-test */ |
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213 | if ( tms570_pbist_is_test_passed() != TRUE ) { |
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214 | /* CPU RAM failed the self-test. |
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215 | * Need custom handler to check the memory failure |
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216 | * and to take the appropriate next step. |
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217 | */ |
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218 | tms570_pbist_fail(); |
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219 | } |
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220 | |
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221 | /* Disable PBIST clocks and disable memory self-test mode */ |
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222 | tms570_pbist_stop(); |
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223 | |
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224 | /* |
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225 | * Initialize CPU RAM. |
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226 | * This function uses the system module's hardware for auto-initialization of memories and their |
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227 | * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. |
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228 | * Hence the value 0x1 passed to the function. |
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229 | * This function will initialize the entire CPU RAM and the corresponding ECC locations. |
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230 | */ |
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231 | tms570_memory_init( 0x1U ); |
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232 | |
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233 | /* |
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234 | * Enable ECC checking for TCRAM accesses. |
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235 | * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. |
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236 | */ |
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237 | _coreEnableRamEcc_(); |
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238 | } /* end of the code skipped for tms570_running_from_tcram() */ |
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239 | |
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240 | /* Start PBIST on all dual-port memories */ |
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241 | /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. |
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242 | PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. |
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243 | */ |
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244 | tms570_pbist_run( (uint32_t) 0x00000000U | /* EMAC RAM */ |
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245 | (uint32_t) 0x00000000U | /* USB RAM */ |
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246 | (uint32_t) 0x00000800U | /* DMA RAM */ |
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247 | (uint32_t) 0x00000200U | /* VIM RAM */ |
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248 | (uint32_t) 0x00000040U | /* MIBSPI1 RAM */ |
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249 | (uint32_t) 0x00000080U | /* MIBSPI3 RAM */ |
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250 | (uint32_t) 0x00000100U | /* MIBSPI5 RAM */ |
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251 | (uint32_t) 0x00000004U | /* CAN1 RAM */ |
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252 | (uint32_t) 0x00000008U | /* CAN2 RAM */ |
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253 | (uint32_t) 0x00000010U | /* CAN3 RAM */ |
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254 | (uint32_t) 0x00000400U | /* ADC1 RAM */ |
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255 | (uint32_t) 0x00020000U | /* ADC2 RAM */ |
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256 | (uint32_t) 0x00001000U | /* HET1 RAM */ |
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257 | (uint32_t) 0x00040000U | /* HET2 RAM */ |
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258 | (uint32_t) 0x00002000U | /* HTU1 RAM */ |
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259 | (uint32_t) 0x00080000U | /* HTU2 RAM */ |
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260 | (uint32_t) 0x00004000U | /* RTP RAM */ |
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261 | (uint32_t) 0x00008000U, /* FRAY RAM */ |
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262 | (uint32_t) PBIST_March13N_DP ); |
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263 | |
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264 | if ( !tms570_running_from_tcram() ) { |
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265 | |
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266 | /* Test the CPU ECC mechanism for RAM accesses. |
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267 | * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses |
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268 | * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error |
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269 | * in the ECC causes a data abort exception. The data abort handler is written to look for |
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270 | * deliberately caused exception and to return the code execution to the instruction |
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271 | * following the one that caused the abort. |
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272 | */ |
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273 | tms570_check_tcram_ecc(); |
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274 | |
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275 | /* Wait for PBIST for CPU RAM to be completed */ |
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276 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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277 | while ( tms570_pbist_is_test_completed() != TRUE ) { |
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278 | } /* Wait */ |
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279 | |
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280 | /* Check if CPU RAM passed the self-test */ |
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281 | if ( tms570_pbist_is_test_passed() != TRUE ) { |
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282 | /* CPU RAM failed the self-test. |
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283 | * Need custom handler to check the memory failure |
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284 | * and to take the appropriate next step. |
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285 | */ |
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286 | tms570_pbist_fail(); |
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287 | } |
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288 | |
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289 | } /* end of the code skipped for tms570_running_from_tcram() */ |
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290 | |
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291 | /* Disable PBIST clocks and disable memory self-test mode */ |
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292 | tms570_pbist_stop(); |
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293 | |
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294 | /* Release the MibSPI1 modules from local reset. |
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295 | * This will cause the MibSPI1 RAMs to get initialized along with the parity memory. |
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296 | */ |
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297 | TMS570_SPI1.GCR0 = TMS570_SPI_GCR0_nRESET; |
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298 | |
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299 | /* Release the MibSPI3 modules from local reset. |
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300 | * This will cause the MibSPI3 RAMs to get initialized along with the parity memory. |
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301 | */ |
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302 | TMS570_SPI3.GCR0 = TMS570_SPI_GCR0_nRESET; |
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303 | |
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304 | /* Release the MibSPI5 modules from local reset. |
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305 | * This will cause the MibSPI5 RAMs to get initialized along with the parity memory. |
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306 | */ |
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307 | TMS570_SPI5.GCR0 = TMS570_SPI_GCR0_nRESET; |
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308 | |
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309 | /* Enable parity on selected RAMs */ |
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310 | tms570_enable_parity(); |
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311 | |
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312 | /* Initialize all on-chip SRAMs except for MibSPIx RAMs |
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313 | * The MibSPIx modules have their own auto-initialization mechanism which is triggered |
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314 | * as soon as the modules are brought out of local reset. |
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315 | */ |
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316 | /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset. |
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317 | */ |
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318 | /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers. |
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319 | Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. |
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320 | */ |
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321 | tms570_memory_init( (uint32_t) ( (uint32_t) 1U << 1U ) | /* DMA RAM */ |
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322 | (uint32_t) ( (uint32_t) 1U << 2U ) | /* VIM RAM */ |
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323 | (uint32_t) ( (uint32_t) 1U << 5U ) | /* CAN1 RAM */ |
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324 | (uint32_t) ( (uint32_t) 1U << 6U ) | /* CAN2 RAM */ |
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325 | (uint32_t) ( (uint32_t) 1U << 10U ) | /* CAN3 RAM */ |
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326 | (uint32_t) ( (uint32_t) 1U << 8U ) | /* ADC1 RAM */ |
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327 | (uint32_t) ( (uint32_t) 1U << 14U ) | /* ADC2 RAM */ |
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328 | (uint32_t) ( (uint32_t) 1U << 3U ) | /* HET1 RAM */ |
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329 | (uint32_t) ( (uint32_t) 1U << 4U ) | /* HTU1 RAM */ |
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330 | (uint32_t) ( (uint32_t) 1U << 15U ) | /* HET2 RAM */ |
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331 | (uint32_t) ( (uint32_t) 1U << 16U ) /* HTU2 RAM */ |
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332 | ); |
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333 | |
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334 | /* Disable parity */ |
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335 | tms570_disable_parity(); |
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336 | |
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337 | /* |
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338 | * Test the parity protection mechanism for peripheral RAMs |
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339 | * Refer DEVICE DATASHEET for the list of Supported Memories |
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340 | * with parity. |
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341 | */ |
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342 | |
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343 | tms570_selftest_par_run( tms570_selftest_par_list, |
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344 | tms570_selftest_par_list_size ); |
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345 | |
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346 | #if 0 |
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347 | /* |
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348 | * RTEMS VIM initialization is implemented by the function |
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349 | * bsp_interrupt_facility_initialize(). RTEMS does not |
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350 | * gain performance from use of vectors targets provided |
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351 | * directly by VIM. RTEMS require to route all interrupts |
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352 | * through _ARMV4_Exception_interrupt handler. |
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353 | * |
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354 | * But actual RTEMS VIM initialization lefts some registers |
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355 | * default values untouched. All registers values should be |
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356 | * ensured/configured in future probably. |
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357 | */ |
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358 | |
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359 | /* Enable IRQ offset via Vic controller */ |
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360 | _coreEnableIrqVicOffset_(); |
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361 | |
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362 | /* Initialize VIM table */ |
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363 | vimInit(); |
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364 | #endif |
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365 | |
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366 | /* Configure system response to error conditions signaled to the ESM group1 */ |
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367 | tms570_esm_init(); |
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368 | |
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369 | #if 1 |
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370 | /* |
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371 | * Do not depend on link register to be restored to |
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372 | * correct value from stack. If TCRAM self test is enabled |
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373 | * the all stack content is zeroed there. |
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374 | */ |
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375 | bsp_start_hook_0_done(); |
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376 | #endif |
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377 | } |
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378 | |
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379 | BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) |
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380 | { |
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381 | /* At this point we can use objects outside the .start section */ |
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382 | #if 0 |
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383 | /* Do not run attempt to initialize MPU when code is running from SDRAM */ |
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384 | if ( !tms570_running_from_sdram() ) { |
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385 | /* |
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386 | * MPU background areas setting has to be overlaid |
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387 | * if execution of code is required from external memory/SDRAM. |
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388 | * This region is non executable by default. |
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389 | */ |
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390 | _mpuInit_(); |
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391 | } |
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392 | #endif |
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393 | tms570_emif_sdram_init(); |
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394 | |
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395 | bsp_start_copy_sections(); |
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396 | bsp_start_clear_bss(); |
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397 | } |
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398 | |
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399 | /* |
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400 | * Chip specific list of peripherals which should be tested |
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401 | * for functional RAM parity reporting |
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402 | */ |
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403 | const tms570_selftest_par_desc_t *const |
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404 | tms570_selftest_par_list[] = { |
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405 | &tms570_selftest_par_het1_desc, |
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406 | &tms570_selftest_par_htu1_desc, |
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407 | &tms570_selftest_par_het2_desc, |
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408 | &tms570_selftest_par_htu2_desc, |
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409 | &tms570_selftest_par_adc1_desc, |
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410 | &tms570_selftest_par_adc2_desc, |
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411 | &tms570_selftest_par_can1_desc, |
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412 | &tms570_selftest_par_can2_desc, |
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413 | &tms570_selftest_par_can3_desc, |
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414 | &tms570_selftest_par_vim_desc, |
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415 | &tms570_selftest_par_dma_desc, |
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416 | &tms570_selftest_par_spi1_desc, |
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417 | &tms570_selftest_par_spi3_desc, |
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418 | &tms570_selftest_par_spi5_desc, |
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419 | }; |
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420 | |
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421 | const int tms570_selftest_par_list_size = |
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422 | RTEMS_ARRAY_SIZE( tms570_selftest_par_list ); |
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