1 | /** |
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2 | ****************************************************************************** |
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3 | * @file stm32f7xx_hal_rcc_ex.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.0.1 |
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6 | * @date 25-June-2015 |
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7 | * @brief Extension RCC HAL module driver. |
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8 | * This file provides firmware functions to manage the following |
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9 | * functionalities RCC extension peripheral: |
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10 | * + Extended Peripheral Control functions |
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11 | * |
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12 | ****************************************************************************** |
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13 | * @attention |
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14 | * |
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15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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16 | * |
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17 | * Redistribution and use in source and binary forms, with or without modification, |
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18 | * are permitted provided that the following conditions are met: |
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19 | * 1. Redistributions of source code must retain the above copyright notice, |
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20 | * this list of conditions and the following disclaimer. |
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21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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22 | * this list of conditions and the following disclaimer in the documentation |
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23 | * and/or other materials provided with the distribution. |
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24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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25 | * may be used to endorse or promote products derived from this software |
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26 | * without specific prior written permission. |
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27 | * |
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28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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38 | * |
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39 | ****************************************************************************** |
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40 | */ |
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41 | |
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42 | /* Includes ------------------------------------------------------------------*/ |
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43 | #include "stm32f7xx_hal.h" |
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44 | |
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45 | /** @addtogroup STM32F7xx_HAL_Driver |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | /** @defgroup RCCEx RCCEx |
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50 | * @brief RCCEx HAL module driver |
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51 | * @{ |
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52 | */ |
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53 | |
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54 | #ifdef HAL_RCC_MODULE_ENABLED |
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55 | |
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56 | /* Private typedef -----------------------------------------------------------*/ |
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57 | /* Private define ------------------------------------------------------------*/ |
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58 | /** @defgroup RCCEx_Private_Defines RCCEx Private Defines |
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59 | * @{ |
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60 | */ |
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61 | |
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62 | #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
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63 | #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
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64 | |
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65 | /** |
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66 | * @} |
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67 | */ |
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68 | /* Private macro -------------------------------------------------------------*/ |
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69 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
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70 | * @{ |
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71 | */ |
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72 | /** |
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73 | * @} |
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74 | */ |
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75 | |
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76 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
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77 | * @{ |
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78 | */ |
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79 | |
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80 | /** |
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81 | * @} |
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82 | */ |
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83 | |
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84 | |
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85 | /* Private variables ---------------------------------------------------------*/ |
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86 | /* Private function prototypes -----------------------------------------------*/ |
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87 | /* Private functions ---------------------------------------------------------*/ |
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88 | |
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89 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
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90 | * @{ |
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91 | */ |
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92 | |
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93 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
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94 | * @brief Extended Peripheral Control functions |
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95 | * |
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96 | @verbatim |
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97 | =============================================================================== |
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98 | ##### Extended Peripheral Control functions ##### |
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99 | =============================================================================== |
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100 | [..] |
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101 | This subsection provides a set of functions allowing to control the RCC Clocks |
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102 | frequencies. |
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103 | [..] |
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104 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
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105 | select the RTC clock source; in this case the Backup domain will be reset in |
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106 | order to modify the RTC Clock source, as consequence RTC registers (including |
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107 | the backup registers) and RCC_BDCR register will be set to their reset values. |
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108 | |
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109 | @endverbatim |
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110 | * @{ |
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111 | */ |
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112 | /** |
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113 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
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114 | * parameters in the RCC_PeriphCLKInitTypeDef. |
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115 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
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116 | * contains the configuration information for the Extended Peripherals |
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117 | * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). |
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118 | * |
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119 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
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120 | * the RTC clock source; in this case the Backup domain will be reset in |
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121 | * order to modify the RTC Clock source, as consequence RTC registers (including |
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122 | * the backup registers) and RCC_BDCR register are set to their reset values. |
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123 | * |
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124 | * @retval HAL status |
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125 | */ |
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126 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
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127 | { |
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128 | uint32_t tickstart = 0; |
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129 | uint32_t tmpreg0 = 0; |
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130 | uint32_t tmpreg1 = 0; |
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131 | uint32_t plli2sused = 0; |
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132 | uint32_t pllsaiused = 0; |
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133 | |
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134 | /* Check the parameters */ |
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135 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
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136 | |
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137 | /*----------------------------------- I2S configuration ----------------------------------*/ |
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138 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
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139 | { |
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140 | /* Check the parameters */ |
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141 | assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); |
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142 | |
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143 | /* Configure I2S Clock source */ |
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144 | __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); |
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145 | |
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146 | /* Enable the PLLI2S when it's used as clock source for I2S */ |
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147 | if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) |
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148 | { |
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149 | plli2sused = 1; |
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150 | } |
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151 | } |
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152 | |
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153 | /*------------------------------------ SAI1 configuration --------------------------------------*/ |
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154 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) |
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155 | { |
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156 | /* Check the parameters */ |
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157 | assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); |
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158 | |
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159 | /* Configure SAI1 Clock source */ |
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160 | __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); |
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161 | /* Enable the PLLI2S when it's used as clock source for SAI */ |
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162 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) |
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163 | { |
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164 | plli2sused = 1; |
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165 | } |
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166 | /* Enable the PLLSAI when it's used as clock source for SAI */ |
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167 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) |
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168 | { |
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169 | pllsaiused = 1; |
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170 | } |
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171 | } |
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172 | |
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173 | /*------------------------------------ SAI2 configuration --------------------------------------*/ |
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174 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) |
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175 | { |
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176 | /* Check the parameters */ |
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177 | assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); |
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178 | |
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179 | /* Configure SAI2 Clock source */ |
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180 | __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); |
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181 | |
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182 | /* Enable the PLLI2S when it's used as clock source for SAI */ |
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183 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) |
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184 | { |
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185 | plli2sused = 1; |
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186 | } |
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187 | /* Enable the PLLSAI when it's used as clock source for SAI */ |
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188 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) |
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189 | { |
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190 | pllsaiused = 1; |
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191 | } |
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192 | } |
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193 | |
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194 | /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ |
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195 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) |
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196 | { |
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197 | plli2sused = 1; |
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198 | } |
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199 | |
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200 | /*------------------------------------ RTC configuration --------------------------------------*/ |
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201 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
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202 | { |
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203 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
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204 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
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205 | { |
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206 | /* Enable Power Clock*/ |
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207 | __HAL_RCC_PWR_CLK_ENABLE(); |
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208 | |
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209 | /* Enable write access to Backup domain */ |
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210 | PWR->CR1 |= PWR_CR1_DBP; |
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211 | |
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212 | /* Get Start Tick*/ |
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213 | tickstart = HAL_GetTick(); |
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214 | |
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215 | /* Wait for Backup domain Write protection disable */ |
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216 | while((PWR->CR1 & PWR_CR1_DBP) == RESET) |
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217 | { |
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218 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
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219 | { |
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220 | return HAL_TIMEOUT; |
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221 | } |
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222 | } |
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223 | |
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224 | /* Store the content of BDCR register before the reset of Backup Domain */ |
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225 | tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
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226 | |
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227 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
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228 | __HAL_RCC_BACKUPRESET_FORCE(); |
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229 | __HAL_RCC_BACKUPRESET_RELEASE(); |
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230 | |
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231 | /* Restore the Content of BDCR register */ |
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232 | RCC->BDCR = tmpreg0; |
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233 | |
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234 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
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235 | if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY)) |
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236 | { |
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237 | /* Get Start Tick*/ |
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238 | tickstart = HAL_GetTick(); |
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239 | |
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240 | /* Wait till LSE is ready */ |
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241 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
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242 | { |
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243 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
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244 | { |
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245 | return HAL_TIMEOUT; |
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246 | } |
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247 | } |
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248 | } |
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249 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
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250 | } |
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251 | } |
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252 | |
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253 | /*------------------------------------ TIM configuration --------------------------------------*/ |
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254 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) |
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255 | { |
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256 | /* Check the parameters */ |
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257 | assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); |
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258 | |
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259 | /* Configure Timer Prescaler */ |
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260 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); |
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261 | } |
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262 | |
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263 | /*-------------------------------------- I2C1 Configuration -----------------------------------*/ |
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264 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
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265 | { |
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266 | /* Check the parameters */ |
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267 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
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268 | |
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269 | /* Configure the I2C1 clock source */ |
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270 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
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271 | } |
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272 | |
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273 | /*-------------------------------------- I2C2 Configuration -----------------------------------*/ |
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274 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) |
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275 | { |
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276 | /* Check the parameters */ |
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277 | assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); |
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278 | |
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279 | /* Configure the I2C2 clock source */ |
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280 | __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); |
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281 | } |
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282 | |
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283 | /*-------------------------------------- I2C3 Configuration -----------------------------------*/ |
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284 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) |
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285 | { |
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286 | /* Check the parameters */ |
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287 | assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); |
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288 | |
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289 | /* Configure the I2C3 clock source */ |
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290 | __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); |
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291 | } |
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292 | |
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293 | /*-------------------------------------- I2C4 Configuration -----------------------------------*/ |
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294 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) |
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295 | { |
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296 | /* Check the parameters */ |
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297 | assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); |
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298 | |
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299 | /* Configure the I2C4 clock source */ |
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300 | __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); |
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301 | } |
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302 | |
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303 | /*-------------------------------------- USART1 Configuration -----------------------------------*/ |
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304 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
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305 | { |
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306 | /* Check the parameters */ |
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307 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
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308 | |
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309 | /* Configure the USART1 clock source */ |
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310 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
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311 | } |
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312 | |
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313 | /*-------------------------------------- USART2 Configuration -----------------------------------*/ |
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314 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
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315 | { |
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316 | /* Check the parameters */ |
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317 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
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318 | |
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319 | /* Configure the USART2 clock source */ |
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320 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
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321 | } |
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322 | |
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323 | /*-------------------------------------- USART3 Configuration -----------------------------------*/ |
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324 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) |
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325 | { |
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326 | /* Check the parameters */ |
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327 | assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); |
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328 | |
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329 | /* Configure the USART3 clock source */ |
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330 | __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); |
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331 | } |
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332 | |
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333 | /*-------------------------------------- UART4 Configuration -----------------------------------*/ |
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334 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) |
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335 | { |
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336 | /* Check the parameters */ |
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337 | assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); |
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338 | |
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339 | /* Configure the UART4 clock source */ |
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340 | __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); |
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341 | } |
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342 | |
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343 | /*-------------------------------------- UART5 Configuration -----------------------------------*/ |
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344 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) |
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345 | { |
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346 | /* Check the parameters */ |
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347 | assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); |
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348 | |
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349 | /* Configure the UART5 clock source */ |
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350 | __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); |
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351 | } |
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352 | |
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353 | /*-------------------------------------- USART6 Configuration -----------------------------------*/ |
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354 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) |
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355 | { |
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356 | /* Check the parameters */ |
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357 | assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); |
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358 | |
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359 | /* Configure the USART6 clock source */ |
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360 | __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); |
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361 | } |
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362 | |
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363 | /*-------------------------------------- UART7 Configuration -----------------------------------*/ |
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364 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) |
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365 | { |
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366 | /* Check the parameters */ |
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367 | assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); |
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368 | |
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369 | /* Configure the UART7 clock source */ |
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370 | __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); |
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371 | } |
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372 | |
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373 | /*-------------------------------------- UART8 Configuration -----------------------------------*/ |
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374 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) |
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375 | { |
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376 | /* Check the parameters */ |
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377 | assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); |
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378 | |
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379 | /* Configure the UART8 clock source */ |
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380 | __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); |
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381 | } |
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382 | |
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383 | /*--------------------------------------- CEC Configuration -----------------------------------*/ |
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384 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) |
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385 | { |
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386 | /* Check the parameters */ |
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387 | assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); |
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388 | |
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389 | /* Configure the CEC clock source */ |
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390 | __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); |
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391 | } |
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392 | |
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393 | /*-------------------------------------- CK48 Configuration -----------------------------------*/ |
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394 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) |
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395 | { |
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396 | /* Check the parameters */ |
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397 | assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); |
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398 | |
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399 | /* Configure the CLK48 source */ |
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400 | __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); |
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401 | |
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402 | /* Enable the PLLSAI when it's used as clock source for CK48 */ |
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403 | if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) |
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404 | { |
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405 | pllsaiused = 1; |
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406 | } |
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407 | } |
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408 | |
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409 | /*-------------------------------------- LTDC Configuration -----------------------------------*/ |
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410 | #if defined(STM32F756xx) || defined(STM32F746xx) |
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411 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) |
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412 | { |
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413 | pllsaiused = 1; |
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414 | } |
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415 | #endif /* STM32F756xx || STM32F746xx */ |
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416 | /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ |
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417 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) |
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418 | { |
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419 | /* Check the parameters */ |
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420 | assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); |
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421 | |
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422 | /* Configure the LTPIM1 clock source */ |
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423 | __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); |
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424 | } |
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425 | |
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426 | /*------------------------------------- SDMMC Configuration ------------------------------------*/ |
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427 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) |
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428 | { |
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429 | /* Check the parameters */ |
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430 | assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); |
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431 | |
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432 | /* Configure the SDMMC1 clock source */ |
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433 | __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); |
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434 | } |
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435 | |
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436 | /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ |
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437 | /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ |
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438 | if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) |
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439 | { |
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440 | /* Disable the PLLI2S */ |
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441 | __HAL_RCC_PLLI2S_DISABLE(); |
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442 | |
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443 | /* Get Start Tick*/ |
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444 | tickstart = HAL_GetTick(); |
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445 | |
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446 | /* Wait till PLLI2S is disabled */ |
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447 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
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448 | { |
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449 | if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
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450 | { |
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451 | /* return in case of Timeout detected */ |
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452 | return HAL_TIMEOUT; |
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453 | } |
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454 | } |
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455 | |
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456 | /* check for common PLLI2S Parameters */ |
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457 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
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458 | |
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459 | /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ |
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460 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) |
---|
461 | { |
---|
462 | /* check for Parameters */ |
---|
463 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
---|
464 | |
---|
465 | /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ |
---|
466 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
---|
467 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
---|
468 | /* Configure the PLLI2S division factors */ |
---|
469 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ |
---|
470 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
---|
471 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); |
---|
472 | } |
---|
473 | |
---|
474 | /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ |
---|
475 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || |
---|
476 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) |
---|
477 | { |
---|
478 | /* Check for PLLI2S Parameters */ |
---|
479 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
---|
480 | /* Check for PLLI2S/DIVQ parameters */ |
---|
481 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); |
---|
482 | |
---|
483 | /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ |
---|
484 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
---|
485 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
---|
486 | /* Configure the PLLI2S division factors */ |
---|
487 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
---|
488 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
---|
489 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
---|
490 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); |
---|
491 | |
---|
492 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
---|
493 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); |
---|
494 | } |
---|
495 | |
---|
496 | /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ |
---|
497 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) |
---|
498 | { |
---|
499 | /* check for Parameters */ |
---|
500 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); |
---|
501 | |
---|
502 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ |
---|
503 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
---|
504 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
---|
505 | /* Configure the PLLI2S division factors */ |
---|
506 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ |
---|
507 | /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ |
---|
508 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); |
---|
509 | } |
---|
510 | |
---|
511 | /*----------------- In Case of PLLI2S is just selected -----------------*/ |
---|
512 | if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) |
---|
513 | { |
---|
514 | /* Check for Parameters */ |
---|
515 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
---|
516 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); |
---|
517 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
---|
518 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
---|
519 | |
---|
520 | /* Configure the PLLI2S division factors */ |
---|
521 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ |
---|
522 | /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ |
---|
523 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); |
---|
524 | } |
---|
525 | |
---|
526 | /* Enable the PLLI2S */ |
---|
527 | __HAL_RCC_PLLI2S_ENABLE(); |
---|
528 | |
---|
529 | /* Get Start Tick*/ |
---|
530 | tickstart = HAL_GetTick(); |
---|
531 | |
---|
532 | /* Wait till PLLI2S is ready */ |
---|
533 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
---|
534 | { |
---|
535 | if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
---|
536 | { |
---|
537 | /* return in case of Timeout detected */ |
---|
538 | return HAL_TIMEOUT; |
---|
539 | } |
---|
540 | } |
---|
541 | } |
---|
542 | |
---|
543 | /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ |
---|
544 | /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ |
---|
545 | if(pllsaiused == 1) |
---|
546 | { |
---|
547 | /* Disable PLLSAI Clock */ |
---|
548 | __HAL_RCC_PLLSAI_DISABLE(); |
---|
549 | |
---|
550 | /* Get Start Tick*/ |
---|
551 | tickstart = HAL_GetTick(); |
---|
552 | |
---|
553 | /* Wait till PLLSAI is disabled */ |
---|
554 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) |
---|
555 | { |
---|
556 | if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) |
---|
557 | { |
---|
558 | /* return in case of Timeout detected */ |
---|
559 | return HAL_TIMEOUT; |
---|
560 | } |
---|
561 | } |
---|
562 | |
---|
563 | /* Check the PLLSAI division factors */ |
---|
564 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); |
---|
565 | |
---|
566 | /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ |
---|
567 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || |
---|
568 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) |
---|
569 | { |
---|
570 | /* check for PLLSAIQ Parameter */ |
---|
571 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); |
---|
572 | /* check for PLLSAI/DIVQ Parameter */ |
---|
573 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); |
---|
574 | |
---|
575 | /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ |
---|
576 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
---|
577 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
---|
578 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
---|
579 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
---|
580 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
---|
581 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); |
---|
582 | |
---|
583 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
---|
584 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); |
---|
585 | } |
---|
586 | |
---|
587 | /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ |
---|
588 | /* In Case of PLLI2S is selected as source clock for CK48 */ |
---|
589 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) |
---|
590 | { |
---|
591 | /* check for Parameters */ |
---|
592 | assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); |
---|
593 | /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ |
---|
594 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
---|
595 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
---|
596 | |
---|
597 | /* Configure the PLLSAI division factors */ |
---|
598 | /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ |
---|
599 | /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ |
---|
600 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); |
---|
601 | } |
---|
602 | |
---|
603 | #if defined(STM32F756xx) || defined(STM32F746xx) |
---|
604 | /*---------------------------- LTDC configuration -------------------------------*/ |
---|
605 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) |
---|
606 | { |
---|
607 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); |
---|
608 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); |
---|
609 | |
---|
610 | /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ |
---|
611 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
---|
612 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
---|
613 | |
---|
614 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
---|
615 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
---|
616 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ |
---|
617 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); |
---|
618 | |
---|
619 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ |
---|
620 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); |
---|
621 | } |
---|
622 | #endif /* STM32F756xx || STM32F746xx */ |
---|
623 | |
---|
624 | /* Enable PLLSAI Clock */ |
---|
625 | __HAL_RCC_PLLSAI_ENABLE(); |
---|
626 | |
---|
627 | /* Get Start Tick*/ |
---|
628 | tickstart = HAL_GetTick(); |
---|
629 | |
---|
630 | /* Wait till PLLSAI is ready */ |
---|
631 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) |
---|
632 | { |
---|
633 | if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) |
---|
634 | { |
---|
635 | /* return in case of Timeout detected */ |
---|
636 | return HAL_TIMEOUT; |
---|
637 | } |
---|
638 | } |
---|
639 | } |
---|
640 | return HAL_OK; |
---|
641 | } |
---|
642 | |
---|
643 | /** |
---|
644 | * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal |
---|
645 | * RCC configuration registers. |
---|
646 | * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure |
---|
647 | * @retval None |
---|
648 | */ |
---|
649 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
---|
650 | { |
---|
651 | uint32_t tempreg = 0; |
---|
652 | |
---|
653 | /* Set all possible values for the extended clock type parameter------------*/ |
---|
654 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ |
---|
655 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ |
---|
656 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ |
---|
657 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ |
---|
658 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ |
---|
659 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ |
---|
660 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ |
---|
661 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ |
---|
662 | RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ |
---|
663 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ |
---|
664 | RCC_PERIPHCLK_CLK48; |
---|
665 | |
---|
666 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
---|
667 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
---|
668 | PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
---|
669 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
---|
670 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
---|
671 | |
---|
672 | /* Get the PLLSAI Clock configuration -----------------------------------------------*/ |
---|
673 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); |
---|
674 | PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
---|
675 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
---|
676 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
---|
677 | |
---|
678 | /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ |
---|
679 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ)); |
---|
680 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ)); |
---|
681 | PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR)); |
---|
682 | |
---|
683 | /* Get the SAI1 clock configuration ----------------------------------------------*/ |
---|
684 | PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); |
---|
685 | |
---|
686 | /* Get the SAI2 clock configuration ----------------------------------------------*/ |
---|
687 | PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); |
---|
688 | |
---|
689 | /* Get the I2S clock configuration ------------------------------------------*/ |
---|
690 | PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); |
---|
691 | |
---|
692 | /* Get the I2C1 clock configuration ------------------------------------------*/ |
---|
693 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
---|
694 | |
---|
695 | /* Get the I2C2 clock configuration ------------------------------------------*/ |
---|
696 | PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); |
---|
697 | |
---|
698 | /* Get the I2C3 clock configuration ------------------------------------------*/ |
---|
699 | PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); |
---|
700 | |
---|
701 | /* Get the I2C4 clock configuration ------------------------------------------*/ |
---|
702 | PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); |
---|
703 | |
---|
704 | /* Get the USART1 clock configuration ------------------------------------------*/ |
---|
705 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
---|
706 | |
---|
707 | /* Get the USART2 clock configuration ------------------------------------------*/ |
---|
708 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
---|
709 | |
---|
710 | /* Get the USART3 clock configuration ------------------------------------------*/ |
---|
711 | PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); |
---|
712 | |
---|
713 | /* Get the UART4 clock configuration ------------------------------------------*/ |
---|
714 | PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); |
---|
715 | |
---|
716 | /* Get the UART5 clock configuration ------------------------------------------*/ |
---|
717 | PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); |
---|
718 | |
---|
719 | /* Get the USART6 clock configuration ------------------------------------------*/ |
---|
720 | PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); |
---|
721 | |
---|
722 | /* Get the UART7 clock configuration ------------------------------------------*/ |
---|
723 | PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); |
---|
724 | |
---|
725 | /* Get the UART8 clock configuration ------------------------------------------*/ |
---|
726 | PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); |
---|
727 | |
---|
728 | /* Get the LPTIM1 clock configuration ------------------------------------------*/ |
---|
729 | PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); |
---|
730 | |
---|
731 | /* Get the CEC clock configuration -----------------------------------------------*/ |
---|
732 | PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); |
---|
733 | |
---|
734 | /* Get the CK48 clock configuration -----------------------------------------------*/ |
---|
735 | PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); |
---|
736 | |
---|
737 | /* Get the SDMMC clock configuration -----------------------------------------------*/ |
---|
738 | PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); |
---|
739 | |
---|
740 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
---|
741 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
---|
742 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
---|
743 | |
---|
744 | /* Get the TIM Prescaler configuration --------------------------------------------*/ |
---|
745 | if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) |
---|
746 | { |
---|
747 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; |
---|
748 | } |
---|
749 | else |
---|
750 | { |
---|
751 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; |
---|
752 | } |
---|
753 | } |
---|
754 | |
---|
755 | /** |
---|
756 | * @brief Return the peripheral clock frequency for a given peripheral(SAI..) |
---|
757 | * @note Return 0 if peripheral clock identifier not managed by this API |
---|
758 | * @param PeriphClk: Peripheral clock identifier |
---|
759 | * This parameter can be one of the following values: |
---|
760 | * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock |
---|
761 | * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock |
---|
762 | * @retval Frequency in KHz |
---|
763 | */ |
---|
764 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
---|
765 | { |
---|
766 | uint32_t tmpreg = 0; |
---|
767 | /* This variable used to store the SAI clock frequency (value in Hz) */ |
---|
768 | uint32_t frequency = 0; |
---|
769 | /* This variable used to store the VCO Input (value in Hz) */ |
---|
770 | uint32_t vcoinput = 0; |
---|
771 | /* This variable used to store the SAI clock source */ |
---|
772 | uint32_t saiclocksource = 0; |
---|
773 | if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2)) |
---|
774 | { |
---|
775 | saiclocksource = RCC->DCKCFGR1; |
---|
776 | saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL); |
---|
777 | switch (saiclocksource) |
---|
778 | { |
---|
779 | case 0: /* PLLSAI is the clock source for SAI*/ |
---|
780 | { |
---|
781 | /* Configure the PLLSAI division factor */ |
---|
782 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
---|
783 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
---|
784 | { |
---|
785 | /* In Case the PLL Source is HSI (Internal Clock) */ |
---|
786 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
---|
787 | } |
---|
788 | else |
---|
789 | { |
---|
790 | /* In Case the PLL Source is HSE (External Clock) */ |
---|
791 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
---|
792 | } |
---|
793 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
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794 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
---|
795 | tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; |
---|
796 | frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); |
---|
797 | |
---|
798 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
---|
799 | tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); |
---|
800 | frequency = frequency/(tmpreg); |
---|
801 | break; |
---|
802 | } |
---|
803 | case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/ |
---|
804 | case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/ |
---|
805 | { |
---|
806 | /* Configure the PLLI2S division factor */ |
---|
807 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
---|
808 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
---|
809 | { |
---|
810 | /* In Case the PLL Source is HSI (Internal Clock) */ |
---|
811 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
---|
812 | } |
---|
813 | else |
---|
814 | { |
---|
815 | /* In Case the PLL Source is HSE (External Clock) */ |
---|
816 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
---|
817 | } |
---|
818 | |
---|
819 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
---|
820 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
---|
821 | tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; |
---|
822 | frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); |
---|
823 | |
---|
824 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
---|
825 | tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); |
---|
826 | frequency = frequency/(tmpreg); |
---|
827 | break; |
---|
828 | } |
---|
829 | case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/ |
---|
830 | case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/ |
---|
831 | { |
---|
832 | frequency = EXTERNAL_CLOCK_VALUE; |
---|
833 | break; |
---|
834 | } |
---|
835 | default : |
---|
836 | { |
---|
837 | break; |
---|
838 | } |
---|
839 | } |
---|
840 | } |
---|
841 | return frequency; |
---|
842 | } |
---|
843 | |
---|
844 | /** |
---|
845 | * @} |
---|
846 | */ |
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847 | |
---|
848 | /** |
---|
849 | * @} |
---|
850 | */ |
---|
851 | |
---|
852 | #endif /* HAL_RCC_MODULE_ENABLED */ |
---|
853 | /** |
---|
854 | * @} |
---|
855 | */ |
---|
856 | |
---|
857 | /** |
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858 | * @} |
---|
859 | */ |
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860 | |
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861 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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