1 | /** |
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2 | ****************************************************************************** |
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3 | * @file stm32f7xx_hal_nor.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.0.1 |
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6 | * @date 25-June-2015 |
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7 | * @brief NOR HAL module driver. |
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8 | * This file provides a generic firmware to drive NOR memories mounted |
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9 | * as external device. |
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10 | * |
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11 | @verbatim |
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12 | ============================================================================== |
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13 | ##### How to use this driver ##### |
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14 | ============================================================================== |
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15 | [..] |
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16 | This driver is a generic layered driver which contains a set of APIs used to |
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17 | control NOR flash memories. It uses the FMC layer functions to interface |
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18 | with NOR devices. This driver is used as follows: |
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19 | |
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20 | (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() |
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21 | with control and timing parameters for both normal and extended mode. |
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22 | |
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23 | (+) Read NOR flash memory manufacturer code and device IDs using the function |
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24 | HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef |
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25 | structure declared by the function caller. |
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26 | |
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27 | (+) Access NOR flash memory by read/write data unit operations using the functions |
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28 | HAL_NOR_Read(), HAL_NOR_Program(). |
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29 | |
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30 | (+) Perform NOR flash erase block/chip operations using the functions |
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31 | HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). |
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32 | |
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33 | (+) Read the NOR flash CFI (common flash interface) IDs using the function |
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34 | HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef |
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35 | structure declared by the function caller. |
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36 | |
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37 | (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ |
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38 | HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation |
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39 | |
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40 | (+) You can monitor the NOR device HAL state by calling the function |
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41 | HAL_NOR_GetState() |
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42 | [..] |
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43 | (@) This driver is a set of generic APIs which handle standard NOR flash operations. |
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44 | If a NOR flash device contains different operations and/or implementations, |
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45 | it should be implemented separately. |
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46 | |
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47 | *** NOR HAL driver macros list *** |
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48 | ============================================= |
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49 | [..] |
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50 | Below the list of most used macros in NOR HAL driver. |
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51 | |
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52 | (+) NOR_WRITE : NOR memory write data to specified address |
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53 | |
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54 | @endverbatim |
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55 | ****************************************************************************** |
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56 | * @attention |
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57 | * |
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58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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59 | * |
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60 | * Redistribution and use in source and binary forms, with or without modification, |
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61 | * are permitted provided that the following conditions are met: |
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62 | * 1. Redistributions of source code must retain the above copyright notice, |
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63 | * this list of conditions and the following disclaimer. |
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64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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65 | * this list of conditions and the following disclaimer in the documentation |
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66 | * and/or other materials provided with the distribution. |
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67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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68 | * may be used to endorse or promote products derived from this software |
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69 | * without specific prior written permission. |
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70 | * |
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71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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81 | * |
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82 | ****************************************************************************** |
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83 | */ |
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84 | |
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85 | /* Includes ------------------------------------------------------------------*/ |
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86 | #include "stm32f7xx_hal.h" |
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87 | |
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88 | /** @addtogroup STM32F7xx_HAL_Driver |
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89 | * @{ |
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90 | */ |
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91 | |
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92 | /** @defgroup NOR NOR |
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93 | * @brief NOR driver modules |
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94 | * @{ |
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95 | */ |
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96 | #ifdef HAL_NOR_MODULE_ENABLED |
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97 | |
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98 | /* Private typedef -----------------------------------------------------------*/ |
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99 | /* Private define ------------------------------------------------------------*/ |
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100 | |
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101 | /** @defgroup NOR_Private_Defines NOR Private Defines |
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102 | * @{ |
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103 | */ |
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104 | |
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105 | /* Constants to define address to set to write a command */ |
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106 | #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 |
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107 | #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 |
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108 | #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA |
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109 | #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 |
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110 | #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 |
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111 | #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA |
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112 | #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 |
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113 | |
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114 | /* Constants to define data to program a command */ |
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115 | #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 |
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116 | #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA |
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117 | #define NOR_CMD_DATA_SECOND (uint16_t)0x0055 |
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118 | #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 |
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119 | #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 |
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120 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 |
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121 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA |
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122 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 |
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123 | #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 |
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124 | #define NOR_CMD_DATA_CFI (uint16_t)0x0098 |
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125 | |
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126 | #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 |
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127 | #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 |
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128 | #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 |
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129 | |
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130 | /* Mask on NOR STATUS REGISTER */ |
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131 | #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 |
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132 | #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 |
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133 | |
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134 | /** |
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135 | * @} |
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136 | */ |
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137 | |
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138 | /* Private macro -------------------------------------------------------------*/ |
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139 | /* Private variables ---------------------------------------------------------*/ |
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140 | /* Private functions ---------------------------------------------------------*/ |
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141 | /* Exported functions --------------------------------------------------------*/ |
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142 | /** @defgroup NOR_Exported_Functions NOR Exported Functions |
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143 | * @{ |
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144 | */ |
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145 | |
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146 | /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
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147 | * @brief Initialization and Configuration functions |
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148 | * |
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149 | @verbatim |
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150 | ============================================================================== |
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151 | ##### NOR Initialization and de_initialization functions ##### |
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152 | ============================================================================== |
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153 | [..] |
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154 | This section provides functions allowing to initialize/de-initialize |
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155 | the NOR memory |
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156 | |
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157 | @endverbatim |
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158 | * @{ |
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159 | */ |
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160 | |
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161 | /** |
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162 | * @brief Perform the NOR memory Initialization sequence |
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163 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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164 | * the configuration information for NOR module. |
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165 | * @param Timing: pointer to NOR control timing structure |
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166 | * @param ExtTiming: pointer to NOR extended mode timing structure |
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167 | * @retval HAL status |
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168 | */ |
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169 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) |
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170 | { |
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171 | /* Check the NOR handle parameter */ |
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172 | if(hnor == NULL) |
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173 | { |
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174 | return HAL_ERROR; |
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175 | } |
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176 | |
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177 | if(hnor->State == HAL_NOR_STATE_RESET) |
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178 | { |
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179 | /* Allocate lock resource and initialize it */ |
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180 | hnor->Lock = HAL_UNLOCKED; |
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181 | /* Initialize the low level hardware (MSP) */ |
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182 | HAL_NOR_MspInit(hnor); |
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183 | } |
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184 | |
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185 | /* Initialize NOR control Interface */ |
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186 | FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); |
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187 | |
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188 | /* Initialize NOR timing Interface */ |
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189 | FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); |
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190 | |
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191 | /* Initialize NOR extended mode timing Interface */ |
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192 | FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); |
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193 | |
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194 | /* Enable the NORSRAM device */ |
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195 | __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); |
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196 | |
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197 | /* Check the NOR controller state */ |
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198 | hnor->State = HAL_NOR_STATE_READY; |
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199 | |
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200 | return HAL_OK; |
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201 | } |
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202 | |
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203 | /** |
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204 | * @brief Perform NOR memory De-Initialization sequence |
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205 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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206 | * the configuration information for NOR module. |
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207 | * @retval HAL status |
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208 | */ |
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209 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) |
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210 | { |
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211 | /* De-Initialize the low level hardware (MSP) */ |
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212 | HAL_NOR_MspDeInit(hnor); |
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213 | |
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214 | /* Configure the NOR registers with their reset values */ |
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215 | FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); |
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216 | |
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217 | /* Update the NOR controller state */ |
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218 | hnor->State = HAL_NOR_STATE_RESET; |
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219 | |
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220 | /* Release Lock */ |
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221 | __HAL_UNLOCK(hnor); |
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222 | |
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223 | return HAL_OK; |
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224 | } |
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225 | |
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226 | /** |
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227 | * @brief NOR MSP Init |
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228 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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229 | * the configuration information for NOR module. |
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230 | * @retval None |
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231 | */ |
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232 | __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) |
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233 | { |
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234 | /* NOTE : This function Should not be modified, when the callback is needed, |
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235 | the HAL_NOR_MspInit could be implemented in the user file |
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236 | */ |
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237 | } |
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238 | |
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239 | /** |
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240 | * @brief NOR MSP DeInit |
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241 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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242 | * the configuration information for NOR module. |
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243 | * @retval None |
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244 | */ |
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245 | __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) |
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246 | { |
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247 | /* NOTE : This function Should not be modified, when the callback is needed, |
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248 | the HAL_NOR_MspDeInit could be implemented in the user file |
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249 | */ |
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250 | } |
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251 | |
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252 | /** |
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253 | * @brief NOR MSP Wait for Ready/Busy signal |
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254 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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255 | * the configuration information for NOR module. |
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256 | * @param Timeout: Maximum timeout value |
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257 | * @retval None |
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258 | */ |
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259 | __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) |
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260 | { |
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261 | /* NOTE : This function Should not be modified, when the callback is needed, |
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262 | the HAL_NOR_MspWait could be implemented in the user file |
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263 | */ |
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264 | } |
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265 | |
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266 | /** |
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267 | * @} |
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268 | */ |
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269 | |
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270 | /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions |
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271 | * @brief Input Output and memory control functions |
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272 | * |
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273 | @verbatim |
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274 | ============================================================================== |
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275 | ##### NOR Input and Output functions ##### |
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276 | ============================================================================== |
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277 | [..] |
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278 | This section provides functions allowing to use and control the NOR memory |
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279 | |
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280 | @endverbatim |
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281 | * @{ |
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282 | */ |
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283 | |
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284 | /** |
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285 | * @brief Read NOR flash IDs |
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286 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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287 | * the configuration information for NOR module. |
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288 | * @param pNOR_ID : pointer to NOR ID structure |
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289 | * @retval HAL status |
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290 | */ |
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291 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) |
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292 | { |
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293 | uint32_t deviceaddress = 0; |
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294 | |
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295 | /* Process Locked */ |
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296 | __HAL_LOCK(hnor); |
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297 | |
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298 | /* Check the NOR controller state */ |
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299 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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300 | { |
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301 | return HAL_BUSY; |
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302 | } |
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303 | |
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304 | /* Select the NOR device address */ |
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305 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
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306 | { |
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307 | deviceaddress = NOR_MEMORY_ADRESS1; |
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308 | } |
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309 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
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310 | { |
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311 | deviceaddress = NOR_MEMORY_ADRESS2; |
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312 | } |
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313 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
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314 | { |
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315 | deviceaddress = NOR_MEMORY_ADRESS3; |
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316 | } |
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317 | else /* FMC_NORSRAM_BANK4 */ |
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318 | { |
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319 | deviceaddress = NOR_MEMORY_ADRESS4; |
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320 | } |
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321 | |
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322 | /* Update the NOR controller state */ |
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323 | hnor->State = HAL_NOR_STATE_BUSY; |
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324 | |
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325 | /* Send read ID command */ |
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326 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
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327 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
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328 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); |
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329 | |
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330 | /* Read the NOR IDs */ |
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331 | pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS); |
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332 | pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR); |
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333 | pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR); |
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334 | pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR); |
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335 | |
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336 | /* Check the NOR controller state */ |
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337 | hnor->State = HAL_NOR_STATE_READY; |
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338 | |
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339 | /* Process unlocked */ |
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340 | __HAL_UNLOCK(hnor); |
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341 | |
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342 | return HAL_OK; |
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343 | } |
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344 | |
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345 | /** |
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346 | * @brief Returns the NOR memory to Read mode. |
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347 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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348 | * the configuration information for NOR module. |
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349 | * @retval HAL status |
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350 | */ |
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351 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) |
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352 | { |
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353 | uint32_t deviceaddress = 0; |
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354 | |
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355 | /* Process Locked */ |
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356 | __HAL_LOCK(hnor); |
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357 | |
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358 | /* Check the NOR controller state */ |
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359 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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360 | { |
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361 | return HAL_BUSY; |
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362 | } |
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363 | |
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364 | /* Select the NOR device address */ |
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365 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
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366 | { |
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367 | deviceaddress = NOR_MEMORY_ADRESS1; |
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368 | } |
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369 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
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370 | { |
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371 | deviceaddress = NOR_MEMORY_ADRESS2; |
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372 | } |
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373 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
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374 | { |
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375 | deviceaddress = NOR_MEMORY_ADRESS3; |
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376 | } |
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377 | else /* FMC_NORSRAM_BANK4 */ |
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378 | { |
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379 | deviceaddress = NOR_MEMORY_ADRESS4; |
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380 | } |
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381 | |
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382 | NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); |
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383 | |
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384 | /* Check the NOR controller state */ |
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385 | hnor->State = HAL_NOR_STATE_READY; |
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386 | |
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387 | /* Process unlocked */ |
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388 | __HAL_UNLOCK(hnor); |
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389 | |
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390 | return HAL_OK; |
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391 | } |
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392 | |
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393 | /** |
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394 | * @brief Read data from NOR memory |
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395 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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396 | * the configuration information for NOR module. |
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397 | * @param pAddress: pointer to Device address |
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398 | * @param pData : pointer to read data |
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399 | * @retval HAL status |
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400 | */ |
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401 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
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402 | { |
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403 | uint32_t deviceaddress = 0; |
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404 | |
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405 | /* Process Locked */ |
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406 | __HAL_LOCK(hnor); |
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407 | |
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408 | /* Check the NOR controller state */ |
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409 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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410 | { |
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411 | return HAL_BUSY; |
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412 | } |
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413 | |
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414 | /* Select the NOR device address */ |
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415 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
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416 | { |
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417 | deviceaddress = NOR_MEMORY_ADRESS1; |
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418 | } |
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419 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
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420 | { |
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421 | deviceaddress = NOR_MEMORY_ADRESS2; |
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422 | } |
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423 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
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424 | { |
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425 | deviceaddress = NOR_MEMORY_ADRESS3; |
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426 | } |
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427 | else /* FMC_NORSRAM_BANK4 */ |
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428 | { |
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429 | deviceaddress = NOR_MEMORY_ADRESS4; |
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430 | } |
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431 | |
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432 | /* Update the NOR controller state */ |
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433 | hnor->State = HAL_NOR_STATE_BUSY; |
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434 | |
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435 | /* Send read data command */ |
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436 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
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437 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
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438 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); |
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439 | |
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440 | /* Read the data */ |
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441 | *pData = *(__IO uint32_t *)(uint32_t)pAddress; |
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442 | |
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443 | /* Check the NOR controller state */ |
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444 | hnor->State = HAL_NOR_STATE_READY; |
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445 | |
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446 | /* Process unlocked */ |
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447 | __HAL_UNLOCK(hnor); |
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448 | |
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449 | return HAL_OK; |
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450 | } |
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451 | |
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452 | /** |
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453 | * @brief Program data to NOR memory |
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454 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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455 | * the configuration information for NOR module. |
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456 | * @param pAddress: Device address |
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457 | * @param pData : pointer to the data to write |
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458 | * @retval HAL status |
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459 | */ |
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460 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
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461 | { |
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462 | uint32_t deviceaddress = 0; |
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463 | |
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464 | /* Process Locked */ |
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465 | __HAL_LOCK(hnor); |
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466 | |
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467 | /* Check the NOR controller state */ |
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468 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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469 | { |
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470 | return HAL_BUSY; |
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471 | } |
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472 | |
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473 | /* Select the NOR device address */ |
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474 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
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475 | { |
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476 | deviceaddress = NOR_MEMORY_ADRESS1; |
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477 | } |
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478 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
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479 | { |
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480 | deviceaddress = NOR_MEMORY_ADRESS2; |
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481 | } |
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482 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
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483 | { |
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484 | deviceaddress = NOR_MEMORY_ADRESS3; |
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485 | } |
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486 | else /* FMC_NORSRAM_BANK4 */ |
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487 | { |
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488 | deviceaddress = NOR_MEMORY_ADRESS4; |
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489 | } |
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490 | |
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491 | /* Update the NOR controller state */ |
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492 | hnor->State = HAL_NOR_STATE_BUSY; |
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493 | |
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494 | /* Send program data command */ |
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495 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
---|
496 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
---|
497 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); |
---|
498 | |
---|
499 | /* Write the data */ |
---|
500 | NOR_WRITE(pAddress, *pData); |
---|
501 | |
---|
502 | /* Check the NOR controller state */ |
---|
503 | hnor->State = HAL_NOR_STATE_READY; |
---|
504 | |
---|
505 | /* Process unlocked */ |
---|
506 | __HAL_UNLOCK(hnor); |
---|
507 | |
---|
508 | return HAL_OK; |
---|
509 | } |
---|
510 | |
---|
511 | /** |
---|
512 | * @brief Reads a half-word buffer from the NOR memory. |
---|
513 | * @param hnor: pointer to the NOR handle |
---|
514 | * @param uwAddress: NOR memory internal address to read from. |
---|
515 | * @param pData: pointer to the buffer that receives the data read from the |
---|
516 | * NOR memory. |
---|
517 | * @param uwBufferSize : number of Half word to read. |
---|
518 | * @retval HAL status |
---|
519 | */ |
---|
520 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
---|
521 | { |
---|
522 | uint32_t deviceaddress = 0; |
---|
523 | |
---|
524 | /* Process Locked */ |
---|
525 | __HAL_LOCK(hnor); |
---|
526 | |
---|
527 | /* Check the NOR controller state */ |
---|
528 | if(hnor->State == HAL_NOR_STATE_BUSY) |
---|
529 | { |
---|
530 | return HAL_BUSY; |
---|
531 | } |
---|
532 | |
---|
533 | /* Select the NOR device address */ |
---|
534 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
---|
535 | { |
---|
536 | deviceaddress = NOR_MEMORY_ADRESS1; |
---|
537 | } |
---|
538 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
---|
539 | { |
---|
540 | deviceaddress = NOR_MEMORY_ADRESS2; |
---|
541 | } |
---|
542 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
---|
543 | { |
---|
544 | deviceaddress = NOR_MEMORY_ADRESS3; |
---|
545 | } |
---|
546 | else /* FMC_NORSRAM_BANK4 */ |
---|
547 | { |
---|
548 | deviceaddress = NOR_MEMORY_ADRESS4; |
---|
549 | } |
---|
550 | |
---|
551 | /* Update the NOR controller state */ |
---|
552 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
553 | |
---|
554 | /* Send read data command */ |
---|
555 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
---|
556 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
---|
557 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); |
---|
558 | |
---|
559 | /* Read buffer */ |
---|
560 | while( uwBufferSize > 0) |
---|
561 | { |
---|
562 | *pData++ = *(__IO uint16_t *)uwAddress; |
---|
563 | uwAddress += 2; |
---|
564 | uwBufferSize--; |
---|
565 | } |
---|
566 | |
---|
567 | /* Check the NOR controller state */ |
---|
568 | hnor->State = HAL_NOR_STATE_READY; |
---|
569 | |
---|
570 | /* Process unlocked */ |
---|
571 | __HAL_UNLOCK(hnor); |
---|
572 | |
---|
573 | return HAL_OK; |
---|
574 | } |
---|
575 | |
---|
576 | /** |
---|
577 | * @brief Writes a half-word buffer to the NOR memory. This function must be used |
---|
578 | only with S29GL128P NOR memory. |
---|
579 | * @param hnor: pointer to the NOR handle |
---|
580 | * @param uwAddress: NOR memory internal start write address |
---|
581 | * @param pData: pointer to source data buffer. |
---|
582 | * @param uwBufferSize: Size of the buffer to write |
---|
583 | * @retval HAL status |
---|
584 | */ |
---|
585 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
---|
586 | { |
---|
587 | uint16_t * p_currentaddress = (uint16_t *)NULL; |
---|
588 | uint16_t * p_endaddress = (uint16_t *)NULL; |
---|
589 | uint32_t lastloadedaddress = 0, deviceaddress = 0; |
---|
590 | |
---|
591 | /* Process Locked */ |
---|
592 | __HAL_LOCK(hnor); |
---|
593 | |
---|
594 | /* Check the NOR controller state */ |
---|
595 | if(hnor->State == HAL_NOR_STATE_BUSY) |
---|
596 | { |
---|
597 | return HAL_BUSY; |
---|
598 | } |
---|
599 | |
---|
600 | /* Select the NOR device address */ |
---|
601 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
---|
602 | { |
---|
603 | deviceaddress = NOR_MEMORY_ADRESS1; |
---|
604 | } |
---|
605 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
---|
606 | { |
---|
607 | deviceaddress = NOR_MEMORY_ADRESS2; |
---|
608 | } |
---|
609 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
---|
610 | { |
---|
611 | deviceaddress = NOR_MEMORY_ADRESS3; |
---|
612 | } |
---|
613 | else /* FMC_NORSRAM_BANK4 */ |
---|
614 | { |
---|
615 | deviceaddress = NOR_MEMORY_ADRESS4; |
---|
616 | } |
---|
617 | |
---|
618 | /* Update the NOR controller state */ |
---|
619 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
620 | |
---|
621 | /* Initialize variables */ |
---|
622 | p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); |
---|
623 | p_endaddress = p_currentaddress + (uwBufferSize-1); |
---|
624 | lastloadedaddress = (uint32_t)(uwAddress); |
---|
625 | |
---|
626 | /* Issue unlock command sequence */ |
---|
627 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
---|
628 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
---|
629 | |
---|
630 | /* Write Buffer Load Command */ |
---|
631 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); |
---|
632 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); |
---|
633 | |
---|
634 | /* Load Data into NOR Buffer */ |
---|
635 | while(p_currentaddress <= p_endaddress) |
---|
636 | { |
---|
637 | /* Store last loaded address & data value (for polling) */ |
---|
638 | lastloadedaddress = (uint32_t)p_currentaddress; |
---|
639 | |
---|
640 | NOR_WRITE(p_currentaddress, *pData++); |
---|
641 | |
---|
642 | p_currentaddress ++; |
---|
643 | } |
---|
644 | |
---|
645 | NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); |
---|
646 | |
---|
647 | /* Check the NOR controller state */ |
---|
648 | hnor->State = HAL_NOR_STATE_READY; |
---|
649 | |
---|
650 | /* Process unlocked */ |
---|
651 | __HAL_UNLOCK(hnor); |
---|
652 | |
---|
653 | return HAL_OK; |
---|
654 | |
---|
655 | } |
---|
656 | |
---|
657 | /** |
---|
658 | * @brief Erase the specified block of the NOR memory |
---|
659 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
660 | * the configuration information for NOR module. |
---|
661 | * @param BlockAddress : Block to erase address |
---|
662 | * @param Address: Device address |
---|
663 | * @retval HAL status |
---|
664 | */ |
---|
665 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) |
---|
666 | { |
---|
667 | uint32_t deviceaddress = 0; |
---|
668 | |
---|
669 | /* Process Locked */ |
---|
670 | __HAL_LOCK(hnor); |
---|
671 | |
---|
672 | /* Check the NOR controller state */ |
---|
673 | if(hnor->State == HAL_NOR_STATE_BUSY) |
---|
674 | { |
---|
675 | return HAL_BUSY; |
---|
676 | } |
---|
677 | |
---|
678 | /* Select the NOR device address */ |
---|
679 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
---|
680 | { |
---|
681 | deviceaddress = NOR_MEMORY_ADRESS1; |
---|
682 | } |
---|
683 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
---|
684 | { |
---|
685 | deviceaddress = NOR_MEMORY_ADRESS2; |
---|
686 | } |
---|
687 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
---|
688 | { |
---|
689 | deviceaddress = NOR_MEMORY_ADRESS3; |
---|
690 | } |
---|
691 | else /* FMC_NORSRAM_BANK4 */ |
---|
692 | { |
---|
693 | deviceaddress = NOR_MEMORY_ADRESS4; |
---|
694 | } |
---|
695 | |
---|
696 | /* Update the NOR controller state */ |
---|
697 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
698 | |
---|
699 | /* Send block erase command sequence */ |
---|
700 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
---|
701 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
---|
702 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
---|
703 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
---|
704 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
---|
705 | NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); |
---|
706 | |
---|
707 | /* Check the NOR memory status and update the controller state */ |
---|
708 | hnor->State = HAL_NOR_STATE_READY; |
---|
709 | |
---|
710 | /* Process unlocked */ |
---|
711 | __HAL_UNLOCK(hnor); |
---|
712 | |
---|
713 | return HAL_OK; |
---|
714 | |
---|
715 | } |
---|
716 | |
---|
717 | /** |
---|
718 | * @brief Erase the entire NOR chip. |
---|
719 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
720 | * the configuration information for NOR module. |
---|
721 | * @param Address : Device address |
---|
722 | * @retval HAL status |
---|
723 | */ |
---|
724 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) |
---|
725 | { |
---|
726 | uint32_t deviceaddress = 0; |
---|
727 | |
---|
728 | /* Process Locked */ |
---|
729 | __HAL_LOCK(hnor); |
---|
730 | |
---|
731 | /* Check the NOR controller state */ |
---|
732 | if(hnor->State == HAL_NOR_STATE_BUSY) |
---|
733 | { |
---|
734 | return HAL_BUSY; |
---|
735 | } |
---|
736 | |
---|
737 | /* Select the NOR device address */ |
---|
738 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
---|
739 | { |
---|
740 | deviceaddress = NOR_MEMORY_ADRESS1; |
---|
741 | } |
---|
742 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
---|
743 | { |
---|
744 | deviceaddress = NOR_MEMORY_ADRESS2; |
---|
745 | } |
---|
746 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
---|
747 | { |
---|
748 | deviceaddress = NOR_MEMORY_ADRESS3; |
---|
749 | } |
---|
750 | else /* FMC_NORSRAM_BANK4 */ |
---|
751 | { |
---|
752 | deviceaddress = NOR_MEMORY_ADRESS4; |
---|
753 | } |
---|
754 | |
---|
755 | /* Update the NOR controller state */ |
---|
756 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
757 | |
---|
758 | /* Send NOR chip erase command sequence */ |
---|
759 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
---|
760 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
---|
761 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
---|
762 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
---|
763 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
---|
764 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); |
---|
765 | |
---|
766 | /* Check the NOR memory status and update the controller state */ |
---|
767 | hnor->State = HAL_NOR_STATE_READY; |
---|
768 | |
---|
769 | /* Process unlocked */ |
---|
770 | __HAL_UNLOCK(hnor); |
---|
771 | |
---|
772 | return HAL_OK; |
---|
773 | } |
---|
774 | |
---|
775 | /** |
---|
776 | * @brief Read NOR flash CFI IDs |
---|
777 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
778 | * the configuration information for NOR module. |
---|
779 | * @param pNOR_CFI : pointer to NOR CFI IDs structure |
---|
780 | * @retval HAL status |
---|
781 | */ |
---|
782 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) |
---|
783 | { |
---|
784 | uint32_t deviceaddress = 0; |
---|
785 | |
---|
786 | /* Process Locked */ |
---|
787 | __HAL_LOCK(hnor); |
---|
788 | |
---|
789 | /* Check the NOR controller state */ |
---|
790 | if(hnor->State == HAL_NOR_STATE_BUSY) |
---|
791 | { |
---|
792 | return HAL_BUSY; |
---|
793 | } |
---|
794 | |
---|
795 | /* Select the NOR device address */ |
---|
796 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
---|
797 | { |
---|
798 | deviceaddress = NOR_MEMORY_ADRESS1; |
---|
799 | } |
---|
800 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
---|
801 | { |
---|
802 | deviceaddress = NOR_MEMORY_ADRESS2; |
---|
803 | } |
---|
804 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
---|
805 | { |
---|
806 | deviceaddress = NOR_MEMORY_ADRESS3; |
---|
807 | } |
---|
808 | else /* FMC_NORSRAM_BANK4 */ |
---|
809 | { |
---|
810 | deviceaddress = NOR_MEMORY_ADRESS4; |
---|
811 | } |
---|
812 | |
---|
813 | /* Update the NOR controller state */ |
---|
814 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
815 | |
---|
816 | /* Send read CFI query command */ |
---|
817 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); |
---|
818 | |
---|
819 | /* read the NOR CFI information */ |
---|
820 | pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS); |
---|
821 | pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS); |
---|
822 | pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS); |
---|
823 | pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS); |
---|
824 | |
---|
825 | /* Check the NOR controller state */ |
---|
826 | hnor->State = HAL_NOR_STATE_READY; |
---|
827 | |
---|
828 | /* Process unlocked */ |
---|
829 | __HAL_UNLOCK(hnor); |
---|
830 | |
---|
831 | return HAL_OK; |
---|
832 | } |
---|
833 | |
---|
834 | /** |
---|
835 | * @} |
---|
836 | */ |
---|
837 | |
---|
838 | /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions |
---|
839 | * @brief management functions |
---|
840 | * |
---|
841 | @verbatim |
---|
842 | ============================================================================== |
---|
843 | ##### NOR Control functions ##### |
---|
844 | ============================================================================== |
---|
845 | [..] |
---|
846 | This subsection provides a set of functions allowing to control dynamically |
---|
847 | the NOR interface. |
---|
848 | |
---|
849 | @endverbatim |
---|
850 | * @{ |
---|
851 | */ |
---|
852 | |
---|
853 | /** |
---|
854 | * @brief Enables dynamically NOR write operation. |
---|
855 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
856 | * the configuration information for NOR module. |
---|
857 | * @retval HAL status |
---|
858 | */ |
---|
859 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) |
---|
860 | { |
---|
861 | /* Process Locked */ |
---|
862 | __HAL_LOCK(hnor); |
---|
863 | |
---|
864 | /* Enable write operation */ |
---|
865 | FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); |
---|
866 | |
---|
867 | /* Update the NOR controller state */ |
---|
868 | hnor->State = HAL_NOR_STATE_READY; |
---|
869 | |
---|
870 | /* Process unlocked */ |
---|
871 | __HAL_UNLOCK(hnor); |
---|
872 | |
---|
873 | return HAL_OK; |
---|
874 | } |
---|
875 | |
---|
876 | /** |
---|
877 | * @brief Disables dynamically NOR write operation. |
---|
878 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
879 | * the configuration information for NOR module. |
---|
880 | * @retval HAL status |
---|
881 | */ |
---|
882 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) |
---|
883 | { |
---|
884 | /* Process Locked */ |
---|
885 | __HAL_LOCK(hnor); |
---|
886 | |
---|
887 | /* Update the SRAM controller state */ |
---|
888 | hnor->State = HAL_NOR_STATE_BUSY; |
---|
889 | |
---|
890 | /* Disable write operation */ |
---|
891 | FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); |
---|
892 | |
---|
893 | /* Update the NOR controller state */ |
---|
894 | hnor->State = HAL_NOR_STATE_PROTECTED; |
---|
895 | |
---|
896 | /* Process unlocked */ |
---|
897 | __HAL_UNLOCK(hnor); |
---|
898 | |
---|
899 | return HAL_OK; |
---|
900 | } |
---|
901 | |
---|
902 | /** |
---|
903 | * @} |
---|
904 | */ |
---|
905 | |
---|
906 | /** @defgroup NOR_Exported_Functions_Group4 NOR State functions |
---|
907 | * @brief Peripheral State functions |
---|
908 | * |
---|
909 | @verbatim |
---|
910 | ============================================================================== |
---|
911 | ##### NOR State functions ##### |
---|
912 | ============================================================================== |
---|
913 | [..] |
---|
914 | This subsection permits to get in run-time the status of the NOR controller |
---|
915 | and the data flow. |
---|
916 | |
---|
917 | @endverbatim |
---|
918 | * @{ |
---|
919 | */ |
---|
920 | |
---|
921 | /** |
---|
922 | * @brief return the NOR controller state |
---|
923 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
924 | * the configuration information for NOR module. |
---|
925 | * @retval NOR controller state |
---|
926 | */ |
---|
927 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) |
---|
928 | { |
---|
929 | return hnor->State; |
---|
930 | } |
---|
931 | |
---|
932 | /** |
---|
933 | * @brief Returns the NOR operation status. |
---|
934 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
---|
935 | * the configuration information for NOR module. |
---|
936 | * @param Address: Device address |
---|
937 | * @param Timeout: NOR programming Timeout |
---|
938 | * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR |
---|
939 | * or HAL_NOR_STATUS_TIMEOUT |
---|
940 | */ |
---|
941 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) |
---|
942 | { |
---|
943 | HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; |
---|
944 | uint16_t tmpSR1 = 0, tmpSR2 = 0; |
---|
945 | uint32_t tickstart = 0; |
---|
946 | |
---|
947 | /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ |
---|
948 | HAL_NOR_MspWait(hnor, Timeout); |
---|
949 | |
---|
950 | /* Get the NOR memory operation status -------------------------------------*/ |
---|
951 | |
---|
952 | /* Get tick */ |
---|
953 | tickstart = HAL_GetTick(); |
---|
954 | while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) |
---|
955 | { |
---|
956 | /* Check for the Timeout */ |
---|
957 | if(Timeout != HAL_MAX_DELAY) |
---|
958 | { |
---|
959 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
---|
960 | { |
---|
961 | status = HAL_NOR_STATUS_TIMEOUT; |
---|
962 | } |
---|
963 | } |
---|
964 | |
---|
965 | /* Read NOR status register (DQ6 and DQ5) */ |
---|
966 | tmpSR1 = *(__IO uint16_t *)Address; |
---|
967 | tmpSR2 = *(__IO uint16_t *)Address; |
---|
968 | |
---|
969 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ |
---|
970 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) |
---|
971 | { |
---|
972 | return HAL_NOR_STATUS_SUCCESS ; |
---|
973 | } |
---|
974 | |
---|
975 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
---|
976 | { |
---|
977 | status = HAL_NOR_STATUS_ONGOING; |
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978 | } |
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979 | |
---|
980 | tmpSR1 = *(__IO uint16_t *)Address; |
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981 | tmpSR2 = *(__IO uint16_t *)Address; |
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982 | |
---|
983 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ |
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984 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) |
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985 | { |
---|
986 | return HAL_NOR_STATUS_SUCCESS; |
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987 | } |
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988 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
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989 | { |
---|
990 | return HAL_NOR_STATUS_ERROR; |
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991 | } |
---|
992 | } |
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993 | |
---|
994 | /* Return the operation status */ |
---|
995 | return status; |
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996 | } |
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997 | |
---|
998 | /** |
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999 | * @} |
---|
1000 | */ |
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1001 | |
---|
1002 | /** |
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1003 | * @} |
---|
1004 | */ |
---|
1005 | #endif /* HAL_NOR_MODULE_ENABLED */ |
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1006 | /** |
---|
1007 | * @} |
---|
1008 | */ |
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1009 | |
---|
1010 | /** |
---|
1011 | * @} |
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1012 | */ |
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1013 | |
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1014 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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