1 | /** |
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2 | ****************************************************************************** |
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3 | * @file stm32f7xx_hal_nand.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.0.1 |
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6 | * @date 25-June-2015 |
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7 | * @brief NAND HAL module driver. |
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8 | * This file provides a generic firmware to drive NAND memories mounted |
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9 | * as external device. |
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10 | * |
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11 | @verbatim |
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12 | ============================================================================== |
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13 | ##### How to use this driver ##### |
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14 | ============================================================================== |
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15 | [..] |
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16 | This driver is a generic layered driver which contains a set of APIs used to |
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17 | control NAND flash memories. It uses the FMC/FSMC layer functions to interface |
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18 | with NAND devices. This driver is used as follows: |
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19 | |
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20 | (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() |
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21 | with control and timing parameters for both common and attribute spaces. |
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22 | |
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23 | (+) Read NAND flash memory maker and device IDs using the function |
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24 | HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef |
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25 | structure declared by the function caller. |
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26 | |
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27 | (+) Access NAND flash memory by read/write operations using the functions |
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28 | HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() |
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29 | to read/write page(s)/spare area(s). These functions use specific device |
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30 | information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef |
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31 | structure. The read/write address information is contained by the Nand_Address_Typedef |
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32 | structure passed as parameter. |
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33 | |
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34 | (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). |
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35 | |
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36 | (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). |
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37 | The erase block address information is contained in the Nand_Address_Typedef |
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38 | structure passed as parameter. |
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39 | |
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40 | (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). |
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41 | |
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42 | (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ |
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43 | HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction |
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44 | feature or the function HAL_NAND_GetECC() to get the ECC correction code. |
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45 | |
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46 | (+) You can monitor the NAND device HAL state by calling the function |
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47 | HAL_NAND_GetState() |
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48 | |
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49 | [..] |
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50 | (@) This driver is a set of generic APIs which handle standard NAND flash operations. |
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51 | If a NAND flash device contains different operations and/or implementations, |
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52 | it should be implemented separately. |
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53 | |
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54 | @endverbatim |
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55 | ****************************************************************************** |
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56 | * @attention |
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57 | * |
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58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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59 | * |
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60 | * Redistribution and use in source and binary forms, with or without modification, |
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61 | * are permitted provided that the following conditions are met: |
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62 | * 1. Redistributions of source code must retain the above copyright notice, |
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63 | * this list of conditions and the following disclaimer. |
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64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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65 | * this list of conditions and the following disclaimer in the documentation |
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66 | * and/or other materials provided with the distribution. |
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67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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68 | * may be used to endorse or promote products derived from this software |
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69 | * without specific prior written permission. |
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70 | * |
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71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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81 | * |
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82 | ****************************************************************************** |
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83 | */ |
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84 | |
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85 | /* Includes ------------------------------------------------------------------*/ |
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86 | #include "stm32f7xx_hal.h" |
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87 | |
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88 | /** @addtogroup STM32F7xx_HAL_Driver |
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89 | * @{ |
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90 | */ |
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91 | |
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92 | |
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93 | #ifdef HAL_NAND_MODULE_ENABLED |
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94 | |
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95 | /** @defgroup NAND NAND |
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96 | * @brief NAND HAL module driver |
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97 | * @{ |
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98 | */ |
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99 | |
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100 | /* Private typedef -----------------------------------------------------------*/ |
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101 | /* Private Constants ------------------------------------------------------------*/ |
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102 | /* Private macro -------------------------------------------------------------*/ |
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103 | /* Private variables ---------------------------------------------------------*/ |
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104 | /* Private function prototypes -----------------------------------------------*/ |
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105 | /* Exported functions ---------------------------------------------------------*/ |
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106 | |
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107 | /** @defgroup NAND_Exported_Functions NAND Exported Functions |
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108 | * @{ |
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109 | */ |
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110 | |
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111 | /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
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112 | * @brief Initialization and Configuration functions |
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113 | * |
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114 | @verbatim |
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115 | ============================================================================== |
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116 | ##### NAND Initialization and de-initialization functions ##### |
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117 | ============================================================================== |
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118 | [..] |
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119 | This section provides functions allowing to initialize/de-initialize |
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120 | the NAND memory |
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121 | |
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122 | @endverbatim |
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123 | * @{ |
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124 | */ |
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125 | |
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126 | /** |
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127 | * @brief Perform NAND memory Initialization sequence |
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128 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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129 | * the configuration information for NAND module. |
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130 | * @param ComSpace_Timing: pointer to Common space timing structure |
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131 | * @param AttSpace_Timing: pointer to Attribute space timing structure |
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132 | * @retval HAL status |
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133 | */ |
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134 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) |
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135 | { |
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136 | /* Check the NAND handle state */ |
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137 | if(hnand == NULL) |
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138 | { |
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139 | return HAL_ERROR; |
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140 | } |
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141 | |
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142 | if(hnand->State == HAL_NAND_STATE_RESET) |
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143 | { |
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144 | /* Allocate lock resource and initialize it */ |
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145 | hnand->Lock = HAL_UNLOCKED; |
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146 | /* Initialize the low level hardware (MSP) */ |
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147 | HAL_NAND_MspInit(hnand); |
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148 | } |
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149 | |
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150 | /* Initialize NAND control Interface */ |
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151 | FMC_NAND_Init(hnand->Instance, &(hnand->Init)); |
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152 | |
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153 | /* Initialize NAND common space timing Interface */ |
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154 | FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); |
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155 | |
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156 | /* Initialize NAND attribute space timing Interface */ |
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157 | FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); |
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158 | |
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159 | /* Enable the NAND device */ |
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160 | __FMC_NAND_ENABLE(hnand->Instance); |
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161 | |
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162 | /* Update the NAND controller state */ |
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163 | hnand->State = HAL_NAND_STATE_READY; |
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164 | |
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165 | return HAL_OK; |
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166 | } |
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167 | |
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168 | /** |
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169 | * @brief Perform NAND memory De-Initialization sequence |
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170 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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171 | * the configuration information for NAND module. |
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172 | * @retval HAL status |
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173 | */ |
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174 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) |
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175 | { |
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176 | /* Initialize the low level hardware (MSP) */ |
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177 | HAL_NAND_MspDeInit(hnand); |
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178 | |
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179 | /* Configure the NAND registers with their reset values */ |
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180 | FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); |
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181 | |
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182 | /* Reset the NAND controller state */ |
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183 | hnand->State = HAL_NAND_STATE_RESET; |
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184 | |
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185 | /* Release Lock */ |
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186 | __HAL_UNLOCK(hnand); |
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187 | |
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188 | return HAL_OK; |
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189 | } |
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190 | |
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191 | /** |
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192 | * @brief NAND MSP Init |
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193 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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194 | * the configuration information for NAND module. |
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195 | * @retval None |
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196 | */ |
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197 | __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) |
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198 | { |
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199 | /* NOTE : This function Should not be modified, when the callback is needed, |
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200 | the HAL_NAND_MspInit could be implemented in the user file |
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201 | */ |
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202 | } |
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203 | |
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204 | /** |
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205 | * @brief NAND MSP DeInit |
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206 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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207 | * the configuration information for NAND module. |
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208 | * @retval None |
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209 | */ |
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210 | __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) |
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211 | { |
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212 | /* NOTE : This function Should not be modified, when the callback is needed, |
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213 | the HAL_NAND_MspDeInit could be implemented in the user file |
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214 | */ |
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215 | } |
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216 | |
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217 | |
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218 | /** |
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219 | * @brief This function handles NAND device interrupt request. |
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220 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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221 | * the configuration information for NAND module. |
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222 | * @retval HAL status |
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223 | */ |
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224 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) |
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225 | { |
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226 | /* Check NAND interrupt Rising edge flag */ |
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227 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) |
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228 | { |
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229 | /* NAND interrupt callback*/ |
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230 | HAL_NAND_ITCallback(hnand); |
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231 | |
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232 | /* Clear NAND interrupt Rising edge pending bit */ |
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233 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); |
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234 | } |
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235 | |
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236 | /* Check NAND interrupt Level flag */ |
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237 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) |
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238 | { |
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239 | /* NAND interrupt callback*/ |
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240 | HAL_NAND_ITCallback(hnand); |
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241 | |
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242 | /* Clear NAND interrupt Level pending bit */ |
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243 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); |
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244 | } |
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245 | |
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246 | /* Check NAND interrupt Falling edge flag */ |
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247 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) |
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248 | { |
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249 | /* NAND interrupt callback*/ |
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250 | HAL_NAND_ITCallback(hnand); |
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251 | |
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252 | /* Clear NAND interrupt Falling edge pending bit */ |
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253 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); |
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254 | } |
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255 | |
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256 | /* Check NAND interrupt FIFO empty flag */ |
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257 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) |
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258 | { |
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259 | /* NAND interrupt callback*/ |
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260 | HAL_NAND_ITCallback(hnand); |
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261 | |
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262 | /* Clear NAND interrupt FIFO empty pending bit */ |
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263 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); |
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264 | } |
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265 | |
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266 | } |
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267 | |
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268 | /** |
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269 | * @brief NAND interrupt feature callback |
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270 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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271 | * the configuration information for NAND module. |
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272 | * @retval None |
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273 | */ |
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274 | __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) |
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275 | { |
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276 | /* NOTE : This function Should not be modified, when the callback is needed, |
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277 | the HAL_NAND_ITCallback could be implemented in the user file |
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278 | */ |
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279 | } |
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280 | |
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281 | /** |
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282 | * @} |
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283 | */ |
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284 | |
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285 | /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions |
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286 | * @brief Input Output and memory control functions |
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287 | * |
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288 | @verbatim |
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289 | ============================================================================== |
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290 | ##### NAND Input and Output functions ##### |
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291 | ============================================================================== |
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292 | [..] |
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293 | This section provides functions allowing to use and control the NAND |
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294 | memory |
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295 | |
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296 | @endverbatim |
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297 | * @{ |
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298 | */ |
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299 | |
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300 | /** |
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301 | * @brief Read the NAND memory electronic signature |
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302 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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303 | * the configuration information for NAND module. |
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304 | * @param pNAND_ID: NAND ID structure |
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305 | * @retval HAL status |
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306 | */ |
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307 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) |
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308 | { |
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309 | __IO uint32_t data = 0; |
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310 | uint32_t deviceAddress = 0; |
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311 | |
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312 | /* Process Locked */ |
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313 | __HAL_LOCK(hnand); |
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314 | |
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315 | /* Check the NAND controller state */ |
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316 | if(hnand->State == HAL_NAND_STATE_BUSY) |
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317 | { |
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318 | return HAL_BUSY; |
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319 | } |
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320 | |
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321 | /* Identify the device address */ |
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322 | deviceAddress = NAND_DEVICE; |
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323 | |
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324 | /* Update the NAND controller state */ |
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325 | hnand->State = HAL_NAND_STATE_BUSY; |
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326 | |
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327 | /* Send Read ID command sequence */ |
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328 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; |
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329 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; |
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330 | |
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331 | /* Read the electronic signature from NAND flash */ |
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332 | data = *(__IO uint32_t *)deviceAddress; |
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333 | |
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334 | /* Return the data read */ |
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335 | pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); |
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336 | pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); |
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337 | pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); |
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338 | pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); |
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339 | |
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340 | /* Update the NAND controller state */ |
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341 | hnand->State = HAL_NAND_STATE_READY; |
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342 | |
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343 | /* Process unlocked */ |
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344 | __HAL_UNLOCK(hnand); |
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345 | |
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346 | return HAL_OK; |
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347 | } |
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348 | |
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349 | /** |
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350 | * @brief NAND memory reset |
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351 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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352 | * the configuration information for NAND module. |
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353 | * @retval HAL status |
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354 | */ |
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355 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) |
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356 | { |
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357 | uint32_t deviceAddress = 0; |
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358 | |
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359 | /* Process Locked */ |
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360 | __HAL_LOCK(hnand); |
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361 | |
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362 | /* Check the NAND controller state */ |
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363 | if(hnand->State == HAL_NAND_STATE_BUSY) |
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364 | { |
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365 | return HAL_BUSY; |
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366 | } |
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367 | |
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368 | /* Identify the device address */ |
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369 | deviceAddress = NAND_DEVICE; |
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370 | |
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371 | /* Update the NAND controller state */ |
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372 | hnand->State = HAL_NAND_STATE_BUSY; |
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373 | |
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374 | /* Send NAND reset command */ |
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375 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; |
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376 | |
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377 | |
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378 | /* Update the NAND controller state */ |
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379 | hnand->State = HAL_NAND_STATE_READY; |
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380 | |
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381 | /* Process unlocked */ |
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382 | __HAL_UNLOCK(hnand); |
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383 | |
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384 | return HAL_OK; |
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385 | |
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386 | } |
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387 | |
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388 | /** |
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389 | * @brief Read Page(s) from NAND memory block |
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390 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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391 | * the configuration information for NAND module. |
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392 | * @param pAddress : pointer to NAND address structure |
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393 | * @param pBuffer : pointer to destination read buffer |
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394 | * @param NumPageToRead : number of pages to read from block |
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395 | * @retval HAL status |
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396 | */ |
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397 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) |
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398 | { |
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399 | __IO uint32_t index = 0; |
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400 | uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; |
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401 | |
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402 | /* Process Locked */ |
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403 | __HAL_LOCK(hnand); |
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404 | |
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405 | /* Check the NAND controller state */ |
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406 | if(hnand->State == HAL_NAND_STATE_BUSY) |
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407 | { |
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408 | return HAL_BUSY; |
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409 | } |
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410 | |
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411 | /* Identify the device address */ |
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412 | deviceAddress = NAND_DEVICE; |
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413 | |
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414 | /* Update the NAND controller state */ |
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415 | hnand->State = HAL_NAND_STATE_BUSY; |
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416 | |
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417 | /* NAND raw address calculation */ |
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418 | nandAddress = ARRAY_ADDRESS(pAddress, hnand); |
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419 | |
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420 | /* Page(s) read loop */ |
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421 | while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) |
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422 | { |
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423 | /* update the buffer size */ |
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424 | size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); |
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425 | |
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426 | /* Send read page command sequence */ |
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427 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; |
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428 | |
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429 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; |
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430 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); |
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431 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); |
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432 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); |
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433 | |
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434 | /* for 512 and 1 GB devices, 4th cycle is required */ |
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435 | if(hnand->Info.BlockNbr >= 1024) |
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436 | { |
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437 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); |
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438 | } |
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439 | |
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440 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
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441 | |
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442 | /* Get Data into Buffer */ |
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443 | for(index = 0; index < size; index++) |
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444 | { |
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445 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; |
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446 | } |
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447 | |
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448 | /* Increment read pages number */ |
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449 | numPagesRead++; |
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450 | |
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451 | /* Decrement pages to read */ |
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452 | NumPageToRead--; |
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453 | |
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454 | /* Increment the NAND address */ |
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455 | nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); |
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456 | |
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457 | } |
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458 | |
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459 | /* Update the NAND controller state */ |
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460 | hnand->State = HAL_NAND_STATE_READY; |
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461 | |
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462 | /* Process unlocked */ |
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463 | __HAL_UNLOCK(hnand); |
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464 | |
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465 | return HAL_OK; |
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466 | |
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467 | } |
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468 | |
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469 | /** |
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470 | * @brief Write Page(s) to NAND memory block |
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471 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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472 | * the configuration information for NAND module. |
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473 | * @param pAddress : pointer to NAND address structure |
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474 | * @param pBuffer : pointer to source buffer to write |
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475 | * @param NumPageToWrite : number of pages to write to block |
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476 | * @retval HAL status |
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477 | */ |
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478 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) |
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479 | { |
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480 | __IO uint32_t index = 0; |
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481 | uint32_t tickstart = 0; |
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482 | uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; |
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483 | |
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484 | /* Process Locked */ |
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485 | __HAL_LOCK(hnand); |
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486 | |
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487 | /* Check the NAND controller state */ |
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488 | if(hnand->State == HAL_NAND_STATE_BUSY) |
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489 | { |
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490 | return HAL_BUSY; |
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491 | } |
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492 | |
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493 | /* Identify the device address */ |
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494 | deviceAddress = NAND_DEVICE; |
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495 | |
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496 | /* Update the NAND controller state */ |
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497 | hnand->State = HAL_NAND_STATE_BUSY; |
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498 | |
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499 | /* NAND raw address calculation */ |
---|
500 | nandAddress = ARRAY_ADDRESS(pAddress, hnand); |
---|
501 | |
---|
502 | /* Page(s) write loop */ |
---|
503 | while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) |
---|
504 | { |
---|
505 | /* update the buffer size */ |
---|
506 | size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); |
---|
507 | |
---|
508 | /* Send write page command sequence */ |
---|
509 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; |
---|
510 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; |
---|
511 | |
---|
512 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; |
---|
513 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); |
---|
514 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); |
---|
515 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); |
---|
516 | __DSB(); |
---|
517 | |
---|
518 | /* for 512 and 1 GB devices, 4th cycle is required */ |
---|
519 | if(hnand->Info.BlockNbr >= 1024) |
---|
520 | { |
---|
521 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); |
---|
522 | __DSB(); |
---|
523 | } |
---|
524 | |
---|
525 | /* Write data to memory */ |
---|
526 | for(index = 0; index < size; index++) |
---|
527 | { |
---|
528 | *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; |
---|
529 | __DSB(); |
---|
530 | } |
---|
531 | |
---|
532 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
---|
533 | |
---|
534 | /* Read status until NAND is ready */ |
---|
535 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
---|
536 | { |
---|
537 | /* Get tick */ |
---|
538 | tickstart = HAL_GetTick(); |
---|
539 | |
---|
540 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
---|
541 | { |
---|
542 | return HAL_TIMEOUT; |
---|
543 | } |
---|
544 | } |
---|
545 | |
---|
546 | /* Increment written pages number */ |
---|
547 | numPagesWritten++; |
---|
548 | |
---|
549 | /* Decrement pages to write */ |
---|
550 | NumPageToWrite--; |
---|
551 | |
---|
552 | /* Increment the NAND address */ |
---|
553 | nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); |
---|
554 | } |
---|
555 | |
---|
556 | /* Update the NAND controller state */ |
---|
557 | hnand->State = HAL_NAND_STATE_READY; |
---|
558 | |
---|
559 | /* Process unlocked */ |
---|
560 | __HAL_UNLOCK(hnand); |
---|
561 | |
---|
562 | return HAL_OK; |
---|
563 | } |
---|
564 | |
---|
565 | /** |
---|
566 | * @brief Read Spare area(s) from NAND memory |
---|
567 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
568 | * the configuration information for NAND module. |
---|
569 | * @param pAddress : pointer to NAND address structure |
---|
570 | * @param pBuffer: pointer to source buffer to write |
---|
571 | * @param NumSpareAreaToRead: Number of spare area to read |
---|
572 | * @retval HAL status |
---|
573 | */ |
---|
574 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) |
---|
575 | { |
---|
576 | __IO uint32_t index = 0; |
---|
577 | uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; |
---|
578 | |
---|
579 | /* Process Locked */ |
---|
580 | __HAL_LOCK(hnand); |
---|
581 | |
---|
582 | /* Check the NAND controller state */ |
---|
583 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
584 | { |
---|
585 | return HAL_BUSY; |
---|
586 | } |
---|
587 | |
---|
588 | /* Identify the device address */ |
---|
589 | deviceAddress = NAND_DEVICE; |
---|
590 | |
---|
591 | /* Update the NAND controller state */ |
---|
592 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
593 | |
---|
594 | /* NAND raw address calculation */ |
---|
595 | nandAddress = ARRAY_ADDRESS(pAddress, hnand); |
---|
596 | |
---|
597 | /* Spare area(s) read loop */ |
---|
598 | while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) |
---|
599 | { |
---|
600 | |
---|
601 | /* update the buffer size */ |
---|
602 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); |
---|
603 | |
---|
604 | /* Send read spare area command sequence */ |
---|
605 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; |
---|
606 | |
---|
607 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; |
---|
608 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); |
---|
609 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); |
---|
610 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); |
---|
611 | |
---|
612 | /* for 512 and 1 GB devices, 4th cycle is required */ |
---|
613 | if(hnand->Info.BlockNbr >= 1024) |
---|
614 | { |
---|
615 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); |
---|
616 | } |
---|
617 | |
---|
618 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
---|
619 | |
---|
620 | /* Get Data into Buffer */ |
---|
621 | for(index = 0; index < size; index++) |
---|
622 | { |
---|
623 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; |
---|
624 | } |
---|
625 | |
---|
626 | /* Increment read spare areas number */ |
---|
627 | numSpareAreaRead++; |
---|
628 | |
---|
629 | /* Decrement spare areas to read */ |
---|
630 | NumSpareAreaToRead--; |
---|
631 | |
---|
632 | /* Increment the NAND address */ |
---|
633 | nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); |
---|
634 | } |
---|
635 | |
---|
636 | /* Update the NAND controller state */ |
---|
637 | hnand->State = HAL_NAND_STATE_READY; |
---|
638 | |
---|
639 | /* Process unlocked */ |
---|
640 | __HAL_UNLOCK(hnand); |
---|
641 | |
---|
642 | return HAL_OK; |
---|
643 | } |
---|
644 | |
---|
645 | /** |
---|
646 | * @brief Write Spare area(s) to NAND memory |
---|
647 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
648 | * the configuration information for NAND module. |
---|
649 | * @param pAddress : pointer to NAND address structure |
---|
650 | * @param pBuffer : pointer to source buffer to write |
---|
651 | * @param NumSpareAreaTowrite : number of spare areas to write to block |
---|
652 | * @retval HAL status |
---|
653 | */ |
---|
654 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) |
---|
655 | { |
---|
656 | __IO uint32_t index = 0; |
---|
657 | uint32_t tickstart = 0; |
---|
658 | uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; |
---|
659 | |
---|
660 | /* Process Locked */ |
---|
661 | __HAL_LOCK(hnand); |
---|
662 | |
---|
663 | /* Check the NAND controller state */ |
---|
664 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
665 | { |
---|
666 | return HAL_BUSY; |
---|
667 | } |
---|
668 | |
---|
669 | /* Identify the device address */ |
---|
670 | deviceAddress = NAND_DEVICE; |
---|
671 | |
---|
672 | /* Update the FMC_NAND controller state */ |
---|
673 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
674 | |
---|
675 | /* NAND raw address calculation */ |
---|
676 | nandAddress = ARRAY_ADDRESS(pAddress, hnand); |
---|
677 | |
---|
678 | /* Spare area(s) write loop */ |
---|
679 | while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) |
---|
680 | { |
---|
681 | /* update the buffer size */ |
---|
682 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); |
---|
683 | |
---|
684 | /* Send write Spare area command sequence */ |
---|
685 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; |
---|
686 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; |
---|
687 | |
---|
688 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; |
---|
689 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); |
---|
690 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); |
---|
691 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); |
---|
692 | __DSB(); |
---|
693 | /* for 512 and 1 GB devices, 4th cycle is required */ |
---|
694 | if(hnand->Info.BlockNbr >= 1024) |
---|
695 | { |
---|
696 | *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); |
---|
697 | __DSB(); |
---|
698 | } |
---|
699 | |
---|
700 | /* Write data to memory */ |
---|
701 | for(index = 0; index < size; index++) |
---|
702 | { |
---|
703 | *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; |
---|
704 | __DSB(); |
---|
705 | } |
---|
706 | |
---|
707 | *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
---|
708 | __DSB(); |
---|
709 | |
---|
710 | /* Read status until NAND is ready */ |
---|
711 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
---|
712 | { |
---|
713 | /* Get tick */ |
---|
714 | tickstart = HAL_GetTick(); |
---|
715 | |
---|
716 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
---|
717 | { |
---|
718 | return HAL_TIMEOUT; |
---|
719 | } |
---|
720 | } |
---|
721 | |
---|
722 | /* Increment written spare areas number */ |
---|
723 | numSpareAreaWritten++; |
---|
724 | |
---|
725 | /* Decrement spare areas to write */ |
---|
726 | NumSpareAreaTowrite--; |
---|
727 | |
---|
728 | /* Increment the NAND address */ |
---|
729 | nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); |
---|
730 | } |
---|
731 | |
---|
732 | /* Update the NAND controller state */ |
---|
733 | hnand->State = HAL_NAND_STATE_READY; |
---|
734 | |
---|
735 | /* Process unlocked */ |
---|
736 | __HAL_UNLOCK(hnand); |
---|
737 | |
---|
738 | return HAL_OK; |
---|
739 | } |
---|
740 | |
---|
741 | /** |
---|
742 | * @brief NAND memory Block erase |
---|
743 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
744 | * the configuration information for NAND module. |
---|
745 | * @param pAddress : pointer to NAND address structure |
---|
746 | * @retval HAL status |
---|
747 | */ |
---|
748 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
---|
749 | { |
---|
750 | uint32_t DeviceAddress = 0; |
---|
751 | |
---|
752 | /* Process Locked */ |
---|
753 | __HAL_LOCK(hnand); |
---|
754 | |
---|
755 | /* Check the NAND controller state */ |
---|
756 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
757 | { |
---|
758 | return HAL_BUSY; |
---|
759 | } |
---|
760 | |
---|
761 | /* Identify the device address */ |
---|
762 | DeviceAddress = NAND_DEVICE; |
---|
763 | |
---|
764 | /* Update the NAND controller state */ |
---|
765 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
766 | |
---|
767 | /* Send Erase block command sequence */ |
---|
768 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; |
---|
769 | |
---|
770 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
---|
771 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
---|
772 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
---|
773 | __DSB(); |
---|
774 | |
---|
775 | /* for 512 and 1 GB devices, 4th cycle is required */ |
---|
776 | if(hnand->Info.BlockNbr >= 1024) |
---|
777 | { |
---|
778 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
---|
779 | __DSB(); |
---|
780 | } |
---|
781 | |
---|
782 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; |
---|
783 | __DSB(); |
---|
784 | |
---|
785 | /* Update the NAND controller state */ |
---|
786 | hnand->State = HAL_NAND_STATE_READY; |
---|
787 | |
---|
788 | /* Process unlocked */ |
---|
789 | __HAL_UNLOCK(hnand); |
---|
790 | |
---|
791 | return HAL_OK; |
---|
792 | } |
---|
793 | |
---|
794 | /** |
---|
795 | * @brief NAND memory read status |
---|
796 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
797 | * the configuration information for NAND module. |
---|
798 | * @retval NAND status |
---|
799 | */ |
---|
800 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) |
---|
801 | { |
---|
802 | uint32_t data = 0; |
---|
803 | uint32_t DeviceAddress = 0; |
---|
804 | |
---|
805 | /* Identify the device address */ |
---|
806 | DeviceAddress = NAND_DEVICE; |
---|
807 | |
---|
808 | /* Send Read status operation command */ |
---|
809 | *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; |
---|
810 | |
---|
811 | /* Read status register data */ |
---|
812 | data = *(__IO uint8_t *)DeviceAddress; |
---|
813 | |
---|
814 | /* Return the status */ |
---|
815 | if((data & NAND_ERROR) == NAND_ERROR) |
---|
816 | { |
---|
817 | return NAND_ERROR; |
---|
818 | } |
---|
819 | else if((data & NAND_READY) == NAND_READY) |
---|
820 | { |
---|
821 | return NAND_READY; |
---|
822 | } |
---|
823 | |
---|
824 | return NAND_BUSY; |
---|
825 | } |
---|
826 | |
---|
827 | /** |
---|
828 | * @brief Increment the NAND memory address |
---|
829 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
830 | * the configuration information for NAND module. |
---|
831 | * @param pAddress: pointer to NAND address structure |
---|
832 | * @retval The new status of the increment address operation. It can be: |
---|
833 | * - NAND_VALID_ADDRESS: When the new address is valid address |
---|
834 | * - NAND_INVALID_ADDRESS: When the new address is invalid address |
---|
835 | */ |
---|
836 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
---|
837 | { |
---|
838 | uint32_t status = NAND_VALID_ADDRESS; |
---|
839 | |
---|
840 | /* Increment page address */ |
---|
841 | pAddress->Page++; |
---|
842 | |
---|
843 | /* Check NAND address is valid */ |
---|
844 | if(pAddress->Page == hnand->Info.BlockSize) |
---|
845 | { |
---|
846 | pAddress->Page = 0; |
---|
847 | pAddress->Block++; |
---|
848 | |
---|
849 | if(pAddress->Block == hnand->Info.ZoneSize) |
---|
850 | { |
---|
851 | pAddress->Block = 0; |
---|
852 | pAddress->Zone++; |
---|
853 | |
---|
854 | if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) |
---|
855 | { |
---|
856 | status = NAND_INVALID_ADDRESS; |
---|
857 | } |
---|
858 | } |
---|
859 | } |
---|
860 | |
---|
861 | return (status); |
---|
862 | } |
---|
863 | /** |
---|
864 | * @} |
---|
865 | */ |
---|
866 | |
---|
867 | /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions |
---|
868 | * @brief management functions |
---|
869 | * |
---|
870 | @verbatim |
---|
871 | ============================================================================== |
---|
872 | ##### NAND Control functions ##### |
---|
873 | ============================================================================== |
---|
874 | [..] |
---|
875 | This subsection provides a set of functions allowing to control dynamically |
---|
876 | the NAND interface. |
---|
877 | |
---|
878 | @endverbatim |
---|
879 | * @{ |
---|
880 | */ |
---|
881 | |
---|
882 | |
---|
883 | /** |
---|
884 | * @brief Enables dynamically NAND ECC feature. |
---|
885 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
886 | * the configuration information for NAND module. |
---|
887 | * @retval HAL status |
---|
888 | */ |
---|
889 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) |
---|
890 | { |
---|
891 | /* Check the NAND controller state */ |
---|
892 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
893 | { |
---|
894 | return HAL_BUSY; |
---|
895 | } |
---|
896 | |
---|
897 | /* Update the NAND state */ |
---|
898 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
899 | |
---|
900 | /* Enable ECC feature */ |
---|
901 | FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); |
---|
902 | |
---|
903 | /* Update the NAND state */ |
---|
904 | hnand->State = HAL_NAND_STATE_READY; |
---|
905 | |
---|
906 | return HAL_OK; |
---|
907 | } |
---|
908 | |
---|
909 | /** |
---|
910 | * @brief Disables dynamically FMC_NAND ECC feature. |
---|
911 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
912 | * the configuration information for NAND module. |
---|
913 | * @retval HAL status |
---|
914 | */ |
---|
915 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) |
---|
916 | { |
---|
917 | /* Check the NAND controller state */ |
---|
918 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
919 | { |
---|
920 | return HAL_BUSY; |
---|
921 | } |
---|
922 | |
---|
923 | /* Update the NAND state */ |
---|
924 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
925 | |
---|
926 | /* Disable ECC feature */ |
---|
927 | FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); |
---|
928 | |
---|
929 | /* Update the NAND state */ |
---|
930 | hnand->State = HAL_NAND_STATE_READY; |
---|
931 | |
---|
932 | return HAL_OK; |
---|
933 | } |
---|
934 | |
---|
935 | /** |
---|
936 | * @brief Disables dynamically NAND ECC feature. |
---|
937 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
---|
938 | * the configuration information for NAND module. |
---|
939 | * @param ECCval: pointer to ECC value |
---|
940 | * @param Timeout: maximum timeout to wait |
---|
941 | * @retval HAL status |
---|
942 | */ |
---|
943 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) |
---|
944 | { |
---|
945 | HAL_StatusTypeDef status = HAL_OK; |
---|
946 | |
---|
947 | /* Check the NAND controller state */ |
---|
948 | if(hnand->State == HAL_NAND_STATE_BUSY) |
---|
949 | { |
---|
950 | return HAL_BUSY; |
---|
951 | } |
---|
952 | |
---|
953 | /* Update the NAND state */ |
---|
954 | hnand->State = HAL_NAND_STATE_BUSY; |
---|
955 | |
---|
956 | /* Get NAND ECC value */ |
---|
957 | status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); |
---|
958 | |
---|
959 | /* Update the NAND state */ |
---|
960 | hnand->State = HAL_NAND_STATE_READY; |
---|
961 | |
---|
962 | return status; |
---|
963 | } |
---|
964 | |
---|
965 | /** |
---|
966 | * @} |
---|
967 | */ |
---|
968 | |
---|
969 | |
---|
970 | /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions |
---|
971 | * @brief Peripheral State functions |
---|
972 | * |
---|
973 | @verbatim |
---|
974 | ============================================================================== |
---|
975 | ##### NAND State functions ##### |
---|
976 | ============================================================================== |
---|
977 | [..] |
---|
978 | This subsection permits to get in run-time the status of the NAND controller |
---|
979 | and the data flow. |
---|
980 | |
---|
981 | @endverbatim |
---|
982 | * @{ |
---|
983 | */ |
---|
984 | |
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985 | /** |
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986 | * @brief return the NAND state |
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987 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
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988 | * the configuration information for NAND module. |
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989 | * @retval HAL state |
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990 | */ |
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991 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) |
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992 | { |
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993 | return hnand->State; |
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994 | } |
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995 | |
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996 | /** |
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997 | * @} |
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998 | */ |
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999 | |
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1000 | /** |
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1001 | * @} |
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1002 | */ |
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1003 | |
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1004 | #endif /* HAL_NAND_MODULE_ENABLED */ |
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1005 | |
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1006 | /** |
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1007 | * @} |
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1008 | */ |
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1009 | |
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1010 | /** |
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1011 | * @} |
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1012 | */ |
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1013 | |
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1014 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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