1 | /** |
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2 | ****************************************************************************** |
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3 | * @file stm32f7xx_hal_dma.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.0.1 |
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6 | * @date 25-June-2015 |
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7 | * @brief DMA HAL module driver. |
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8 | * |
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9 | * This file provides firmware functions to manage the following |
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10 | * functionalities of the Direct Memory Access (DMA) peripheral: |
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11 | * + Initialization and de-initialization functions |
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12 | * + IO operation functions |
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13 | * + Peripheral State and errors functions |
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14 | @verbatim |
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15 | ============================================================================== |
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16 | ##### How to use this driver ##### |
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17 | ============================================================================== |
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18 | [..] |
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19 | (#) Enable and configure the peripheral to be connected to the DMA Stream |
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20 | (except for internal SRAM/FLASH memories: no initialization is |
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21 | necessary) please refer to Reference manual for connection between peripherals |
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22 | and DMA requests . |
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23 | |
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24 | (#) For a given Stream, program the required configuration through the following parameters: |
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25 | Transfer Direction, Source and Destination data formats, |
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26 | Circular, Normal or peripheral flow control mode, Stream Priority level, |
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27 | Source and Destination Increment mode, FIFO mode and its Threshold (if needed), |
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28 | Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. |
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29 | |
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30 | *** Polling mode IO operation *** |
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31 | ================================= |
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32 | [..] |
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33 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
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34 | address and destination address and the Length of data to be transferred |
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35 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
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36 | case a fixed Timeout can be configured by User depending from his application. |
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37 | |
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38 | *** Interrupt mode IO operation *** |
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39 | =================================== |
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40 | [..] |
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41 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
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42 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
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43 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
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44 | Source address and destination address and the Length of data to be transferred. In this |
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45 | case the DMA interrupt is configured |
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46 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
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47 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
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48 | add his own function by customization of function pointer XferCpltCallback and |
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49 | XferErrorCallback (i.e a member of DMA handle structure). |
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50 | [..] |
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51 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
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52 | detection. |
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53 | |
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54 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
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55 | |
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56 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
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57 | |
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58 | -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is |
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59 | possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set |
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60 | Half-Word data size for the peripheral to access its data register and set Word data size |
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61 | for the Memory to gain in access time. Each two half words will be packed and written in |
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62 | a single access to a Word in the Memory). |
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63 | |
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64 | -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source |
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65 | and Destination. In this case the Peripheral Data Size will be applied to both Source |
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66 | and Destination. |
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67 | |
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68 | *** DMA HAL driver macros list *** |
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69 | ============================================= |
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70 | [..] |
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71 | Below the list of most used macros in DMA HAL driver. |
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72 | |
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73 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. |
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74 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. |
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75 | (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. |
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76 | (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags. |
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77 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags. |
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78 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. |
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79 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. |
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80 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. |
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81 | |
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82 | [..] |
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83 | (@) You can refer to the DMA HAL driver header file for more useful macros |
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84 | |
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85 | @endverbatim |
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86 | ****************************************************************************** |
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87 | * @attention |
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88 | * |
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89 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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90 | * |
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91 | * Redistribution and use in source and binary forms, with or without modification, |
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92 | * are permitted provided that the following conditions are met: |
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93 | * 1. Redistributions of source code must retain the above copyright notice, |
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94 | * this list of conditions and the following disclaimer. |
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95 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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96 | * this list of conditions and the following disclaimer in the documentation |
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97 | * and/or other materials provided with the distribution. |
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98 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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99 | * may be used to endorse or promote products derived from this software |
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100 | * without specific prior written permission. |
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101 | * |
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102 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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103 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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104 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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105 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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106 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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107 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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108 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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109 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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110 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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111 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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112 | * |
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113 | ****************************************************************************** |
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114 | */ |
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115 | |
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116 | /* Includes ------------------------------------------------------------------*/ |
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117 | #include "stm32f7xx_hal.h" |
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118 | |
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119 | /** @addtogroup STM32F7xx_HAL_Driver |
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120 | * @{ |
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121 | */ |
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122 | |
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123 | /** @defgroup DMA DMA |
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124 | * @brief DMA HAL module driver |
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125 | * @{ |
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126 | */ |
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127 | |
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128 | #ifdef HAL_DMA_MODULE_ENABLED |
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129 | |
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130 | /* Private types -------------------------------------------------------------*/ |
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131 | /* Private variables ---------------------------------------------------------*/ |
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132 | /* Private constants ---------------------------------------------------------*/ |
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133 | /** @addtogroup DMA_Private_Constants |
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134 | * @{ |
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135 | */ |
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136 | #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ |
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137 | /** |
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138 | * @} |
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139 | */ |
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140 | /* Private macros ------------------------------------------------------------*/ |
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141 | /* Private functions ---------------------------------------------------------*/ |
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142 | /** @addtogroup DMA_Private_Functions |
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143 | * @{ |
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144 | */ |
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145 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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146 | /** |
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147 | * @brief Sets the DMA Transfer parameter. |
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148 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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149 | * the configuration information for the specified DMA Stream. |
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150 | * @param SrcAddress: The source memory Buffer address |
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151 | * @param DstAddress: The destination memory Buffer address |
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152 | * @param DataLength: The length of data to be transferred from source to destination |
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153 | * @retval HAL status |
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154 | */ |
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155 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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156 | { |
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157 | /* Clear DBM bit */ |
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158 | hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); |
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159 | |
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160 | /* Configure DMA Stream data length */ |
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161 | hdma->Instance->NDTR = DataLength; |
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162 | |
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163 | /* Peripheral to Memory */ |
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164 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
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165 | { |
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166 | /* Configure DMA Stream destination address */ |
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167 | hdma->Instance->PAR = DstAddress; |
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168 | |
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169 | /* Configure DMA Stream source address */ |
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170 | hdma->Instance->M0AR = SrcAddress; |
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171 | } |
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172 | /* Memory to Peripheral */ |
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173 | else |
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174 | { |
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175 | /* Configure DMA Stream source address */ |
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176 | hdma->Instance->PAR = SrcAddress; |
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177 | |
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178 | /* Configure DMA Stream destination address */ |
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179 | hdma->Instance->M0AR = DstAddress; |
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180 | } |
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181 | } |
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182 | |
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183 | /** |
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184 | * @} |
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185 | */ |
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186 | |
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187 | /* Exported functions ---------------------------------------------------------*/ |
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188 | /** @addtogroup DMA_Exported_Functions |
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189 | * @{ |
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190 | */ |
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191 | |
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192 | /** @addtogroup DMA_Exported_Functions_Group1 |
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193 | * |
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194 | @verbatim |
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195 | =============================================================================== |
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196 | ##### Initialization and de-initialization functions ##### |
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197 | =============================================================================== |
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198 | [..] |
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199 | This section provides functions allowing to initialize the DMA Stream source |
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200 | and destination addresses, incrementation and data sizes, transfer direction, |
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201 | circular/normal mode selection, memory-to-memory mode selection and Stream priority value. |
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202 | [..] |
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203 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
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204 | reference manual. |
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205 | |
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206 | @endverbatim |
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207 | * @{ |
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208 | */ |
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209 | |
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210 | /** |
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211 | * @brief Initializes the DMA according to the specified |
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212 | * parameters in the DMA_InitTypeDef and create the associated handle. |
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213 | * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
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214 | * the configuration information for the specified DMA Stream. |
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215 | * @retval HAL status |
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216 | */ |
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217 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
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218 | { |
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219 | uint32_t tmp = 0; |
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220 | |
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221 | /* Check the DMA peripheral state */ |
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222 | if(hdma == NULL) |
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223 | { |
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224 | return HAL_ERROR; |
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225 | } |
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226 | |
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227 | /* Check the parameters */ |
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228 | assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); |
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229 | assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); |
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230 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
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231 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
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232 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
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233 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
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234 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
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235 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
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236 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
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237 | assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); |
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238 | /* Check the memory burst, peripheral burst and FIFO threshold parameters only |
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239 | when FIFO mode is enabled */ |
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240 | if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) |
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241 | { |
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242 | assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); |
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243 | assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); |
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244 | assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); |
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245 | } |
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246 | |
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247 | /* Change DMA peripheral state */ |
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248 | hdma->State = HAL_DMA_STATE_BUSY; |
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249 | |
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250 | /* Get the CR register value */ |
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251 | tmp = hdma->Instance->CR; |
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252 | |
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253 | /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ |
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254 | tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ |
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255 | DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ |
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256 | DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ |
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257 | DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); |
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258 | |
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259 | /* Prepare the DMA Stream configuration */ |
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260 | tmp |= hdma->Init.Channel | hdma->Init.Direction | |
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261 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
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262 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
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263 | hdma->Init.Mode | hdma->Init.Priority; |
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264 | |
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265 | /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ |
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266 | if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) |
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267 | { |
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268 | /* Get memory burst and peripheral burst */ |
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269 | tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; |
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270 | } |
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271 | |
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272 | /* Write to DMA Stream CR register */ |
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273 | hdma->Instance->CR = tmp; |
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274 | |
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275 | /* Get the FCR register value */ |
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276 | tmp = hdma->Instance->FCR; |
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277 | |
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278 | /* Clear Direct mode and FIFO threshold bits */ |
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279 | tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); |
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280 | |
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281 | /* Prepare the DMA Stream FIFO configuration */ |
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282 | tmp |= hdma->Init.FIFOMode; |
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283 | |
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284 | /* the FIFO threshold is not used when the FIFO mode is disabled */ |
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285 | if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) |
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286 | { |
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287 | /* Get the FIFO threshold */ |
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288 | tmp |= hdma->Init.FIFOThreshold; |
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289 | } |
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290 | |
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291 | /* Write to DMA Stream FCR */ |
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292 | hdma->Instance->FCR = tmp; |
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293 | |
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294 | /* Initialize the error code */ |
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295 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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296 | |
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297 | /* Initialize the DMA state */ |
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298 | hdma->State = HAL_DMA_STATE_READY; |
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299 | |
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300 | return HAL_OK; |
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301 | } |
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302 | |
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303 | /** |
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304 | * @brief DeInitializes the DMA peripheral |
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305 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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306 | * the configuration information for the specified DMA Stream. |
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307 | * @retval HAL status |
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308 | */ |
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309 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
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310 | { |
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311 | /* Check the DMA peripheral state */ |
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312 | if(hdma == NULL) |
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313 | { |
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314 | return HAL_ERROR; |
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315 | } |
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316 | |
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317 | /* Check the DMA peripheral state */ |
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318 | if(hdma->State == HAL_DMA_STATE_BUSY) |
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319 | { |
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320 | return HAL_ERROR; |
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321 | } |
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322 | |
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323 | /* Disable the selected DMA Streamx */ |
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324 | __HAL_DMA_DISABLE(hdma); |
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325 | |
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326 | /* Reset DMA Streamx control register */ |
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327 | hdma->Instance->CR = 0; |
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328 | |
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329 | /* Reset DMA Streamx number of data to transfer register */ |
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330 | hdma->Instance->NDTR = 0; |
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331 | |
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332 | /* Reset DMA Streamx peripheral address register */ |
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333 | hdma->Instance->PAR = 0; |
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334 | |
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335 | /* Reset DMA Streamx memory 0 address register */ |
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336 | hdma->Instance->M0AR = 0; |
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337 | |
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338 | /* Reset DMA Streamx memory 1 address register */ |
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339 | hdma->Instance->M1AR = 0; |
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340 | |
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341 | /* Reset DMA Streamx FIFO control register */ |
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342 | hdma->Instance->FCR = (uint32_t)0x00000021; |
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343 | |
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344 | /* Clear all flags */ |
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345 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
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346 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
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347 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
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348 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
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349 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
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350 | |
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351 | /* Initialize the error code */ |
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352 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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353 | |
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354 | /* Initialize the DMA state */ |
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355 | hdma->State = HAL_DMA_STATE_RESET; |
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356 | |
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357 | /* Release Lock */ |
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358 | __HAL_UNLOCK(hdma); |
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359 | |
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360 | return HAL_OK; |
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361 | } |
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362 | |
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363 | /** |
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364 | * @} |
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365 | */ |
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366 | |
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367 | /** @addtogroup DMA_Exported_Functions_Group2 |
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368 | * |
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369 | @verbatim |
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370 | =============================================================================== |
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371 | ##### IO operation functions ##### |
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372 | =============================================================================== |
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373 | [..] This section provides functions allowing to: |
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374 | (+) Configure the source, destination address and data length and Start DMA transfer |
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375 | (+) Configure the source, destination address and data length and |
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376 | Start DMA transfer with interrupt |
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377 | (+) Abort DMA transfer |
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378 | (+) Poll for transfer complete |
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379 | (+) Handle DMA interrupt request |
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380 | |
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381 | @endverbatim |
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382 | * @{ |
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383 | */ |
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384 | |
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385 | /** |
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386 | * @brief Starts the DMA Transfer. |
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387 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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388 | * the configuration information for the specified DMA Stream. |
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389 | * @param SrcAddress: The source memory Buffer address |
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390 | * @param DstAddress: The destination memory Buffer address |
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391 | * @param DataLength: The length of data to be transferred from source to destination |
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392 | * @retval HAL status |
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393 | */ |
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394 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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395 | { |
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396 | /* Process locked */ |
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397 | __HAL_LOCK(hdma); |
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398 | |
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399 | /* Change DMA peripheral state */ |
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400 | hdma->State = HAL_DMA_STATE_BUSY; |
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401 | |
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402 | /* Check the parameters */ |
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403 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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404 | |
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405 | /* Disable the peripheral */ |
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406 | __HAL_DMA_DISABLE(hdma); |
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407 | |
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408 | /* Configure the source, destination address and the data length */ |
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409 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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410 | |
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411 | /* Enable the Peripheral */ |
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412 | __HAL_DMA_ENABLE(hdma); |
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413 | |
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414 | return HAL_OK; |
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415 | } |
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416 | |
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417 | /** |
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418 | * @brief Start the DMA Transfer with interrupt enabled. |
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419 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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420 | * the configuration information for the specified DMA Stream. |
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421 | * @param SrcAddress: The source memory Buffer address |
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422 | * @param DstAddress: The destination memory Buffer address |
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423 | * @param DataLength: The length of data to be transferred from source to destination |
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424 | * @retval HAL status |
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425 | */ |
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426 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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427 | { |
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428 | /* Process locked */ |
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429 | __HAL_LOCK(hdma); |
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430 | |
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431 | /* Change DMA peripheral state */ |
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432 | hdma->State = HAL_DMA_STATE_BUSY; |
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433 | |
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434 | /* Check the parameters */ |
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435 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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436 | |
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437 | /* Disable the peripheral */ |
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438 | __HAL_DMA_DISABLE(hdma); |
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439 | |
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440 | /* Configure the source, destination address and the data length */ |
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441 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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442 | |
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443 | /* Enable the transfer complete interrupt */ |
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444 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); |
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445 | |
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446 | /* Enable the Half transfer complete interrupt */ |
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447 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); |
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448 | |
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449 | /* Enable the transfer Error interrupt */ |
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450 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); |
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451 | |
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452 | /* Enable the FIFO Error interrupt */ |
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453 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); |
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454 | |
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455 | /* Enable the direct mode Error interrupt */ |
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456 | __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); |
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457 | |
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458 | /* Enable the Peripheral */ |
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459 | __HAL_DMA_ENABLE(hdma); |
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460 | |
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461 | return HAL_OK; |
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462 | } |
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463 | |
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464 | /** |
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465 | * @brief Aborts the DMA Transfer. |
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466 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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467 | * the configuration information for the specified DMA Stream. |
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468 | * |
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469 | * @note After disabling a DMA Stream, a check for wait until the DMA Stream is |
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470 | * effectively disabled is added. If a Stream is disabled |
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471 | * while a data transfer is ongoing, the current data will be transferred |
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472 | * and the Stream will be effectively disabled only after the transfer of |
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473 | * this single data is finished. |
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474 | * @retval HAL status |
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475 | */ |
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476 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
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477 | { |
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478 | uint32_t tickstart = 0; |
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479 | |
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480 | /* Disable the stream */ |
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481 | __HAL_DMA_DISABLE(hdma); |
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482 | |
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483 | /* Get tick */ |
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484 | tickstart = HAL_GetTick(); |
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485 | |
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486 | /* Check if the DMA Stream is effectively disabled */ |
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487 | while((hdma->Instance->CR & DMA_SxCR_EN) != 0) |
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488 | { |
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489 | /* Check for the Timeout */ |
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490 | if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) |
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491 | { |
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492 | /* Update error code */ |
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493 | hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; |
---|
494 | |
---|
495 | /* Process Unlocked */ |
---|
496 | __HAL_UNLOCK(hdma); |
---|
497 | |
---|
498 | /* Change the DMA state */ |
---|
499 | hdma->State = HAL_DMA_STATE_TIMEOUT; |
---|
500 | |
---|
501 | return HAL_TIMEOUT; |
---|
502 | } |
---|
503 | } |
---|
504 | /* Process Unlocked */ |
---|
505 | __HAL_UNLOCK(hdma); |
---|
506 | |
---|
507 | /* Change the DMA state*/ |
---|
508 | hdma->State = HAL_DMA_STATE_READY; |
---|
509 | |
---|
510 | return HAL_OK; |
---|
511 | } |
---|
512 | |
---|
513 | /** |
---|
514 | * @brief Polling for transfer complete. |
---|
515 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
---|
516 | * the configuration information for the specified DMA Stream. |
---|
517 | * @param CompleteLevel: Specifies the DMA level complete. |
---|
518 | * @param Timeout: Timeout duration. |
---|
519 | * @retval HAL status |
---|
520 | */ |
---|
521 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
---|
522 | { |
---|
523 | uint32_t temp, tmp, tmp1, tmp2; |
---|
524 | uint32_t tickstart = 0; |
---|
525 | |
---|
526 | /* Get the level transfer complete flag */ |
---|
527 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
---|
528 | { |
---|
529 | /* Transfer Complete flag */ |
---|
530 | temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
---|
531 | } |
---|
532 | else |
---|
533 | { |
---|
534 | /* Half Transfer Complete flag */ |
---|
535 | temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
---|
536 | } |
---|
537 | |
---|
538 | /* Get tick */ |
---|
539 | tickstart = HAL_GetTick(); |
---|
540 | |
---|
541 | while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
---|
542 | { |
---|
543 | tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
---|
544 | tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
---|
545 | tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
---|
546 | if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) |
---|
547 | { |
---|
548 | if(tmp != RESET) |
---|
549 | { |
---|
550 | /* Update error code */ |
---|
551 | hdma->ErrorCode |= HAL_DMA_ERROR_TE; |
---|
552 | |
---|
553 | /* Clear the transfer error flag */ |
---|
554 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
---|
555 | } |
---|
556 | if(tmp1 != RESET) |
---|
557 | { |
---|
558 | /* Update error code */ |
---|
559 | hdma->ErrorCode |= HAL_DMA_ERROR_FE; |
---|
560 | |
---|
561 | /* Clear the FIFO error flag */ |
---|
562 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
---|
563 | } |
---|
564 | if(tmp2 != RESET) |
---|
565 | { |
---|
566 | /* Update error code */ |
---|
567 | hdma->ErrorCode |= HAL_DMA_ERROR_DME; |
---|
568 | |
---|
569 | /* Clear the Direct Mode error flag */ |
---|
570 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
---|
571 | } |
---|
572 | /* Change the DMA state */ |
---|
573 | hdma->State= HAL_DMA_STATE_ERROR; |
---|
574 | |
---|
575 | /* Process Unlocked */ |
---|
576 | __HAL_UNLOCK(hdma); |
---|
577 | |
---|
578 | return HAL_ERROR; |
---|
579 | } |
---|
580 | /* Check for the Timeout */ |
---|
581 | if(Timeout != HAL_MAX_DELAY) |
---|
582 | { |
---|
583 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
---|
584 | { |
---|
585 | /* Update error code */ |
---|
586 | hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; |
---|
587 | |
---|
588 | /* Change the DMA state */ |
---|
589 | hdma->State = HAL_DMA_STATE_TIMEOUT; |
---|
590 | |
---|
591 | /* Process Unlocked */ |
---|
592 | __HAL_UNLOCK(hdma); |
---|
593 | |
---|
594 | return HAL_TIMEOUT; |
---|
595 | } |
---|
596 | } |
---|
597 | } |
---|
598 | |
---|
599 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
---|
600 | { |
---|
601 | /* Multi_Buffering mode enabled */ |
---|
602 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
---|
603 | { |
---|
604 | /* Clear the half transfer complete flag */ |
---|
605 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
606 | /* Clear the transfer complete flag */ |
---|
607 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
---|
608 | |
---|
609 | /* Current memory buffer used is Memory 0 */ |
---|
610 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
---|
611 | { |
---|
612 | /* Change DMA peripheral state */ |
---|
613 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
---|
614 | } |
---|
615 | /* Current memory buffer used is Memory 1 */ |
---|
616 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
---|
617 | { |
---|
618 | /* Change DMA peripheral state */ |
---|
619 | hdma->State = HAL_DMA_STATE_READY_MEM1; |
---|
620 | } |
---|
621 | } |
---|
622 | else |
---|
623 | { |
---|
624 | /* Clear the half transfer complete flag */ |
---|
625 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
626 | /* Clear the transfer complete flag */ |
---|
627 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
---|
628 | |
---|
629 | /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers |
---|
630 | are complete) */ |
---|
631 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
---|
632 | } |
---|
633 | /* Process Unlocked */ |
---|
634 | __HAL_UNLOCK(hdma); |
---|
635 | } |
---|
636 | else |
---|
637 | { |
---|
638 | /* Multi_Buffering mode enabled */ |
---|
639 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
---|
640 | { |
---|
641 | /* Clear the half transfer complete flag */ |
---|
642 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
643 | |
---|
644 | /* Current memory buffer used is Memory 0 */ |
---|
645 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
---|
646 | { |
---|
647 | /* Change DMA peripheral state */ |
---|
648 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
---|
649 | } |
---|
650 | /* Current memory buffer used is Memory 1 */ |
---|
651 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
---|
652 | { |
---|
653 | /* Change DMA peripheral state */ |
---|
654 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; |
---|
655 | } |
---|
656 | } |
---|
657 | else |
---|
658 | { |
---|
659 | /* Clear the half transfer complete flag */ |
---|
660 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
661 | |
---|
662 | /* Change DMA peripheral state */ |
---|
663 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
---|
664 | } |
---|
665 | } |
---|
666 | return HAL_OK; |
---|
667 | } |
---|
668 | |
---|
669 | /** |
---|
670 | * @brief Handles DMA interrupt request. |
---|
671 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
---|
672 | * the configuration information for the specified DMA Stream. |
---|
673 | * @retval None |
---|
674 | */ |
---|
675 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
---|
676 | { |
---|
677 | /* Transfer Error Interrupt management ***************************************/ |
---|
678 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) |
---|
679 | { |
---|
680 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) |
---|
681 | { |
---|
682 | /* Disable the transfer error interrupt */ |
---|
683 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); |
---|
684 | |
---|
685 | /* Clear the transfer error flag */ |
---|
686 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
---|
687 | |
---|
688 | /* Update error code */ |
---|
689 | hdma->ErrorCode |= HAL_DMA_ERROR_TE; |
---|
690 | |
---|
691 | /* Change the DMA state */ |
---|
692 | hdma->State = HAL_DMA_STATE_ERROR; |
---|
693 | |
---|
694 | /* Process Unlocked */ |
---|
695 | __HAL_UNLOCK(hdma); |
---|
696 | |
---|
697 | if(hdma->XferErrorCallback != NULL) |
---|
698 | { |
---|
699 | /* Transfer error callback */ |
---|
700 | hdma->XferErrorCallback(hdma); |
---|
701 | } |
---|
702 | } |
---|
703 | } |
---|
704 | /* FIFO Error Interrupt management ******************************************/ |
---|
705 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET) |
---|
706 | { |
---|
707 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) |
---|
708 | { |
---|
709 | /* Disable the FIFO Error interrupt */ |
---|
710 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); |
---|
711 | |
---|
712 | /* Clear the FIFO error flag */ |
---|
713 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); |
---|
714 | |
---|
715 | /* Update error code */ |
---|
716 | hdma->ErrorCode |= HAL_DMA_ERROR_FE; |
---|
717 | |
---|
718 | /* Change the DMA state */ |
---|
719 | hdma->State = HAL_DMA_STATE_ERROR; |
---|
720 | |
---|
721 | /* Process Unlocked */ |
---|
722 | __HAL_UNLOCK(hdma); |
---|
723 | |
---|
724 | if(hdma->XferErrorCallback != NULL) |
---|
725 | { |
---|
726 | /* Transfer error callback */ |
---|
727 | hdma->XferErrorCallback(hdma); |
---|
728 | } |
---|
729 | } |
---|
730 | } |
---|
731 | /* Direct Mode Error Interrupt management ***********************************/ |
---|
732 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET) |
---|
733 | { |
---|
734 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) |
---|
735 | { |
---|
736 | /* Disable the direct mode Error interrupt */ |
---|
737 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); |
---|
738 | |
---|
739 | /* Clear the direct mode error flag */ |
---|
740 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); |
---|
741 | |
---|
742 | /* Update error code */ |
---|
743 | hdma->ErrorCode |= HAL_DMA_ERROR_DME; |
---|
744 | |
---|
745 | /* Change the DMA state */ |
---|
746 | hdma->State = HAL_DMA_STATE_ERROR; |
---|
747 | |
---|
748 | /* Process Unlocked */ |
---|
749 | __HAL_UNLOCK(hdma); |
---|
750 | |
---|
751 | if(hdma->XferErrorCallback != NULL) |
---|
752 | { |
---|
753 | /* Transfer error callback */ |
---|
754 | hdma->XferErrorCallback(hdma); |
---|
755 | } |
---|
756 | } |
---|
757 | } |
---|
758 | /* Half Transfer Complete Interrupt management ******************************/ |
---|
759 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) |
---|
760 | { |
---|
761 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) |
---|
762 | { |
---|
763 | /* Multi_Buffering mode enabled */ |
---|
764 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
---|
765 | { |
---|
766 | /* Clear the half transfer complete flag */ |
---|
767 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
768 | |
---|
769 | /* Current memory buffer used is Memory 0 */ |
---|
770 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
---|
771 | { |
---|
772 | /* Change DMA peripheral state */ |
---|
773 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
---|
774 | } |
---|
775 | /* Current memory buffer used is Memory 1 */ |
---|
776 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
---|
777 | { |
---|
778 | /* Change DMA peripheral state */ |
---|
779 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; |
---|
780 | } |
---|
781 | } |
---|
782 | else |
---|
783 | { |
---|
784 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
---|
785 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
---|
786 | { |
---|
787 | /* Disable the half transfer interrupt */ |
---|
788 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
---|
789 | } |
---|
790 | /* Clear the half transfer complete flag */ |
---|
791 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
---|
792 | |
---|
793 | /* Change DMA peripheral state */ |
---|
794 | hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; |
---|
795 | } |
---|
796 | |
---|
797 | if(hdma->XferHalfCpltCallback != NULL) |
---|
798 | { |
---|
799 | /* Half transfer callback */ |
---|
800 | hdma->XferHalfCpltCallback(hdma); |
---|
801 | } |
---|
802 | } |
---|
803 | } |
---|
804 | /* Transfer Complete Interrupt management ***********************************/ |
---|
805 | if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) |
---|
806 | { |
---|
807 | if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) |
---|
808 | { |
---|
809 | if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) |
---|
810 | { |
---|
811 | /* Clear the transfer complete flag */ |
---|
812 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
---|
813 | |
---|
814 | /* Current memory buffer used is Memory 1 */ |
---|
815 | if((hdma->Instance->CR & DMA_SxCR_CT) == 0) |
---|
816 | { |
---|
817 | if(hdma->XferM1CpltCallback != NULL) |
---|
818 | { |
---|
819 | /* Transfer complete Callback for memory1 */ |
---|
820 | hdma->XferM1CpltCallback(hdma); |
---|
821 | } |
---|
822 | } |
---|
823 | /* Current memory buffer used is Memory 0 */ |
---|
824 | else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) |
---|
825 | { |
---|
826 | if(hdma->XferCpltCallback != NULL) |
---|
827 | { |
---|
828 | /* Transfer complete Callback for memory0 */ |
---|
829 | hdma->XferCpltCallback(hdma); |
---|
830 | } |
---|
831 | } |
---|
832 | } |
---|
833 | /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ |
---|
834 | else |
---|
835 | { |
---|
836 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
---|
837 | { |
---|
838 | /* Disable the transfer complete interrupt */ |
---|
839 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); |
---|
840 | } |
---|
841 | /* Clear the transfer complete flag */ |
---|
842 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
---|
843 | |
---|
844 | /* Update error code */ |
---|
845 | hdma->ErrorCode |= HAL_DMA_ERROR_NONE; |
---|
846 | |
---|
847 | /* Change the DMA state */ |
---|
848 | hdma->State = HAL_DMA_STATE_READY_MEM0; |
---|
849 | |
---|
850 | /* Process Unlocked */ |
---|
851 | __HAL_UNLOCK(hdma); |
---|
852 | |
---|
853 | if(hdma->XferCpltCallback != NULL) |
---|
854 | { |
---|
855 | /* Transfer complete callback */ |
---|
856 | hdma->XferCpltCallback(hdma); |
---|
857 | } |
---|
858 | } |
---|
859 | } |
---|
860 | } |
---|
861 | } |
---|
862 | |
---|
863 | /** |
---|
864 | * @} |
---|
865 | */ |
---|
866 | |
---|
867 | /** @addtogroup DMA_Exported_Functions_Group3 |
---|
868 | * |
---|
869 | @verbatim |
---|
870 | =============================================================================== |
---|
871 | ##### State and Errors functions ##### |
---|
872 | =============================================================================== |
---|
873 | [..] |
---|
874 | This subsection provides functions allowing to |
---|
875 | (+) Check the DMA state |
---|
876 | (+) Get error code |
---|
877 | |
---|
878 | @endverbatim |
---|
879 | * @{ |
---|
880 | */ |
---|
881 | |
---|
882 | /** |
---|
883 | * @brief Returns the DMA state. |
---|
884 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
---|
885 | * the configuration information for the specified DMA Stream. |
---|
886 | * @retval HAL state |
---|
887 | */ |
---|
888 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
---|
889 | { |
---|
890 | return hdma->State; |
---|
891 | } |
---|
892 | |
---|
893 | /** |
---|
894 | * @brief Return the DMA error code |
---|
895 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
---|
896 | * the configuration information for the specified DMA Stream. |
---|
897 | * @retval DMA Error Code |
---|
898 | */ |
---|
899 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
---|
900 | { |
---|
901 | return hdma->ErrorCode; |
---|
902 | } |
---|
903 | |
---|
904 | /** |
---|
905 | * @} |
---|
906 | */ |
---|
907 | |
---|
908 | /** |
---|
909 | * @} |
---|
910 | */ |
---|
911 | |
---|
912 | #endif /* HAL_DMA_MODULE_ENABLED */ |
---|
913 | /** |
---|
914 | * @} |
---|
915 | */ |
---|
916 | |
---|
917 | /** |
---|
918 | * @} |
---|
919 | */ |
---|
920 | |
---|
921 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
---|