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source: rtems/c/src/lib/libbsp/arm/stm32f7x/hal/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h @ c20847a5

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Last change on this file since c20847a5 was c20847a5, checked in by Isaac Gutekunst <isaac.gutekunst@…>, on 09/16/15 at 13:16:02

Add STM32F7 HAL Files

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+ STC32CubeF7 V1.1.0 from http://www.st.com/web/en/catalog/tools/PF261909

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Line
1	/**
2	******************************************************************************
3	* @file stm32f7xx_ll_sdmmc.h
4	* @author MCD Application Team
5	* @version V1.0.1
6	* @date 25-June-2015
7	* @brief Header file of SDMMC HAL module.
8	******************************************************************************
9	* @attention
10	*
11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12	*
13	* Redistribution and use in source and binary forms, with or without modification,
14	* are permitted provided that the following conditions are met:
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright notice,
18	* this list of conditions and the following disclaimer in the documentation
19	* and/or other materials provided with the distribution.
20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
21	* may be used to endorse or promote products derived from this software
22	* without specific prior written permission.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34	*
35	******************************************************************************
36	*/
37
38	/* Define to prevent recursive inclusion -------------------------------------*/
39	#ifndef __STM32F7xx_LL_SDMMC_H
40	#define __STM32F7xx_LL_SDMMC_H
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45
46	/* Includes ------------------------------------------------------------------*/
47	#include "stm32f7xx_hal_def.h"
48
49	/** @addtogroup STM32F7xx_Driver
50	* @{
51	*/
52
53	/** @addtogroup SDMMC_LL
54	* @{
55	*/
56
57	/* Exported types ------------------------------------------------------------*/
58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
59	* @{
60	*/
61
62	/**
63	* @brief SDMMC Configuration Structure definition
64	*/
65	typedef struct
66	{
67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
69
70	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
71	enabled or disabled.
72	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
73
74	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
75	disabled when the bus is idle.
76	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
77
78	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
79	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
80
81	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
82	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
83
84	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
85	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
86
87	}SDMMC_InitTypeDef;
88
89
90	/**
91	* @brief SDMMC Command Control structure
92	*/
93	typedef struct
94	{
95	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
96	to a card as part of a command message. If a command
97	contains an argument, it must be loaded into this register
98	before writing the command to the command register. */
99
100	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
101	Max_Data = 64 */
102
103	uint32_t Response; /*!< Specifies the SDMMC response type.
104	This parameter can be a value of @ref SDMMC_LL_Response_Type */
105
106	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
107	enabled or disabled.
108	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
109
110	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
111	is enabled or disabled.
112	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
113	}SDMMC_CmdInitTypeDef;
114
115
116	/**
117	* @brief SDMMC Data Control structure
118	*/
119	typedef struct
120	{
121	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
122
123	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
124
125	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
126	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
127
128	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
129	is a read or write.
130	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
131
132	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
133	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
134
135	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
136	is enabled or disabled.
137	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
138	}SDMMC_DataInitTypeDef;
139
140	/**
141	* @}
142	*/
143
144	/* Exported constants --------------------------------------------------------*/
145	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
146	* @{
147	*/
148
149	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
150	* @{
151	*/
152	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
153	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
154
155	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
156	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
157	/**
158	* @}
159	*/
160
161	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
162	* @{
163	*/
164	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
165	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
166
167	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
168	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
169	/**
170	* @}
171	*/
172
173	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
174	* @{
175	*/
176	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
177	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
178
179	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
180	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
181	/**
182	* @}
183	*/
184
185	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
186	* @{
187	*/
188	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)
189	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
190	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
191
192	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
193	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
194	((WIDE) == SDMMC_BUS_WIDE_8B))
195	/**
196	* @}
197	*/
198
199	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
200	* @{
201	*/
202	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
203	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
204
205	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
206	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
207	/**
208	* @}
209	*/
210
211	/** @defgroup SDMMC_LL_Clock_Division Clock Division
212	* @{
213	*/
214	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
215	/**
216	* @}
217	*/
218
219	/** @defgroup SDMMC_LL_Command_Index Command Index
220	* @{
221	*/
222	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
223	/**
224	* @}
225	*/
226
227	/** @defgroup SDMMC_LL_Response_Type Response Type
228	* @{
229	*/
230	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)
231	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
232	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
233
234	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
235	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
236	((RESPONSE) == SDMMC_RESPONSE_LONG))
237	/**
238	* @}
239	*/
240
241	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
242	* @{
243	*/
244	#define SDMMC_WAIT_NO ((uint32_t)0x00000000)
245	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
246	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
247
248	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
249	((WAIT) == SDMMC_WAIT_IT) \|\| \
250	((WAIT) == SDMMC_WAIT_PEND))
251	/**
252	* @}
253	*/
254
255	/** @defgroup SDMMC_LL_CPSM_State CPSM State
256	* @{
257	*/
258	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)
259	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
260
261	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
262	((CPSM) == SDMMC_CPSM_ENABLE))
263	/**
264	* @}
265	*/
266
267	/** @defgroup SDMMC_LL_Response_Registers Response Register
268	* @{
269	*/
270	#define SDMMC_RESP1 ((uint32_t)0x00000000)
271	#define SDMMC_RESP2 ((uint32_t)0x00000004)
272	#define SDMMC_RESP3 ((uint32_t)0x00000008)
273	#define SDMMC_RESP4 ((uint32_t)0x0000000C)
274
275	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
276	((RESP) == SDMMC_RESP2) \|\| \
277	((RESP) == SDMMC_RESP3) \|\| \
278	((RESP) == SDMMC_RESP4))
279	/**
280	* @}
281	*/
282
283	/** @defgroup SDMMC_LL_Data_Length Data Lenght
284	* @{
285	*/
286	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
287	/**
288	* @}
289	*/
290
291	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
292	* @{
293	*/
294	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
295	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
296	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
297	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
298	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
299	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
300	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
301	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
302	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
303	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
304	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
305	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
306	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
307	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
308	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
309
310	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
311	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
312	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
313	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
314	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
315	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
316	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
317	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
318	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
319	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
320	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
321	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
322	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
323	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
324	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
325	/**
326	* @}
327	*/
328
329	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
330	* @{
331	*/
332	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
333	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
334
335	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
336	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
337	/**
338	* @}
339	*/
340
341	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
342	* @{
343	*/
344	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
345	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
346
347	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
348	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
349	/**
350	* @}
351	*/
352
353	/** @defgroup SDMMC_LL_DPSM_State DPSM State
354	* @{
355	*/
356	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)
357	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
358
359	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
360	((DPSM) == SDMMC_DPSM_ENABLE))
361	/**
362	* @}
363	*/
364
365	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
366	* @{
367	*/
368	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
369	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
370
371	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
372	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
373	/**
374	* @}
375	*/
376
377	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
378	* @{
379	*/
380	#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
381	#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
382	#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
383	#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
384	#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
385	#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
386	#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
387	#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
388	#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
389	#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
390	#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
391	#define SDMMC_IT_TXACT SDMMC_STA_TXACT
392	#define SDMMC_IT_RXACT SDMMC_STA_RXACT
393	#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
394	#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
395	#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
396	#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
397	#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
398	#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
399	#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
400	#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
401	#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
402	/**
403	* @}
404	*/
405
406	/** @defgroup SDMMC_LL_Flags Flags
407	* @{
408	*/
409	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
410	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
411	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
412	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
413	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
414	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
415	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
416	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
417	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
418	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
419	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
420	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
421	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
422	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
423	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
424	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
425	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
426	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
427	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
428	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
429	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
430	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
431	/**
432	* @}
433	*/
434
435	/**
436	* @}
437	*/
438
439	/* Exported macro ------------------------------------------------------------*/
440	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
441	* @{
442	*/
443
444	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
445	* @brief SDMMC_LL registers bit address in the alias region
446	* @{
447	*/
448	/* ---------------------- SDMMC registers bit mask --------------------------- */
449	/* --- CLKCR Register ---*/
450	/* CLKCR register clear mask */
451	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
452	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
453	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
454
455	/* --- DCTRL Register ---*/
456	/* SDMMC DCTRL Clear Mask */
457	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
458	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
459
460	/* --- CMD Register ---*/
461	/* CMD Register clear mask */
462	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
463	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
464	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
465
466	/* SDMMC Initialization Frequency (400KHz max) */
467	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
468
469	/* SDMMC Data Transfer Frequency (25MHz max) */
470	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
471
472	/**
473	* @}
474	*/
475
476	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
477	* @brief macros to handle interrupts and specific clock configurations
478	* @{
479	*/
480
481	/**
482	* @brief Enable the SDMMC device.
483	* @param __INSTANCE__: SDMMC Instance
484	* @retval None
485	*/
486	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
487
488	/**
489	* @brief Disable the SDMMC device.
490	* @param __INSTANCE__: SDMMC Instance
491	* @retval None
492	*/
493	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
494
495	/**
496	* @brief Enable the SDMMC DMA transfer.
497	* @param __INSTANCE__: SDMMC Instance
498	* @retval None
499	*/
500	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
501	/**
502	* @brief Disable the SDMMC DMA transfer.
503	* @param __INSTANCE__: SDMMC Instance
504	* @retval None
505	*/
506	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
507
508	/**
509	* @brief Enable the SDMMC device interrupt.
510	* @param __INSTANCE__ : Pointer to SDMMC register base
511	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
512	* This parameter can be one or a combination of the following values:
513	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
514	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
515	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
516	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
517	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
518	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
519	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
520	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
521	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
522	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
523	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
524	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
525	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
526	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
527	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
528	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
529	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
530	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
531	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
532	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
533	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
534	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
535	* @retval None
536	*/
537	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
538
539	/**
540	* @brief Disable the SDMMC device interrupt.
541	* @param __INSTANCE__ : Pointer to SDMMC register base
542	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
543	* This parameter can be one or a combination of the following values:
544	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
545	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
546	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
547	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
548	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
549	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
550	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
551	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
552	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
553	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
554	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
555	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
556	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
557	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
558	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
559	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
560	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
561	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
562	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
563	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
564	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
565	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
566	* @retval None
567	*/
568	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
569
570	/**
571	* @brief Checks whether the specified SDMMC flag is set or not.
572	* @param __INSTANCE__ : Pointer to SDMMC register base
573	* @param __FLAG__: specifies the flag to check.
574	* This parameter can be one of the following values:
575	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
576	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
577	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
578	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
579	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
580	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
581	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
582	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
583	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
584	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
585	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
586	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
587	* @arg SDMMC_FLAG_RXACT: Data receive in progress
588	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
589	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
590	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
591	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
592	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
593	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
594	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
595	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
596	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
597	* @retval The new state of SDMMC_FLAG (SET or RESET).
598	*/
599	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
600
601
602	/**
603	* @brief Clears the SDMMC pending flags.
604	* @param __INSTANCE__ : Pointer to SDMMC register base
605	* @param __FLAG__: specifies the flag to clear.
606	* This parameter can be one or a combination of the following values:
607	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
608	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
609	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
610	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
611	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
612	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
613	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
614	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
615	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
616	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
617	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
618	* @retval None
619	*/
620	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
621
622	/**
623	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
624	* @param __INSTANCE__ : Pointer to SDMMC register base
625	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
626	* This parameter can be one of the following values:
627	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
628	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
629	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
630	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
631	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
632	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
633	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
634	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
635	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
636	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
637	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
638	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
639	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
640	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
641	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
642	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
643	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
644	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
645	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
646	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
647	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
648	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
649	* @retval The new state of SDMMC_IT (SET or RESET).
650	*/
651	#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
652
653	/**
654	* @brief Clears the SDMMC's interrupt pending bits.
655	* @param __INSTANCE__ : Pointer to SDMMC register base
656	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
657	* This parameter can be one or a combination of the following values:
658	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
659	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
660	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
661	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
662	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
663	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
664	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
665	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
666	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
667	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
668	* @retval None
669	*/
670	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
671
672	/**
673	* @brief Enable Start the SD I/O Read Wait operation.
674	* @param __INSTANCE__ : Pointer to SDMMC register base
675	* @retval None
676	*/
677	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
678
679	/**
680	* @brief Disable Start the SD I/O Read Wait operations.
681	* @param __INSTANCE__ : Pointer to SDMMC register base
682	* @retval None
683	*/
684	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
685
686	/**
687	* @brief Enable Start the SD I/O Read Wait operation.
688	* @param __INSTANCE__ : Pointer to SDMMC register base
689	* @retval None
690	*/
691	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
692
693	/**
694	* @brief Disable Stop the SD I/O Read Wait operations.
695	* @param __INSTANCE__ : Pointer to SDMMC register base
696	* @retval None
697	*/
698	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
699
700	/**
701	* @brief Enable the SD I/O Mode Operation.
702	* @param __INSTANCE__ : Pointer to SDMMC register base
703	* @retval None
704	*/
705	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
706
707	/**
708	* @brief Disable the SD I/O Mode Operation.
709	* @param __INSTANCE__ : Pointer to SDMMC register base
710	* @retval None
711	*/
712	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
713
714	/**
715	* @brief Enable the SD I/O Suspend command sending.
716	* @param __INSTANCE__ : Pointer to SDMMC register base
717	* @retval None
718	*/
719	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
720
721	/**
722	* @brief Disable the SD I/O Suspend command sending.
723	* @param __INSTANCE__ : Pointer to SDMMC register base
724	* @retval None
725	*/
726	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
727
728	/**
729	* @}
730	*/
731
732	/**
733	* @}
734	*/
735
736	/* Exported functions --------------------------------------------------------*/
737	/** @addtogroup SDMMC_LL_Exported_Functions
738	* @{
739	*/
740
741	/* Initialization/de-initialization functions **********************************/
742	/** @addtogroup HAL_SDMMC_LL_Group1
743	* @{
744	*/
745	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
746	/**
747	* @}
748	*/
749
750	/* I/O operation functions *****************************************************/
751	/** @addtogroup HAL_SDMMC_LL_Group2
752	* @{
753	*/
754	/* Blocking mode: Polling */
755	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
756	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
757	/**
758	* @}
759	*/
760
761	/* Peripheral Control functions ************************************************/
762	/** @addtogroup HAL_SDMMC_LL_Group3
763	* @{
764	*/
765	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
766	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
767	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
768
769	/* Command path state machine (CPSM) management functions */
770	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
771	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
772	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
773
774	/* Data path state machine (DPSM) management functions */
775	HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
776	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
777	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
778
779	/* SDMMC Cards mode management functions */
780	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
781
782	/**
783	* @}
784	*/
785
786	/**
787	* @}
788	*/
789
790	/**
791	* @}
792	*/
793
794	/**
795	* @}
796	*/
797
798	#ifdef __cplusplus
799	}
800	#endif
801
802	#endif /* __STM32F7xx_LL_SDMMC_H */
803
804	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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