1 | /** |
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2 | ****************************************************************************** |
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3 | * @file stm32f7xx_hal_tim.h |
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4 | * @author MCD Application Team |
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5 | * @version V1.0.1 |
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6 | * @date 25-June-2015 |
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7 | * @brief Header file of TIM HAL module. |
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8 | ****************************************************************************** |
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9 | * @attention |
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10 | * |
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11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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12 | * |
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13 | * Redistribution and use in source and binary forms, with or without modification, |
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14 | * are permitted provided that the following conditions are met: |
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15 | * 1. Redistributions of source code must retain the above copyright notice, |
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16 | * this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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18 | * this list of conditions and the following disclaimer in the documentation |
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19 | * and/or other materials provided with the distribution. |
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20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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21 | * may be used to endorse or promote products derived from this software |
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22 | * without specific prior written permission. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | ****************************************************************************** |
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36 | */ |
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37 | |
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38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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39 | #ifndef __STM32F7xx_HAL_TIM_H |
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40 | #define __STM32F7xx_HAL_TIM_H |
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41 | |
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42 | #ifdef __cplusplus |
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43 | extern "C" { |
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44 | #endif |
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45 | |
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46 | /* Includes ------------------------------------------------------------------*/ |
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47 | #include "stm32f7xx_hal_def.h" |
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48 | |
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49 | /** @addtogroup STM32F7xx_HAL_Driver |
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50 | * @{ |
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51 | */ |
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52 | |
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53 | /** @addtogroup TIM |
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54 | * @{ |
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55 | */ |
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56 | |
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57 | /* Exported types ------------------------------------------------------------*/ |
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58 | /** @defgroup TIM_Exported_Types TIM Exported Types |
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59 | * @{ |
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60 | */ |
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61 | |
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62 | /** |
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63 | * @brief TIM Time base Configuration Structure definition |
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64 | */ |
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65 | typedef struct |
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66 | { |
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67 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
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68 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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69 | |
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70 | uint32_t CounterMode; /*!< Specifies the counter mode. |
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71 | This parameter can be a value of @ref TIM_Counter_Mode */ |
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72 | |
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73 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
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74 | Auto-Reload Register at the next update event. |
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75 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
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76 | |
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77 | uint32_t ClockDivision; /*!< Specifies the clock division. |
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78 | This parameter can be a value of @ref TIM_ClockDivision */ |
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79 | |
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80 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
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81 | reaches zero, an update event is generated and counting restarts |
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82 | from the RCR value (N). |
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83 | This means in PWM mode that (N+1) corresponds to: |
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84 | - the number of PWM periods in edge-aligned mode |
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85 | - the number of half PWM period in center-aligned mode |
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86 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
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87 | @note This parameter is valid only for TIM1 and TIM8. */ |
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88 | } TIM_Base_InitTypeDef; |
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89 | |
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90 | /** |
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91 | * @brief TIM Output Compare Configuration Structure definition |
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92 | */ |
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93 | |
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94 | typedef struct |
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95 | { |
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96 | uint32_t OCMode; /*!< Specifies the TIM mode. |
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97 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
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98 | |
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99 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
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100 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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101 | |
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102 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
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103 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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104 | |
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105 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
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106 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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107 | @note This parameter is valid only for TIM1 and TIM8. */ |
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108 | |
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109 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
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110 | This parameter can be a value of @ref TIM_Output_Fast_State |
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111 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
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112 | |
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113 | |
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114 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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115 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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116 | @note This parameter is valid only for TIM1 and TIM8. */ |
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117 | |
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118 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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119 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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120 | @note This parameter is valid only for TIM1 and TIM8. */ |
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121 | } TIM_OC_InitTypeDef; |
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122 | |
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123 | /** |
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124 | * @brief TIM One Pulse Mode Configuration Structure definition |
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125 | */ |
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126 | typedef struct |
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127 | { |
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128 | uint32_t OCMode; /*!< Specifies the TIM mode. |
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129 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
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130 | |
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131 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
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132 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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133 | |
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134 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
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135 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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136 | |
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137 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
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138 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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139 | @note This parameter is valid only for TIM1 and TIM8. */ |
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140 | |
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141 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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142 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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143 | @note This parameter is valid only for TIM1 and TIM8. */ |
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144 | |
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145 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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146 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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147 | @note This parameter is valid only for TIM1 and TIM8. */ |
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148 | |
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149 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
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150 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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151 | |
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152 | uint32_t ICSelection; /*!< Specifies the input. |
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153 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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154 | |
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155 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
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156 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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157 | } TIM_OnePulse_InitTypeDef; |
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158 | |
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159 | |
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160 | /** |
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161 | * @brief TIM Input Capture Configuration Structure definition |
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162 | */ |
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163 | |
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164 | typedef struct |
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165 | { |
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166 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
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167 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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168 | |
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169 | uint32_t ICSelection; /*!< Specifies the input. |
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170 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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171 | |
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172 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
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173 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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174 | |
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175 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
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176 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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177 | } TIM_IC_InitTypeDef; |
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178 | |
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179 | /** |
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180 | * @brief TIM Encoder Configuration Structure definition |
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181 | */ |
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182 | |
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183 | typedef struct |
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184 | { |
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185 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
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186 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
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187 | |
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188 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
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189 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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190 | |
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191 | uint32_t IC1Selection; /*!< Specifies the input. |
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192 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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193 | |
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194 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
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195 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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196 | |
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197 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
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198 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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199 | |
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200 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
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201 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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202 | |
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203 | uint32_t IC2Selection; /*!< Specifies the input. |
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204 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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205 | |
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206 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
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207 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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208 | |
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209 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
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210 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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211 | } TIM_Encoder_InitTypeDef; |
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212 | |
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213 | /** |
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214 | * @brief Clock Configuration Handle Structure definition |
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215 | */ |
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216 | typedef struct |
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217 | { |
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218 | uint32_t ClockSource; /*!< TIM clock sources. |
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219 | This parameter can be a value of @ref TIM_Clock_Source */ |
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220 | uint32_t ClockPolarity; /*!< TIM clock polarity. |
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221 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
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222 | uint32_t ClockPrescaler; /*!< TIM clock prescaler. |
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223 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
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224 | uint32_t ClockFilter; /*!< TIM clock filter. |
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225 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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226 | }TIM_ClockConfigTypeDef; |
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227 | |
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228 | /** |
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229 | * @brief Clear Input Configuration Handle Structure definition |
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230 | */ |
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231 | typedef struct |
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232 | { |
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233 | uint32_t ClearInputState; /*!< TIM clear Input state. |
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234 | This parameter can be ENABLE or DISABLE */ |
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235 | uint32_t ClearInputSource; /*!< TIM clear Input sources. |
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236 | This parameter can be a value of @ref TIMEx_ClearInput_Source */ |
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237 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. |
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238 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
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239 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. |
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240 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
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241 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter. |
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242 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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243 | }TIM_ClearInputConfigTypeDef; |
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244 | |
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245 | /** |
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246 | * @brief TIM Slave configuration Structure definition |
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247 | */ |
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248 | typedef struct { |
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249 | uint32_t SlaveMode; /*!< Slave mode selection |
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250 | This parameter can be a value of @ref TIMEx_Slave_Mode */ |
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251 | uint32_t InputTrigger; /*!< Input Trigger source |
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252 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
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253 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
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254 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
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255 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
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256 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
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257 | uint32_t TriggerFilter; /*!< Input trigger filter |
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258 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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259 | |
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260 | }TIM_SlaveConfigTypeDef; |
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261 | |
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262 | /** |
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263 | * @brief HAL State structures definition |
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264 | */ |
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265 | typedef enum |
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266 | { |
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267 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
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268 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
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269 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
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270 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
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271 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
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272 | }HAL_TIM_StateTypeDef; |
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273 | |
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274 | /** |
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275 | * @brief HAL Active channel structures definition |
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276 | */ |
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277 | typedef enum |
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278 | { |
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279 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
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280 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
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281 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
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282 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
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283 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
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284 | }HAL_TIM_ActiveChannel; |
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285 | |
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286 | /** |
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287 | * @brief TIM Time Base Handle Structure definition |
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288 | */ |
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289 | typedef struct |
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290 | { |
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291 | TIM_TypeDef *Instance; /*!< Register base address */ |
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292 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
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293 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
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294 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
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295 | This array is accessed by a @ref DMA_Handle_index */ |
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296 | HAL_LockTypeDef Lock; /*!< Locking object */ |
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297 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
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298 | }TIM_HandleTypeDef; |
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299 | /** |
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300 | * @} |
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301 | */ |
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302 | |
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303 | /* Exported constants --------------------------------------------------------*/ |
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304 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
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305 | * @{ |
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306 | */ |
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307 | |
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308 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
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309 | * @{ |
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310 | */ |
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311 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
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312 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
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313 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
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314 | /** |
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315 | * @} |
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316 | */ |
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317 | |
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318 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
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319 | * @{ |
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320 | */ |
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321 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
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322 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
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323 | /** |
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324 | * @} |
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325 | */ |
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326 | |
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327 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
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328 | * @{ |
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329 | */ |
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330 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
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331 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
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332 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
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333 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
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334 | /** |
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335 | * @} |
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336 | */ |
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337 | |
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338 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
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339 | * @{ |
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340 | */ |
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341 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
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342 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
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343 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
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344 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
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345 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
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346 | /** |
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347 | * @} |
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348 | */ |
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349 | |
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350 | /** @defgroup TIM_ClockDivision TIM Clock Division |
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351 | * @{ |
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352 | */ |
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353 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
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354 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
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355 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
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356 | /** |
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357 | * @} |
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358 | */ |
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359 | |
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360 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
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361 | * @{ |
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362 | */ |
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363 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) |
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364 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
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365 | |
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366 | /** |
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367 | * @} |
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368 | */ |
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369 | |
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370 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
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371 | * @{ |
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372 | */ |
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373 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
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374 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
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375 | /** |
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376 | * @} |
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377 | */ |
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378 | |
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379 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
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380 | * @{ |
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381 | */ |
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382 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) |
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383 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
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384 | /** |
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385 | * @} |
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386 | */ |
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387 | |
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388 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
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389 | * @{ |
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390 | */ |
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391 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
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392 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
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393 | /** |
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394 | * @} |
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395 | */ |
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396 | |
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397 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
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398 | * @{ |
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399 | */ |
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400 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) |
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401 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
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402 | /** |
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403 | * @} |
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404 | */ |
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405 | |
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406 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
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407 | * @{ |
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408 | */ |
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409 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
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410 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
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411 | /** |
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412 | * @} |
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413 | */ |
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414 | |
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415 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State |
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416 | * @{ |
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417 | */ |
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418 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
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419 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) |
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420 | /** |
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421 | * @} |
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422 | */ |
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423 | |
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424 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
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425 | * @{ |
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426 | */ |
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427 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
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428 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
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429 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
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430 | /** |
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431 | * @} |
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432 | */ |
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433 | |
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434 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
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435 | * @{ |
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436 | */ |
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437 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
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438 | connected to IC1, IC2, IC3 or IC4, respectively */ |
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439 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
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440 | connected to IC2, IC1, IC4 or IC3, respectively */ |
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441 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
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442 | |
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443 | /** |
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444 | * @} |
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445 | */ |
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446 | |
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447 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
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448 | * @{ |
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449 | */ |
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450 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
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451 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
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452 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
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453 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
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454 | /** |
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455 | * @} |
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456 | */ |
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457 | |
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458 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
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459 | * @{ |
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460 | */ |
---|
461 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
---|
462 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
---|
463 | /** |
---|
464 | * @} |
---|
465 | */ |
---|
466 | |
---|
467 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
---|
468 | * @{ |
---|
469 | */ |
---|
470 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
---|
471 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
---|
472 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
---|
473 | |
---|
474 | /** |
---|
475 | * @} |
---|
476 | */ |
---|
477 | |
---|
478 | /** @defgroup TIM_Interrupt_definition TIM Interrupt definition |
---|
479 | * @{ |
---|
480 | */ |
---|
481 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
---|
482 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
---|
483 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
---|
484 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
---|
485 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
---|
486 | #define TIM_IT_COM (TIM_DIER_COMIE) |
---|
487 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
---|
488 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
---|
489 | /** |
---|
490 | * @} |
---|
491 | */ |
---|
492 | |
---|
493 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
---|
494 | * @{ |
---|
495 | */ |
---|
496 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
---|
497 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) |
---|
498 | /** |
---|
499 | * @} |
---|
500 | */ |
---|
501 | |
---|
502 | /** @defgroup TIM_DMA_sources TIM DMA sources |
---|
503 | * @{ |
---|
504 | */ |
---|
505 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
---|
506 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
---|
507 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
---|
508 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
---|
509 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
---|
510 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
---|
511 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
---|
512 | /** |
---|
513 | * @} |
---|
514 | */ |
---|
515 | |
---|
516 | /** @defgroup TIM_Event_Source TIM Event Source |
---|
517 | * @{ |
---|
518 | */ |
---|
519 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
---|
520 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
---|
521 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
---|
522 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
---|
523 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
---|
524 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG |
---|
525 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
---|
526 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
---|
527 | #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G |
---|
528 | /** |
---|
529 | * @} |
---|
530 | */ |
---|
531 | |
---|
532 | /** @defgroup TIM_Flag_definition TIM Flag definition |
---|
533 | * @{ |
---|
534 | */ |
---|
535 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
---|
536 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
---|
537 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
---|
538 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
---|
539 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
---|
540 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
---|
541 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
---|
542 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
---|
543 | #define TIM_FLAG_BREAK2 (TIM_SR_B2IF) |
---|
544 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
---|
545 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
---|
546 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
---|
547 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
---|
548 | /** |
---|
549 | * @} |
---|
550 | */ |
---|
551 | |
---|
552 | /** @defgroup TIM_Clock_Source TIM Clock Source |
---|
553 | * @{ |
---|
554 | */ |
---|
555 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
---|
556 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
---|
557 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
---|
558 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
---|
559 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
---|
560 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
---|
561 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
---|
562 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
---|
563 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
---|
564 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
---|
565 | /** |
---|
566 | * @} |
---|
567 | */ |
---|
568 | |
---|
569 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
---|
570 | * @{ |
---|
571 | */ |
---|
572 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
---|
573 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
---|
574 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
---|
575 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
---|
576 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
---|
577 | /** |
---|
578 | * @} |
---|
579 | */ |
---|
580 | |
---|
581 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
---|
582 | * @{ |
---|
583 | */ |
---|
584 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
---|
585 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
---|
586 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
---|
587 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
---|
588 | /** |
---|
589 | * @} |
---|
590 | */ |
---|
591 | |
---|
592 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
---|
593 | * @{ |
---|
594 | */ |
---|
595 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
---|
596 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
---|
597 | /** |
---|
598 | * @} |
---|
599 | */ |
---|
600 | |
---|
601 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
---|
602 | * @{ |
---|
603 | */ |
---|
604 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
---|
605 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
---|
606 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
---|
607 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
---|
608 | /** |
---|
609 | * @} |
---|
610 | */ |
---|
611 | |
---|
612 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state |
---|
613 | * @{ |
---|
614 | */ |
---|
615 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
---|
616 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
---|
617 | /** |
---|
618 | * @} |
---|
619 | */ |
---|
620 | |
---|
621 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state |
---|
622 | * @{ |
---|
623 | */ |
---|
624 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
---|
625 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
---|
626 | /** |
---|
627 | * @} |
---|
628 | */ |
---|
629 | |
---|
630 | /** @defgroup TIM_Lock_level TIM Lock level |
---|
631 | * @{ |
---|
632 | */ |
---|
633 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
---|
634 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
---|
635 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
---|
636 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
---|
637 | /** |
---|
638 | * @} |
---|
639 | */ |
---|
640 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State |
---|
641 | * @{ |
---|
642 | */ |
---|
643 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
---|
644 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000) |
---|
645 | /** |
---|
646 | * @} |
---|
647 | */ |
---|
648 | |
---|
649 | /** @defgroup TIM_Break_Polarity TIM Break Polarity |
---|
650 | * @{ |
---|
651 | */ |
---|
652 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) |
---|
653 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
---|
654 | /** |
---|
655 | * @} |
---|
656 | */ |
---|
657 | |
---|
658 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State |
---|
659 | * @{ |
---|
660 | */ |
---|
661 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
---|
662 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
---|
663 | /** |
---|
664 | * @} |
---|
665 | */ |
---|
666 | |
---|
667 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
---|
668 | * @{ |
---|
669 | */ |
---|
670 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
---|
671 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
---|
672 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
---|
673 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
---|
674 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
---|
675 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
---|
676 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
---|
677 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
---|
678 | /** |
---|
679 | * @} |
---|
680 | */ |
---|
681 | |
---|
682 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
---|
683 | * @{ |
---|
684 | */ |
---|
685 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
---|
686 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
---|
687 | /** |
---|
688 | * @} |
---|
689 | */ |
---|
690 | |
---|
691 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
---|
692 | * @{ |
---|
693 | */ |
---|
694 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
---|
695 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
---|
696 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
---|
697 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
---|
698 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
---|
699 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
---|
700 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
---|
701 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
---|
702 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
---|
703 | /** |
---|
704 | * @} |
---|
705 | */ |
---|
706 | |
---|
707 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
---|
708 | * @{ |
---|
709 | */ |
---|
710 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
---|
711 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
---|
712 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
---|
713 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
---|
714 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
---|
715 | /** |
---|
716 | * @} |
---|
717 | */ |
---|
718 | |
---|
719 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
---|
720 | * @{ |
---|
721 | */ |
---|
722 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
---|
723 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
---|
724 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
---|
725 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
---|
726 | /** |
---|
727 | * @} |
---|
728 | */ |
---|
729 | |
---|
730 | |
---|
731 | /** @defgroup TIM_TI1_Selection TIM TI1 Selection |
---|
732 | * @{ |
---|
733 | */ |
---|
734 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
---|
735 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
---|
736 | /** |
---|
737 | * @} |
---|
738 | */ |
---|
739 | |
---|
740 | /** @defgroup TIM_DMA_Base_address TIM DMA Base address |
---|
741 | * @{ |
---|
742 | */ |
---|
743 | #define TIM_DMABASE_CR1 (0x00000000) |
---|
744 | #define TIM_DMABASE_CR2 (0x00000001) |
---|
745 | #define TIM_DMABASE_SMCR (0x00000002) |
---|
746 | #define TIM_DMABASE_DIER (0x00000003) |
---|
747 | #define TIM_DMABASE_SR (0x00000004) |
---|
748 | #define TIM_DMABASE_EGR (0x00000005) |
---|
749 | #define TIM_DMABASE_CCMR1 (0x00000006) |
---|
750 | #define TIM_DMABASE_CCMR2 (0x00000007) |
---|
751 | #define TIM_DMABASE_CCER (0x00000008) |
---|
752 | #define TIM_DMABASE_CNT (0x00000009) |
---|
753 | #define TIM_DMABASE_PSC (0x0000000A) |
---|
754 | #define TIM_DMABASE_ARR (0x0000000B) |
---|
755 | #define TIM_DMABASE_RCR (0x0000000C) |
---|
756 | #define TIM_DMABASE_CCR1 (0x0000000D) |
---|
757 | #define TIM_DMABASE_CCR2 (0x0000000E) |
---|
758 | #define TIM_DMABASE_CCR3 (0x0000000F) |
---|
759 | #define TIM_DMABASE_CCR4 (0x00000010) |
---|
760 | #define TIM_DMABASE_BDTR (0x00000011) |
---|
761 | #define TIM_DMABASE_DCR (0x00000012) |
---|
762 | #define TIM_DMABASE_OR (0x00000013) |
---|
763 | /** |
---|
764 | * @} |
---|
765 | */ |
---|
766 | |
---|
767 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
---|
768 | * @{ |
---|
769 | */ |
---|
770 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
---|
771 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
---|
772 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
---|
773 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
---|
774 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
---|
775 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
---|
776 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
---|
777 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
---|
778 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
---|
779 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
---|
780 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
---|
781 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
---|
782 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
---|
783 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
---|
784 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
---|
785 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
---|
786 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
---|
787 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
---|
788 | /** |
---|
789 | * @} |
---|
790 | */ |
---|
791 | |
---|
792 | /** @defgroup DMA_Handle_index DMA Handle index |
---|
793 | * @{ |
---|
794 | */ |
---|
795 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
---|
796 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
---|
797 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
---|
798 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
---|
799 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
---|
800 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
---|
801 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
---|
802 | /** |
---|
803 | * @} |
---|
804 | */ |
---|
805 | |
---|
806 | /** @defgroup Channel_CC_State Channel CC State |
---|
807 | * @{ |
---|
808 | */ |
---|
809 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
---|
810 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
---|
811 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004) |
---|
812 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000) |
---|
813 | /** |
---|
814 | * @} |
---|
815 | */ |
---|
816 | |
---|
817 | /** |
---|
818 | * @} |
---|
819 | */ |
---|
820 | |
---|
821 | /* Exported macro ------------------------------------------------------------*/ |
---|
822 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
---|
823 | * @{ |
---|
824 | */ |
---|
825 | /** @brief Reset TIM handle state |
---|
826 | * @param __HANDLE__: TIM handle |
---|
827 | * @retval None |
---|
828 | */ |
---|
829 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
---|
830 | |
---|
831 | /** |
---|
832 | * @brief Enable the TIM peripheral. |
---|
833 | * @param __HANDLE__: TIM handle |
---|
834 | * @retval None |
---|
835 | */ |
---|
836 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
---|
837 | |
---|
838 | /** |
---|
839 | * @brief Enable the TIM update source request. |
---|
840 | * @param __HANDLE__: TIM handle |
---|
841 | * @retval None |
---|
842 | */ |
---|
843 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS)) |
---|
844 | |
---|
845 | /** |
---|
846 | * @brief Enable the TIM main Output. |
---|
847 | * @param __HANDLE__: TIM handle |
---|
848 | * @retval None |
---|
849 | */ |
---|
850 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
---|
851 | |
---|
852 | |
---|
853 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
---|
854 | channels have been disabled */ |
---|
855 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
---|
856 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
---|
857 | |
---|
858 | /** |
---|
859 | * @brief Disable the TIM peripheral. |
---|
860 | * @param __HANDLE__: TIM handle |
---|
861 | * @retval None |
---|
862 | */ |
---|
863 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
---|
864 | do { \ |
---|
865 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
---|
866 | { \ |
---|
867 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
---|
868 | { \ |
---|
869 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
---|
870 | } \ |
---|
871 | } \ |
---|
872 | } while(0) |
---|
873 | |
---|
874 | /** |
---|
875 | * @brief Disable the TIM update source request. |
---|
876 | * @param __HANDLE__: TIM handle |
---|
877 | * @retval None |
---|
878 | */ |
---|
879 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
---|
880 | |
---|
881 | |
---|
882 | /* The Main Output of a timer instance is disabled only if all the CCx and CCxN |
---|
883 | channels have been disabled */ |
---|
884 | /** |
---|
885 | * @brief Disable the TIM main Output. |
---|
886 | * @param __HANDLE__: TIM handle |
---|
887 | * @retval None |
---|
888 | */ |
---|
889 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
---|
890 | do { \ |
---|
891 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
---|
892 | { \ |
---|
893 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
---|
894 | { \ |
---|
895 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
---|
896 | } \ |
---|
897 | } \ |
---|
898 | } while(0) |
---|
899 | |
---|
900 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
---|
901 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
---|
902 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
---|
903 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
---|
904 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
---|
905 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
---|
906 | |
---|
907 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
---|
908 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
---|
909 | |
---|
910 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
---|
911 | #define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
---|
912 | |
---|
913 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
---|
914 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
---|
915 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
---|
916 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
---|
917 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
---|
918 | |
---|
919 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
---|
920 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
---|
921 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
---|
922 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
---|
923 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
---|
924 | |
---|
925 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
---|
926 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
---|
927 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
---|
928 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
---|
929 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) |
---|
930 | |
---|
931 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
---|
932 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
---|
933 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
---|
934 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
---|
935 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
---|
936 | |
---|
937 | /** |
---|
938 | * @brief Sets the TIM Counter Register value on runtime. |
---|
939 | * @param __HANDLE__: TIM handle. |
---|
940 | * @param __COUNTER__: specifies the Counter register new value. |
---|
941 | * @retval None |
---|
942 | */ |
---|
943 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
---|
944 | |
---|
945 | /** |
---|
946 | * @brief Gets the TIM Counter Register value on runtime. |
---|
947 | * @param __HANDLE__: TIM handle. |
---|
948 | * @retval None |
---|
949 | */ |
---|
950 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
---|
951 | |
---|
952 | /** |
---|
953 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
---|
954 | * another time any Init function. |
---|
955 | * @param __HANDLE__: TIM handle. |
---|
956 | * @param __AUTORELOAD__: specifies the Counter register new value. |
---|
957 | * @retval None |
---|
958 | */ |
---|
959 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
---|
960 | do{ \ |
---|
961 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
---|
962 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
---|
963 | } while(0) |
---|
964 | /** |
---|
965 | * @brief Gets the TIM Autoreload Register value on runtime |
---|
966 | * @param __HANDLE__: TIM handle. |
---|
967 | * @retval None |
---|
968 | */ |
---|
969 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
---|
970 | |
---|
971 | /** |
---|
972 | * @brief Sets the TIM Clock Division value on runtime without calling |
---|
973 | * another time any Init function. |
---|
974 | * @param __HANDLE__: TIM handle. |
---|
975 | * @param __CKD__: specifies the clock division value. |
---|
976 | * This parameter can be one of the following value: |
---|
977 | * @arg TIM_CLOCKDIVISION_DIV1 |
---|
978 | * @arg TIM_CLOCKDIVISION_DIV2 |
---|
979 | * @arg TIM_CLOCKDIVISION_DIV4 |
---|
980 | * @retval None |
---|
981 | */ |
---|
982 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
---|
983 | do{ \ |
---|
984 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
---|
985 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
---|
986 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
---|
987 | } while(0) |
---|
988 | /** |
---|
989 | * @brief Gets the TIM Clock Division value on runtime |
---|
990 | * @param __HANDLE__: TIM handle. |
---|
991 | * @retval None |
---|
992 | */ |
---|
993 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
---|
994 | |
---|
995 | /** |
---|
996 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
---|
997 | * another time HAL_TIM_IC_ConfigChannel() function. |
---|
998 | * @param __HANDLE__: TIM handle. |
---|
999 | * @param __CHANNEL__ : TIM Channels to be configured. |
---|
1000 | * This parameter can be one of the following values: |
---|
1001 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
---|
1002 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
---|
1003 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
---|
1004 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
---|
1005 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
---|
1006 | * This parameter can be one of the following values: |
---|
1007 | * @arg TIM_ICPSC_DIV1: no prescaler |
---|
1008 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
---|
1009 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
---|
1010 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
---|
1011 | * @retval None |
---|
1012 | */ |
---|
1013 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
---|
1014 | do{ \ |
---|
1015 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
---|
1016 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
---|
1017 | } while(0) |
---|
1018 | |
---|
1019 | /** |
---|
1020 | * @brief Gets the TIM Input Capture prescaler on runtime |
---|
1021 | * @param __HANDLE__: TIM handle. |
---|
1022 | * @param __CHANNEL__ : TIM Channels to be configured. |
---|
1023 | * This parameter can be one of the following values: |
---|
1024 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
---|
1025 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
---|
1026 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
---|
1027 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
---|
1028 | * @retval None |
---|
1029 | */ |
---|
1030 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
---|
1031 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
---|
1032 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
---|
1033 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
---|
1034 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
---|
1035 | |
---|
1036 | /** |
---|
1037 | * @brief Sets the TIM Capture x input polarity on runtime. |
---|
1038 | * @param __HANDLE__: TIM handle. |
---|
1039 | * @param __CHANNEL__: TIM Channels to be configured. |
---|
1040 | * This parameter can be one of the following values: |
---|
1041 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
---|
1042 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
---|
1043 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
---|
1044 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
---|
1045 | * @param __POLARITY__: Polarity for TIx source |
---|
1046 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
---|
1047 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
---|
1048 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
---|
1049 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
---|
1050 | * @retval None |
---|
1051 | */ |
---|
1052 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
---|
1053 | do{ \ |
---|
1054 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
---|
1055 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
---|
1056 | }while(0) |
---|
1057 | |
---|
1058 | /** |
---|
1059 | * @} |
---|
1060 | */ |
---|
1061 | |
---|
1062 | /* Include TIM HAL Extension module */ |
---|
1063 | #include "stm32f7xx_hal_tim_ex.h" |
---|
1064 | |
---|
1065 | /* Exported functions --------------------------------------------------------*/ |
---|
1066 | /** @addtogroup TIM_Exported_Functions |
---|
1067 | * @{ |
---|
1068 | */ |
---|
1069 | |
---|
1070 | /** @addtogroup TIM_Exported_Functions_Group1 |
---|
1071 | * @{ |
---|
1072 | */ |
---|
1073 | |
---|
1074 | /* Time Base functions ********************************************************/ |
---|
1075 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
---|
1076 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
---|
1077 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
---|
1078 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1079 | /* Blocking mode: Polling */ |
---|
1080 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
---|
1081 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
---|
1082 | /* Non-Blocking mode: Interrupt */ |
---|
1083 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
---|
1084 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
---|
1085 | /* Non-Blocking mode: DMA */ |
---|
1086 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
---|
1087 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
---|
1088 | /** |
---|
1089 | * @} |
---|
1090 | */ |
---|
1091 | |
---|
1092 | /** @addtogroup TIM_Exported_Functions_Group2 |
---|
1093 | * @{ |
---|
1094 | */ |
---|
1095 | /* Timer Output Compare functions **********************************************/ |
---|
1096 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
---|
1097 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
---|
1098 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
---|
1099 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1100 | /* Blocking mode: Polling */ |
---|
1101 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1102 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1103 | /* Non-Blocking mode: Interrupt */ |
---|
1104 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1105 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1106 | /* Non-Blocking mode: DMA */ |
---|
1107 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
---|
1108 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1109 | |
---|
1110 | /** |
---|
1111 | * @} |
---|
1112 | */ |
---|
1113 | |
---|
1114 | /** @addtogroup TIM_Exported_Functions_Group3 |
---|
1115 | * @{ |
---|
1116 | */ |
---|
1117 | /* Timer PWM functions *********************************************************/ |
---|
1118 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
---|
1119 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
---|
1120 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
---|
1121 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1122 | /* Blocking mode: Polling */ |
---|
1123 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1124 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1125 | /* Non-Blocking mode: Interrupt */ |
---|
1126 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1127 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1128 | /* Non-Blocking mode: DMA */ |
---|
1129 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
---|
1130 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1131 | |
---|
1132 | /** |
---|
1133 | * @} |
---|
1134 | */ |
---|
1135 | |
---|
1136 | /** @addtogroup TIM_Exported_Functions_Group4 |
---|
1137 | * @{ |
---|
1138 | */ |
---|
1139 | /* Timer Input Capture functions ***********************************************/ |
---|
1140 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
---|
1141 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
---|
1142 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
---|
1143 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1144 | /* Blocking mode: Polling */ |
---|
1145 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1146 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1147 | /* Non-Blocking mode: Interrupt */ |
---|
1148 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1149 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1150 | /* Non-Blocking mode: DMA */ |
---|
1151 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
---|
1152 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1153 | |
---|
1154 | /** |
---|
1155 | * @} |
---|
1156 | */ |
---|
1157 | |
---|
1158 | /** @addtogroup TIM_Exported_Functions_Group5 |
---|
1159 | * @{ |
---|
1160 | */ |
---|
1161 | /* Timer One Pulse functions ***************************************************/ |
---|
1162 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
---|
1163 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
---|
1164 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
---|
1165 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1166 | /* Blocking mode: Polling */ |
---|
1167 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
---|
1168 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
---|
1169 | |
---|
1170 | /* Non-Blocking mode: Interrupt */ |
---|
1171 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
---|
1172 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
---|
1173 | |
---|
1174 | /** |
---|
1175 | * @} |
---|
1176 | */ |
---|
1177 | |
---|
1178 | /** @addtogroup TIM_Exported_Functions_Group6 |
---|
1179 | * @{ |
---|
1180 | */ |
---|
1181 | /* Timer Encoder functions *****************************************************/ |
---|
1182 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
---|
1183 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
---|
1184 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
---|
1185 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
---|
1186 | /* Blocking mode: Polling */ |
---|
1187 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1188 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1189 | /* Non-Blocking mode: Interrupt */ |
---|
1190 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1191 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1192 | /* Non-Blocking mode: DMA */ |
---|
1193 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
---|
1194 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1195 | |
---|
1196 | /** |
---|
1197 | * @} |
---|
1198 | */ |
---|
1199 | |
---|
1200 | /** @addtogroup TIM_Exported_Functions_Group7 |
---|
1201 | * @{ |
---|
1202 | */ |
---|
1203 | /* Interrupt Handler functions **********************************************/ |
---|
1204 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
---|
1205 | |
---|
1206 | /** |
---|
1207 | * @} |
---|
1208 | */ |
---|
1209 | |
---|
1210 | /** @addtogroup TIM_Exported_Functions_Group8 |
---|
1211 | * @{ |
---|
1212 | */ |
---|
1213 | /* Control functions *********************************************************/ |
---|
1214 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
---|
1215 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
---|
1216 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
---|
1217 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
---|
1218 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
---|
1219 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
---|
1220 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
---|
1221 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
---|
1222 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
---|
1223 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
---|
1224 | uint32_t *BurstBuffer, uint32_t BurstLength); |
---|
1225 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
---|
1226 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
---|
1227 | uint32_t *BurstBuffer, uint32_t BurstLength); |
---|
1228 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
---|
1229 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
---|
1230 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
---|
1231 | |
---|
1232 | /** |
---|
1233 | * @} |
---|
1234 | */ |
---|
1235 | |
---|
1236 | /** @addtogroup TIM_Exported_Functions_Group9 |
---|
1237 | * @{ |
---|
1238 | */ |
---|
1239 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
---|
1240 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
---|
1241 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
---|
1242 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
---|
1243 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
---|
1244 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
---|
1245 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
---|
1246 | |
---|
1247 | /** |
---|
1248 | * @} |
---|
1249 | */ |
---|
1250 | |
---|
1251 | /** @addtogroup TIM_Exported_Functions_Group10 |
---|
1252 | * @{ |
---|
1253 | */ |
---|
1254 | /* Peripheral State functions **************************************************/ |
---|
1255 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
---|
1256 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
---|
1257 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
---|
1258 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
---|
1259 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
---|
1260 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
---|
1261 | |
---|
1262 | /** |
---|
1263 | * @} |
---|
1264 | */ |
---|
1265 | |
---|
1266 | /** |
---|
1267 | * @} |
---|
1268 | */ |
---|
1269 | |
---|
1270 | /* Private macros ------------------------------------------------------------*/ |
---|
1271 | /** @defgroup TIM_Private_Macros TIM Private Macros |
---|
1272 | * @{ |
---|
1273 | */ |
---|
1274 | |
---|
1275 | /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters |
---|
1276 | * @{ |
---|
1277 | */ |
---|
1278 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
---|
1279 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
---|
1280 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
---|
1281 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
---|
1282 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
---|
1283 | |
---|
1284 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
---|
1285 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
---|
1286 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
---|
1287 | |
---|
1288 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
---|
1289 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
---|
1290 | |
---|
1291 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ |
---|
1292 | ((STATE) == TIM_OUTPUTSTATE_ENABLE)) |
---|
1293 | |
---|
1294 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ |
---|
1295 | ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) |
---|
1296 | |
---|
1297 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
---|
1298 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
---|
1299 | |
---|
1300 | #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ |
---|
1301 | ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) |
---|
1302 | |
---|
1303 | #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ |
---|
1304 | ((__STATE__) == TIM_OCIDLESTATE_RESET)) |
---|
1305 | |
---|
1306 | #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ |
---|
1307 | ((__STATE__) == TIM_OCNIDLESTATE_RESET)) |
---|
1308 | |
---|
1309 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
---|
1310 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
---|
1311 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
---|
1312 | |
---|
1313 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
---|
1314 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
---|
1315 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
---|
1316 | |
---|
1317 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
---|
1318 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
---|
1319 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
---|
1320 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
---|
1321 | |
---|
1322 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
---|
1323 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
---|
1324 | |
---|
1325 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
---|
1326 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
---|
1327 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
---|
1328 | |
---|
1329 | #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000)) |
---|
1330 | |
---|
1331 | |
---|
1332 | #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ |
---|
1333 | ((__IT__) == TIM_IT_CC1) || \ |
---|
1334 | ((__IT__) == TIM_IT_CC2) || \ |
---|
1335 | ((__IT__) == TIM_IT_CC3) || \ |
---|
1336 | ((__IT__) == TIM_IT_CC4) || \ |
---|
1337 | ((__IT__) == TIM_IT_COM) || \ |
---|
1338 | ((__IT__) == TIM_IT_TRIGGER) || \ |
---|
1339 | ((__IT__) == TIM_IT_BREAK)) |
---|
1340 | |
---|
1341 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) |
---|
1342 | |
---|
1343 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) |
---|
1344 | |
---|
1345 | #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ |
---|
1346 | ((__FLAG__) == TIM_FLAG_CC1) || \ |
---|
1347 | ((__FLAG__) == TIM_FLAG_CC2) || \ |
---|
1348 | ((__FLAG__) == TIM_FLAG_CC3) || \ |
---|
1349 | ((__FLAG__) == TIM_FLAG_CC4) || \ |
---|
1350 | ((__FLAG__) == TIM_FLAG_COM) || \ |
---|
1351 | ((__FLAG__) == TIM_FLAG_TRIGGER) || \ |
---|
1352 | ((__FLAG__) == TIM_FLAG_BREAK) || \ |
---|
1353 | ((__FLAG__) == TIM_FLAG_BREAK2) || \ |
---|
1354 | ((__FLAG__) == TIM_FLAG_CC1OF) || \ |
---|
1355 | ((__FLAG__) == TIM_FLAG_CC2OF) || \ |
---|
1356 | ((__FLAG__) == TIM_FLAG_CC3OF) || \ |
---|
1357 | ((__FLAG__) == TIM_FLAG_CC4OF)) |
---|
1358 | |
---|
1359 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
---|
1360 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
---|
1361 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
---|
1362 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
---|
1363 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
---|
1364 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
---|
1365 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
---|
1366 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
---|
1367 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
---|
1368 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
---|
1369 | |
---|
1370 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
---|
1371 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
---|
1372 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
---|
1373 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
---|
1374 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
---|
1375 | |
---|
1376 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
---|
1377 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
---|
1378 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
---|
1379 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
---|
1380 | |
---|
1381 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
---|
1382 | |
---|
1383 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
---|
1384 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
---|
1385 | |
---|
1386 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
---|
1387 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
---|
1388 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
---|
1389 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
---|
1390 | |
---|
1391 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
---|
1392 | |
---|
1393 | #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ |
---|
1394 | ((__STATE__) == TIM_OSSR_DISABLE)) |
---|
1395 | |
---|
1396 | #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ |
---|
1397 | ((__STATE__) == TIM_OSSI_DISABLE)) |
---|
1398 | |
---|
1399 | #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ |
---|
1400 | ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ |
---|
1401 | ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ |
---|
1402 | ((__LEVEL__) == TIM_LOCKLEVEL_3)) |
---|
1403 | |
---|
1404 | #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ |
---|
1405 | ((__STATE__) == TIM_BREAK_DISABLE)) |
---|
1406 | |
---|
1407 | #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ |
---|
1408 | ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) |
---|
1409 | |
---|
1410 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
---|
1411 | ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) |
---|
1412 | |
---|
1413 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
---|
1414 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
---|
1415 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
---|
1416 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
---|
1417 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
---|
1418 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
---|
1419 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
---|
1420 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
---|
1421 | |
---|
1422 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
---|
1423 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
---|
1424 | |
---|
1425 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
---|
1426 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
---|
1427 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
---|
1428 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
---|
1429 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
---|
1430 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
---|
1431 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
---|
1432 | ((__SELECTION__) == TIM_TS_ETRF)) |
---|
1433 | |
---|
1434 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
---|
1435 | ((SELECTION) == TIM_TS_ITR1) || \ |
---|
1436 | ((SELECTION) == TIM_TS_ITR2) || \ |
---|
1437 | ((SELECTION) == TIM_TS_ITR3)) |
---|
1438 | |
---|
1439 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
---|
1440 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
---|
1441 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
---|
1442 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
---|
1443 | ((__SELECTION__) == TIM_TS_NONE)) |
---|
1444 | |
---|
1445 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
---|
1446 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
---|
1447 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
---|
1448 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
---|
1449 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
---|
1450 | |
---|
1451 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
---|
1452 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
---|
1453 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
---|
1454 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
---|
1455 | |
---|
1456 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
---|
1457 | |
---|
1458 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
---|
1459 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
---|
1460 | |
---|
1461 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
---|
1462 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
---|
1463 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
---|
1464 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
---|
1465 | ((__BASE__) == TIM_DMABASE_SR) || \ |
---|
1466 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
---|
1467 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
---|
1468 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
---|
1469 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
---|
1470 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
---|
1471 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
---|
1472 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
---|
1473 | ((__BASE__) == TIM_DMABASE_RCR) || \ |
---|
1474 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
---|
1475 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
---|
1476 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
---|
1477 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
---|
1478 | ((__BASE__) == TIM_DMABASE_BDTR) || \ |
---|
1479 | ((__BASE__) == TIM_DMABASE_DCR) || \ |
---|
1480 | ((__BASE__) == TIM_DMABASE_OR)) |
---|
1481 | |
---|
1482 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
---|
1483 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
---|
1484 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
---|
1485 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
---|
1486 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
---|
1487 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
---|
1488 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
---|
1489 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
---|
1490 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
---|
1491 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
---|
1492 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
---|
1493 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
---|
1494 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
---|
1495 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
---|
1496 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
---|
1497 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
---|
1498 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
---|
1499 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
---|
1500 | |
---|
1501 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
---|
1502 | |
---|
1503 | |
---|
1504 | /** |
---|
1505 | * @} |
---|
1506 | */ |
---|
1507 | |
---|
1508 | /** |
---|
1509 | * @} |
---|
1510 | */ |
---|
1511 | |
---|
1512 | /* Private functions ---------------------------------------------------------*/ |
---|
1513 | /** @defgroup TIM_Private_Functions TIM Private Functions |
---|
1514 | * @{ |
---|
1515 | */ |
---|
1516 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
---|
1517 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
---|
1518 | void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
---|
1519 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
---|
1520 | void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
---|
1521 | void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
---|
1522 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
---|
1523 | |
---|
1524 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
---|
1525 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); |
---|
1526 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
---|
1527 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
---|
1528 | /** |
---|
1529 | * @} |
---|
1530 | */ |
---|
1531 | |
---|
1532 | /** |
---|
1533 | * @} |
---|
1534 | */ |
---|
1535 | |
---|
1536 | /** |
---|
1537 | * @} |
---|
1538 | */ |
---|
1539 | |
---|
1540 | #ifdef __cplusplus |
---|
1541 | } |
---|
1542 | #endif |
---|
1543 | |
---|
1544 | #endif /* __STM32F7xx_HAL_TIM_H */ |
---|
1545 | |
---|
1546 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
---|