source: rtems/c/src/lib/libbsp/arm/stm32f4/startup/io.c @ 1485a58

4.115
Last change on this file since 1485a58 was 1485a58, checked in by Christian Mauderer <Christian.Mauderer@…>, on 09/18/13 at 13:44:42

bsp/stm32f4: Add STM32F10XXX support.
  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*
2 * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#include <bsp/io.h>
16#include <bsp/rcc.h>
17#include <bsp/stm32f4.h>
18
19#include <rtems.h>
20
21RTEMS_STATIC_ASSERT(sizeof(stm32f4_gpio_config) == 4, size_of_config);
22
23void stm32f4_gpio_set_clock(int pin, bool set)
24{
25  int port = STM32F4_GPIO_PORT_OF_PIN(pin);
26  stm32f4_rcc_index index = STM32F4_RCC_GPIOA + port;
27
28  stm32f4_rcc_set_clock(index, set);
29}
30
31static void clear_and_set(
32  volatile uint32_t *reg,
33  unsigned index,
34  unsigned width,
35  uint32_t set
36)
37{
38  uint32_t mask = (1U << width) - 1U;
39  unsigned shift = width * index;
40  uint32_t val = *reg;
41
42  val &= ~(mask << shift);
43  val |= set << shift;
44
45  *reg = val;
46}
47
48#ifdef STM32F4_FAMILY_F10XXX
49#define STM32F4_AFIO_REMAP_ENTRY(mod, afio_reg_v, start_v, width_v, value_v) \
50  [mod] = { \
51    .afio_reg = afio_reg_v, \
52    .start = start_v, \
53    .width = width_v, \
54    .value = value_v, \
55    .reserved = 0 \
56  }
57
58typedef struct {
59  uint16_t afio_reg : 3;
60  uint16_t start : 5;
61  uint16_t width : 2;
62  uint16_t value : 3;
63  uint16_t reserved : 3;
64} stm32f4_afio_remap_entry;
65
66static const stm32f4_afio_remap_entry stm32f4_afio_remap_table [] = {
67  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_DONT_CHANGE, 0, 0, 0, 0),
68  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_0, 1, 0, 1, 0),
69  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_1, 1, 0, 1, 1),
70  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_0, 1, 1, 1, 0),
71  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_1, 1, 1, 1, 1),
72  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_0, 1, 2, 1, 0),
73  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_1, 1, 2, 1, 1),
74  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_0, 1, 3, 1, 0),
75  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_1, 1, 3, 1, 1),
76  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_0, 1, 4, 2, 0),
77  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_1, 1, 4, 2, 1),
78  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_3, 1, 4, 2, 3),
79  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_0, 1, 6, 2, 0),
80  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_1, 1, 6, 2, 1),
81  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_3, 1, 6, 2, 3),
82  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_0, 1, 8, 2, 0),
83  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_1, 1, 8, 2, 1),
84  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_2, 1, 8, 2, 2),
85  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_3, 1, 8, 2, 3),
86  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_0, 1, 10, 2, 0),
87  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_2, 1, 10, 2, 2),
88  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_3, 1, 10, 2, 3),
89  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_0, 1, 12, 1, 0),
90  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_1, 1, 12, 1, 1),
91  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_0, 1, 13, 2, 0),
92  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_2, 1, 13, 2, 2),
93  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_3, 1, 13, 2, 3),
94  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_0, 1, 15, 1, 0),
95  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_1, 1, 15, 1, 1),
96  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_0, 1, 16, 1, 0),
97  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_1, 1, 16, 1, 1),
98  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, 1, 17, 1, 0),
99  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, 1, 17, 1, 1),
100  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, 1, 18, 1, 0),
101  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, 1, 18, 1, 1),
102  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, 1, 19, 1, 0),
103  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, 1, 19, 1, 1),
104  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, 1, 20, 1, 0),
105  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, 1, 20, 1, 1),
106  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_0, 1, 21, 1, 0),
107  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_1, 1, 21, 1, 1),
108  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_0, 1, 22, 1, 0),
109  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_1, 1, 22, 1, 1),
110  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_0, 1, 23, 1, 0),
111  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_1, 1, 23, 1, 1),
112  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_0, 1, 24, 3, 0),
113  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_1, 1, 24, 3, 1),
114  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_2, 1, 24, 3, 2),
115  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_4, 1, 24, 3, 4),
116  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_0, 1, 28, 1, 0),
117  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_1, 1, 28, 1, 1),
118  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_0, 1, 29, 1, 0),
119  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_1, 1, 29, 1, 1),
120  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_0, 1, 30, 1, 0),
121  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_1, 1, 30, 1, 1),
122  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_0, 6, 0, 1, 0),
123  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_1, 6, 0, 1, 1),
124  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_0, 6, 1, 1, 0),
125  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_1, 6, 1, 1, 1),
126  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_0, 6, 2, 1, 0),
127  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_1, 6, 2, 1, 1),
128  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_0, 6, 3, 1, 0),
129  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_1, 6, 3, 1, 1),
130  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_0, 6, 4, 1, 0),
131  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_1, 6, 4, 1, 1),
132  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_0, 6, 5, 1, 0),
133  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_1, 6, 5, 1, 1),
134  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_0, 6, 6, 1, 0),
135  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_1, 6, 6, 1, 1),
136  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_0, 6, 7, 1, 0),
137  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_1, 6, 7, 1, 1),
138  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_0, 6, 8, 1, 0),
139  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_1, 6, 8, 1, 1),
140  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_0, 6, 9, 1, 0),
141  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_1, 6, 9, 1, 1),
142  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_0, 6, 10, 1, 0),
143  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_1, 6, 10, 1, 1),
144  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, 6, 11, 1, 0),
145  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, 6, 11, 1, 1),
146  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_0, 6, 12, 1, 0),
147  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_1, 6, 12, 1, 1),
148  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_0, 6, 13, 1, 0),
149  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_1, 6, 13, 1, 1),
150};
151
152static void set_remap_config(stm32f4_gpio_remap remap)
153{
154  if(remap != STM32F4_GPIO_REMAP_DONT_CHANGE)
155  {
156    stm32f4_afio_remap_entry entry = stm32f4_afio_remap_table[remap];
157    volatile stm32f4_afio *afio = STM32F4_AFIO;
158    volatile uint32_t *reg = ((uint32_t*) afio) + entry.afio_reg;
159    uint32_t mask = (1 << entry.width) - 1;
160    uint32_t value = *reg;
161
162    value &= mask << entry.start;
163    value |= entry.value << entry.start;
164
165    *reg = value;
166  }
167}
168
169#endif /* STM32F4_FAMILY_F10XXX */
170
171static void set_config(unsigned pin, const stm32f4_gpio_config *config)
172{
173  unsigned port = STM32F4_GPIO_PORT_OF_PIN(pin);
174  volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
175  unsigned index = STM32F4_GPIO_INDEX_OF_PIN(pin);
176  rtems_interrupt_level level;
177  int set_or_clear_offset = config->fields.output ? 0 : 16;
178#ifdef STM32F4_FAMILY_F4XXXX
179  unsigned af_reg = index >> 3;
180  unsigned af_index = index & 0x7;
181
182  rtems_interrupt_disable(level);
183  gpio->bsrr = 1U << (index + set_or_clear_offset);
184  clear_and_set(&gpio->pupdr, index, 2, config->fields.pupd);
185  clear_and_set(&gpio->otyper, index, 1, config->fields.otype);
186  clear_and_set(&gpio->ospeedr, index, 2, config->fields.ospeed);
187  clear_and_set(&gpio->afr [af_reg], af_index, 4, config->fields.af);
188  clear_and_set(&gpio->moder, index, 2, config->fields.mode);
189  rtems_interrupt_enable(level);
190
191#endif /* STM32F4_FAMILY_F4XXXX */
192#ifdef STM32F4_FAMILY_F10XXX
193  unsigned cr_reg = index >> 3;
194  unsigned cr_index = index & 3;
195
196  rtems_interrupt_disable(level);
197  gpio->bsrr = 1U << (index + set_or_clear_offset);
198  clear_and_set(&gpio->cr[cr_reg], cr_index, 4,
199    (config->fields.cnf << 2) | config->fields.mode);
200  set_remap_config(config->fields.remap);
201  rtems_interrupt_enable(level);
202
203#endif /* STM32F4_FAMILY_F10XXX */
204}
205
206void stm32f4_gpio_set_config(const stm32f4_gpio_config *config)
207{
208  int current = config->fields.pin_first;
209  int last = config->fields.pin_last;
210
211#ifdef STM32F4_FAMILY_F10XXX
212  stm32f4_rcc_set_clock(STM32F4_RCC_AFIO, true);
213#endif /* STM32F4_FAMILY_F10XXX */
214
215  while (current <= last) {
216    stm32f4_gpio_set_clock(current, true);
217    set_config(current, config);
218    ++current;
219  }
220}
221
222void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs)
223{
224  stm32f4_gpio_config terminal = STM32F4_GPIO_CONFIG_TERMINAL;
225
226  while (configs->value != terminal.value) {
227    stm32f4_gpio_set_config(configs);
228    ++configs;
229  }
230}
231
232void stm32f4_gpio_set_output(int pin, bool set)
233{
234  int port = STM32F4_GPIO_PORT_OF_PIN(pin);
235  volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
236  int index = STM32F4_GPIO_INDEX_OF_PIN(pin);
237  int set_or_clear_offset = set ? 0 : 16;
238
239  gpio->bsrr = 1U << (index + set_or_clear_offset);
240}
241
242bool stm32f4_gpio_get_input(int pin)
243{
244  int port = STM32F4_GPIO_PORT_OF_PIN(pin);
245  volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
246  int index = STM32F4_GPIO_INDEX_OF_PIN(pin);
247
248  return (gpio->idr & (1U << index)) != 0;
249}
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