[e230fb4] | 1 | /* |
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| 2 | * Copyright (c) 2012 Sebastian Huber. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Obere Lagerstr. 30 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <rtems@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[e230fb4] | 13 | */ |
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| 14 | |
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| 15 | #include <bsp.h> |
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[7be19f8] | 16 | #include <bsp/io.h> |
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| 17 | #include <bsp/irq.h> |
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[e230fb4] | 18 | #include <bsp/bootcard.h> |
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| 19 | #include <bsp/irq-generic.h> |
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[7db6953] | 20 | #include <assert.h> |
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| 21 | #include <bsp/stm32f4.h> |
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[e230fb4] | 22 | |
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[7db6953] | 23 | #ifdef STM32F4_FAMILY_F4XXXX |
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| 24 | |
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| 25 | #include <bsp/stm32f4xxxx_rcc.h> |
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| 26 | #include <bsp/stm32f4xxxx_flash.h> |
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| 27 | |
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| 28 | static rtems_status_code set_system_clk( |
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| 29 | uint32_t sys_clk, |
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| 30 | uint32_t hse_clk, |
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| 31 | uint32_t hse_flag |
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| 32 | ); |
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| 33 | |
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| 34 | static void init_main_osc( void ) |
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| 35 | { |
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| 36 | volatile stm32f4_rcc *rcc = STM32F4_RCC; |
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| 37 | rtems_status_code status; |
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| 38 | |
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| 39 | /* Revert to reset values */ |
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| 40 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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| 41 | |
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| 42 | while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ; |
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| 43 | |
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| 44 | rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI */ |
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| 45 | |
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| 46 | rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */ |
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| 47 | |
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| 48 | status = set_system_clk( STM32F4_SYSCLK / 1000000L, |
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| 49 | STM32F4_HSE_OSCILLATOR / 1000000L, |
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| 50 | 1 ); |
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| 51 | |
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| 52 | assert( rtems_is_status_successful( status ) ); |
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| 53 | } |
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| 54 | |
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| 55 | /** |
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| 56 | * @brief Sets up clocks configuration. |
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| 57 | * |
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| 58 | * Set up clocks configuration to achieve desired system clock |
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| 59 | * as close as possible with simple math. |
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| 60 | * |
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| 61 | * Limitations: |
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| 62 | * It is assumed that 1MHz resolution is enough. |
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| 63 | * Best fits for the clocks are achieved with multiplies of 42MHz. |
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| 64 | * Even though APB1, APB2 and AHB are calculated user is still required |
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| 65 | * to provide correct values for the bsp configuration for the: |
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| 66 | * STM32F4_PCLK1 |
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| 67 | * STM32F4_PCLK2 |
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| 68 | * STM32F4_HCLK |
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| 69 | * as those are used for the peripheral clocking calculations. |
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| 70 | * |
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| 71 | * @param sys_clk Desired system clock in MHz. |
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| 72 | * @param hse_clk External clock speed in MHz. |
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| 73 | * @param hse_flag Flag determining which clock source to use, 1 for HSE, |
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| 74 | * 0 for HSI. |
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| 75 | * |
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| 76 | * @retval RTEMS_SUCCESSFUL Configuration has been succesfully aplied for the |
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| 77 | * requested clock speed. |
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| 78 | * @retval RTEMS_TIMEOUT HSE clock didn't start or PLL didn't lock. |
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| 79 | * @retval RTEMS_INVALID_NUMBER Requested clock speed is out of range. |
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| 80 | */ |
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| 81 | static rtems_status_code set_system_clk( |
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| 82 | uint32_t sys_clk, |
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| 83 | uint32_t hse_clk, |
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| 84 | uint32_t hse_flag |
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| 85 | ) |
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| 86 | { |
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| 87 | volatile stm32f4_rcc *rcc = STM32F4_RCC; |
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| 88 | volatile stm32f4_flash *flash = STM32F4_FLASH; |
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| 89 | long timeout = 0; |
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| 90 | |
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| 91 | int src_clk = 0; |
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| 92 | |
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| 93 | uint32_t pll_m = 0; |
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| 94 | uint32_t pll_n = 0; |
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| 95 | uint32_t pll_p = 0; |
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| 96 | uint32_t pll_q = 0; |
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| 97 | |
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| 98 | uint32_t ahbpre = 0; |
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| 99 | uint32_t apbpre1 = 0; |
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| 100 | uint32_t apbpre2 = 0; |
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| 101 | |
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| 102 | if ( sys_clk == 16 && hse_clk != 16 ) { |
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| 103 | /* Revert to reset values */ |
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| 104 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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| 105 | |
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| 106 | while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ; |
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| 107 | |
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| 108 | /* all prescalers to 0, clock source to HSI */ |
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| 109 | rcc->cfgr &= 0x00000300 | RCC_CFGR_SW_HSI; |
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| 110 | rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */ |
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| 111 | flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */ |
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| 112 | |
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| 113 | return RTEMS_SUCCESSFUL; |
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| 114 | } |
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| 115 | |
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| 116 | if ( sys_clk == hse_clk ) { |
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| 117 | /* Revert to reset values */ |
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| 118 | rcc->cr |= RCC_CR_HSEON; /* turn on HSE */ |
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| 119 | timeout = 400; |
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| 120 | |
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| 121 | while ( !( rcc->cr & RCC_CR_HSERDY ) && --timeout ) ; |
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| 122 | |
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| 123 | assert( timeout != 0 ); |
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| 124 | |
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| 125 | if ( timeout == 0 ) { |
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| 126 | return RTEMS_TIMEOUT; |
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| 127 | } |
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| 128 | |
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| 129 | /* all prescalers to 0, clock source to HSE */ |
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| 130 | rcc->cfgr &= 0x00000300; |
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| 131 | rcc->cfgr |= RCC_CFGR_SW_HSE; |
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| 132 | /* turn off all clocks and PLL except HSE */ |
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| 133 | rcc->cr &= 0xF0F0FFFC | RCC_CR_HSEON; |
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| 134 | flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */ |
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| 135 | |
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| 136 | return RTEMS_SUCCESSFUL; |
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| 137 | } |
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| 138 | |
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| 139 | /* |
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| 140 | * Lets use 1MHz input for PLL so we get higher VCO output |
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| 141 | * this way we get better value for the PLL_Q divader for the USB |
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| 142 | * |
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| 143 | * Though you might want to use 2MHz as per CPU specification: |
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| 144 | * |
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| 145 | * Caution:The software has to set these bits correctly to ensure |
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| 146 | * that the VCO input frequency ranges from 1 to 2 MHz. |
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| 147 | * It is recommended to select a frequency of 2 MHz to limit PLL jitter. |
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| 148 | */ |
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| 149 | |
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| 150 | if ( sys_clk > 180 ) { |
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| 151 | return RTEMS_INVALID_NUMBER; |
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| 152 | } else if ( sys_clk >= 96 ) { |
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| 153 | pll_n = sys_clk << 1; |
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| 154 | pll_p = RCC_PLLCFGR_PLLP_BY_2; |
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| 155 | } else if ( sys_clk >= 48 ) { |
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| 156 | pll_n = sys_clk << 2; |
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| 157 | pll_p = RCC_PLLCFGR_PLLP_BY_4; |
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| 158 | } else if ( sys_clk >= 24 ) { |
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| 159 | pll_n = sys_clk << 3; |
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| 160 | pll_p = RCC_PLLCFGR_PLLP_BY_8; |
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| 161 | } else { |
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| 162 | return RTEMS_INVALID_NUMBER; |
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| 163 | } |
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| 164 | |
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| 165 | if ( hse_clk == 0 || hse_flag == 0 ) { |
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| 166 | src_clk = 16; |
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| 167 | hse_flag = 0; |
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| 168 | } else { |
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| 169 | src_clk = hse_clk; |
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| 170 | } |
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| 171 | |
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| 172 | pll_m = src_clk; /* divide by the oscilator speed in MHz */ |
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| 173 | |
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| 174 | /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG, |
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| 175 | * best if results in the 48MHz for the USB |
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| 176 | */ |
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[040ed0b4] | 177 | pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; |
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[7db6953] | 178 | |
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| 179 | if ( pll_q < 2 ) { |
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| 180 | pll_q = 2; |
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| 181 | } |
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| 182 | |
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| 183 | /* APB1 prescaler, APB1 clock must be < 42MHz */ |
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| 184 | apbpre1 = ( sys_clk * 100 ) / 42; |
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| 185 | |
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| 186 | if ( apbpre1 <= 100 ) { |
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| 187 | apbpre1 = RCC_CFGR_PPRE1_BY_1; |
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| 188 | } else if ( apbpre1 <= 200 ) { |
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| 189 | apbpre1 = RCC_CFGR_PPRE1_BY_2; |
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| 190 | } else if ( apbpre1 <= 400 ) { |
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| 191 | apbpre1 = RCC_CFGR_PPRE1_BY_4; |
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| 192 | } else if ( apbpre1 <= 800 ) { |
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| 193 | apbpre1 = RCC_CFGR_PPRE1_BY_8; |
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| 194 | } else if ( apbpre1 ) { |
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| 195 | apbpre1 = RCC_CFGR_PPRE1_BY_16; |
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| 196 | } |
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| 197 | |
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| 198 | /* APB2 prescaler, APB2 clock must be < 84MHz */ |
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| 199 | apbpre2 = ( sys_clk * 100 ) / 84; |
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| 200 | |
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| 201 | if ( apbpre2 <= 100 ) { |
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| 202 | apbpre2 = RCC_CFGR_PPRE2_BY_1; |
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| 203 | } else if ( apbpre2 <= 200 ) { |
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| 204 | apbpre2 = RCC_CFGR_PPRE2_BY_2; |
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| 205 | } else if ( apbpre2 <= 400 ) { |
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| 206 | apbpre2 = RCC_CFGR_PPRE2_BY_4; |
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| 207 | } else if ( apbpre2 <= 800 ) { |
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| 208 | apbpre2 = RCC_CFGR_PPRE2_BY_8; |
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| 209 | } else { |
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| 210 | apbpre2 = RCC_CFGR_PPRE2_BY_16; |
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| 211 | } |
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| 212 | |
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| 213 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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| 214 | |
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| 215 | while ( ( !( rcc->cr & RCC_CR_HSIRDY ) ) ) ; |
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| 216 | |
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| 217 | /* all prescalers to 0, clock source to HSI */ |
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| 218 | rcc->cfgr &= 0x00000300; |
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| 219 | rcc->cfgr |= RCC_CFGR_SW_HSI; |
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| 220 | |
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| 221 | while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_HSI ) ) ; |
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| 222 | |
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| 223 | /* turn off PLL */ |
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| 224 | rcc->cr &= ~( RCC_CR_PLLON | RCC_CR_PLLRDY ); |
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| 225 | |
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| 226 | /* turn on HSE */ |
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| 227 | if ( hse_flag ) { |
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| 228 | rcc->cr |= RCC_CR_HSEON; |
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| 229 | timeout = 400; |
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| 230 | |
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| 231 | while ( ( !( rcc->cr & RCC_CR_HSERDY ) ) && timeout-- ) ; |
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| 232 | |
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| 233 | assert( timeout != 0 ); |
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| 234 | |
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| 235 | if ( timeout == 0 ) { |
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| 236 | return RTEMS_TIMEOUT; |
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| 237 | } |
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| 238 | } |
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| 239 | |
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| 240 | rcc->pllcfgr &= 0xF0BC8000; /* clear PLL prescalers */ |
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| 241 | |
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| 242 | /* set pll parameters */ |
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| 243 | rcc->pllcfgr |= RCC_PLLCFGR_PLLM( pll_m ) | /* input divider */ |
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| 244 | RCC_PLLCFGR_PLLN( pll_n ) | /* multiplier */ |
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| 245 | pll_p | /* output divider from table */ |
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| 246 | /* HSE v HSI */ |
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| 247 | ( hse_flag ? RCC_PLLCFGR_PLLSRC_HSE : RCC_PLLCFGR_PLLSRC_HSI ) |
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| 248 | | |
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| 249 | RCC_PLLCFGR_PLLQ( pll_q ); /* PLLQ divider */ |
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| 250 | |
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| 251 | /* set prescalers for the internal busses */ |
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| 252 | rcc->cfgr |= apbpre1 | |
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| 253 | apbpre2 | |
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| 254 | ahbpre; |
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| 255 | |
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| 256 | /* |
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| 257 | * Set flash parameters, hard coded for now for fast system clocks. |
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| 258 | * TODO implement some math to use flash on as low latancy as possible |
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| 259 | */ |
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[040ed0b4] | 260 | flash->acr = STM32F4_FLASH_ACR_LATENCY( 5 ) | /* latency */ |
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| 261 | STM32F4_FLASH_ACR_ICEN | /* instruction cache */ |
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| 262 | STM32F4_FLASH_ACR_DCEN | /* data cache */ |
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| 263 | STM32F4_FLASH_ACR_PRFTEN; |
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[7db6953] | 264 | |
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| 265 | /* turn on PLL */ |
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| 266 | rcc->cr |= RCC_CR_PLLON; |
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| 267 | timeout = 40000; |
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| 268 | |
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| 269 | while ( ( !( rcc->cr & RCC_CR_PLLRDY ) ) && --timeout ) ; |
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| 270 | |
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| 271 | assert( timeout != 0 ); |
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| 272 | |
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| 273 | if ( timeout == 0 ) { |
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| 274 | return RTEMS_TIMEOUT; |
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| 275 | } |
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| 276 | |
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| 277 | /* clock source to PLL */ |
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| 278 | rcc->cfgr = ( rcc->cfgr & ~RCC_CFGR_SW_MSK ) | RCC_CFGR_SW_PLL; |
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| 279 | |
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| 280 | while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_PLL ) ) ; |
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| 281 | |
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| 282 | return RTEMS_SUCCESSFUL; |
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| 283 | } |
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| 284 | |
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| 285 | #endif /* STM32F4_FAMILY_F4XXXX */ |
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| 286 | |
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| 287 | #ifdef STM32F4_FAMILY_F10XXX |
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| 288 | |
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| 289 | static void init_main_osc( void ) |
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| 290 | { |
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| 291 | |
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| 292 | } |
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| 293 | |
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| 294 | #endif /* STM32F4_FAMILY_F10XXX */ |
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| 295 | |
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| 296 | void bsp_start( void ) |
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[e230fb4] | 297 | { |
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[7db6953] | 298 | init_main_osc(); |
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| 299 | |
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| 300 | stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] ); |
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[7be19f8] | 301 | |
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[dd8df59] | 302 | bsp_interrupt_initialize(); |
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[e230fb4] | 303 | } |
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