1 | /** |
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2 | * @file |
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3 | * @ingroup stm32f4xxxx_rcc |
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4 | * @brief STM32F4XXXX RCC support. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2012 Sebastian Huber. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H |
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22 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H |
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23 | |
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24 | #include <bsp/utility.h> |
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25 | |
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26 | /** |
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27 | * @defgroup stm32f4xxxx_rcc STM32F4XXXX RCC Support |
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28 | * @ingroup stm32f4_rcc |
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29 | * @brief STM32F4XXXX RCC Support |
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30 | * @{ |
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31 | */ |
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32 | |
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33 | typedef struct { |
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34 | uint32_t cr; |
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35 | uint32_t pllcfgr; |
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36 | uint32_t cfgr; |
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37 | uint32_t cir; |
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38 | uint32_t ahbrstr[ 3 ]; |
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39 | uint32_t reserved_1c; |
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40 | uint32_t apbrstr[ 2 ]; |
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41 | uint32_t reserved_28[ 2 ]; |
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42 | uint32_t ahbenr[ 3 ]; |
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43 | uint32_t reserved_3c; |
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44 | uint32_t apbenr[ 2 ]; |
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45 | uint32_t reserved_48[ 2 ]; |
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46 | uint32_t ahblpenr[ 3 ]; |
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47 | uint32_t reserved_5c; |
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48 | uint32_t apblpenr[ 2 ]; |
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49 | uint32_t reserved_68[ 2 ]; |
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50 | uint32_t bdcr; |
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51 | uint32_t csr; |
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52 | uint32_t reserved_78[ 2 ]; |
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53 | uint32_t sscgr; |
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54 | uint32_t plli2scfgr; |
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55 | } stm32f4_rcc; |
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56 | |
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57 | /** @} */ |
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58 | |
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59 | #define RCC_CR_HSION BSP_BIT32( 0 ) |
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60 | #define RCC_CR_HSIRDY BSP_BIT32( 1 ) |
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61 | #define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 ) |
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62 | #define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 ) |
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63 | #define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 ) |
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64 | #define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 ) |
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65 | #define RCC_CR_HSEON BSP_BIT32( 16 ) |
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66 | #define RCC_CR_HSERDY BSP_BIT32( 17 ) |
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67 | #define RCC_CR_HSEBYP BSP_BIT32( 18 ) |
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68 | #define RCC_CR_CSSON BSP_BIT32( 19 ) |
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69 | #define RCC_CR_PLLON BSP_BIT32( 24 ) |
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70 | #define RCC_CR_PLLRDY BSP_BIT32( 25 ) |
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71 | #define RCC_CR_PLLI2SON BSP_BIT32( 26 ) |
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72 | #define RCC_CR_PLLI2SRDY BSP_BIT32( 27 ) |
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73 | |
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74 | #define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 ) |
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75 | #define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 ) |
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76 | #define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 ) |
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77 | #define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 ) |
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78 | |
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79 | #define RCC_PLLCFGR_PLLP 16 |
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80 | #define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 ) |
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81 | #define RCC_PLLCFGR_PLLP_BY_2 0 |
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82 | #define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 ) |
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83 | #define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 ) |
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84 | #define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 ) |
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85 | |
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86 | #define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 ) |
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87 | #define RCC_PLLCFGR_PLLSRC_HSI 0 |
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88 | |
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89 | #define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 ) |
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90 | #define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 ) |
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91 | |
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92 | #define RCC_CFGR_SW 0 |
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93 | #define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 ) |
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94 | #define RCC_CFGR_SW_HSI 0 |
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95 | #define RCC_CFGR_SW_HSE 1 |
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96 | #define RCC_CFGR_SW_PLL 2 |
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97 | |
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98 | #define RCC_CFGR_SWS 2 |
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99 | #define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 ) |
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100 | #define RCC_CFGR_SWS_HSI 0 |
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101 | #define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 ) |
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102 | #define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 ) |
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103 | |
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104 | #define RCC_CFGR_HPRE 4 |
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105 | #define RCC_CFGR_HPRE_BY_1 0 |
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106 | #define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 ) |
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107 | #define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 ) |
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108 | #define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 ) |
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109 | #define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 ) |
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110 | #define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 ) |
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111 | #define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 ) |
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112 | #define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 ) |
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113 | #define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 ) |
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114 | |
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115 | #define RCC_CFGR_PPRE1 10 |
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116 | #define RCC_CFGR_PPRE1_BY_1 0 |
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117 | #define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 ) |
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118 | #define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 ) |
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119 | #define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 ) |
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120 | #define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 ) |
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121 | |
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122 | #define RCC_CFGR_PPRE2 13 |
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123 | #define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 ) |
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124 | #define RCC_CFGR_PPRE2_BY_1 0 |
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125 | #define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 ) |
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126 | #define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 ) |
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127 | #define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 ) |
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128 | #define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 ) |
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129 | |
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130 | #define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 ) |
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131 | #define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 ) |
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132 | |
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133 | #define RCC_CFGR_MCO1 21 |
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134 | #define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 ) |
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135 | #define RCC_CFGR_MCO1_HSI 0 |
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136 | #define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 ) |
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137 | #define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 ) |
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138 | #define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 ) |
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139 | |
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140 | #define RCC_CFGR_I2SSRC BSP_BIT32( 23 ) |
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141 | |
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142 | #define RCC_CFGR_MCO1PRE 24 |
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143 | #define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 ) |
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144 | #define RCC_CFGR_MCO1PRE_BY_1 0 |
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145 | #define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 ) |
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146 | #define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 ) |
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147 | #define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 ) |
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148 | #define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 ) |
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149 | |
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150 | #define RCC_CFGR_MCO2PRE 27 |
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151 | #define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 ) |
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152 | #define RCC_CFGR_MCO2PRE_BY_1 0 |
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153 | #define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 ) |
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154 | #define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 ) |
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155 | #define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 ) |
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156 | #define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 ) |
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157 | |
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158 | #define RCC_CFGR_MCO2 30 |
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159 | #define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 ) |
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160 | #define RCC_CFGR_MCO2_SYSCLK 0 |
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161 | #define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 ) |
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162 | #define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) |
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163 | #define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) |
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164 | |
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165 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ |
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