1 | /** |
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2 | * @file |
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3 | * @ingroup stm32f4xxxx_rcc |
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4 | * @brief STM32F4XXXX RCC support. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2012 Sebastian Huber. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H |
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22 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H |
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23 | |
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24 | #include <bsp/utility.h> |
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25 | |
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26 | /** |
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27 | * @defgroup stm32f4xxxx_rcc STM32F4XXXX RCC Support |
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28 | * @ingroup stm32f4_rcc |
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29 | * @brief STM32F4XXXX RCC Support |
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30 | * @{ |
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31 | */ |
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32 | |
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33 | typedef struct { |
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34 | uint32_t cr; |
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35 | #define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag |
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36 | #define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable |
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37 | #define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag |
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38 | #define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable |
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39 | #define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable |
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40 | #define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass |
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41 | #define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag |
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42 | #define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable |
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43 | #define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag |
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44 | #define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable |
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45 | |
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46 | uint32_t pllcfgr; |
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47 | #define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27) |
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48 | #define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27) |
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49 | #define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) |
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50 | #define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source |
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51 | #define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC |
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52 | #define STM32F4_RCC_PLLCFGR_SRC_HSI 0 |
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53 | #define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17) |
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54 | #define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17) |
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55 | #define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) |
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56 | #define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0) |
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57 | #define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1) |
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58 | #define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2) |
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59 | #define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3) |
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60 | #define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14) |
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61 | #define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14) |
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62 | #define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14) |
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63 | #define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5) |
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64 | #define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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65 | #define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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66 | |
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67 | uint32_t cfgr; |
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68 | #define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2 |
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69 | #define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31) |
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70 | #define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31) |
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71 | #define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0) |
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72 | #define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1) |
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73 | #define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2) |
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74 | #define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3) |
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75 | #define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar |
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76 | #define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29) |
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77 | #define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) |
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78 | #define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0) |
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79 | #define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4) |
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80 | #define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5) |
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81 | #define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6) |
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82 | #define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7) |
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83 | #define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar |
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84 | #define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26) |
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85 | #define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) |
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86 | #define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0) |
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87 | #define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4) |
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88 | #define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5) |
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89 | #define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6) |
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90 | #define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7) |
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91 | #define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection |
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92 | #define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1 |
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93 | #define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22) |
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94 | #define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22) |
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95 | #define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0) |
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96 | #define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1) |
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97 | #define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2) |
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98 | #define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3) |
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99 | #define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock |
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100 | #define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20) |
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101 | #define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) |
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102 | #define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2) |
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103 | #define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15) |
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104 | #define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) |
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105 | #define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0) |
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106 | #define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4) |
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107 | #define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5) |
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108 | #define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6) |
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109 | #define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7) |
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110 | #define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1) |
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111 | #define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12) |
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112 | #define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) |
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113 | #define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0) |
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114 | #define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4) |
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115 | #define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) |
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116 | #define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) |
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117 | #define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) |
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118 | #define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar |
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119 | #define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) |
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120 | #define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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121 | #define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0) |
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122 | #define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8) |
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123 | #define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9) |
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124 | #define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10) |
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125 | #define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11) |
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126 | #define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12) |
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127 | #define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13) |
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128 | #define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14) |
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129 | #define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15) |
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130 | #define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status |
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131 | #define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3) |
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132 | #define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) |
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133 | #define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0) |
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134 | #define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1) |
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135 | #define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2) |
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136 | #define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch |
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137 | #define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1) |
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138 | #define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) |
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139 | #define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0) |
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140 | #define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1) |
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141 | #define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2) |
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142 | |
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143 | uint32_t cir; |
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144 | |
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145 | uint32_t ahbrstr [3]; |
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146 | |
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147 | uint32_t reserved_1c; |
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148 | |
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149 | uint32_t apbrstr [2]; |
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150 | |
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151 | uint32_t reserved_28 [2]; |
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152 | |
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153 | uint32_t ahbenr [3]; |
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154 | |
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155 | uint32_t reserved_3c; |
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156 | |
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157 | uint32_t apbenr [2]; |
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158 | |
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159 | uint32_t reserved_48 [2]; |
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160 | |
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161 | uint32_t ahblpenr [3]; |
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162 | |
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163 | uint32_t reserved_5c; |
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164 | |
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165 | uint32_t apblpenr [2]; |
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166 | |
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167 | uint32_t reserved_68 [2]; |
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168 | |
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169 | uint32_t bdcr; |
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170 | |
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171 | uint32_t csr; |
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172 | |
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173 | uint32_t reserved_78 [2]; |
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174 | |
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175 | uint32_t sscgr; |
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176 | |
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177 | uint32_t plli2scfgr; |
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178 | |
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179 | } stm32f4_rcc; |
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180 | |
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181 | /** @} */ |
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182 | |
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183 | #define RCC_CR_HSION BSP_BIT32( 0 ) |
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184 | #define RCC_CR_HSIRDY BSP_BIT32( 1 ) |
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185 | #define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 ) |
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186 | #define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 ) |
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187 | #define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 ) |
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188 | #define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 ) |
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189 | #define RCC_CR_HSEON BSP_BIT32( 16 ) |
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190 | #define RCC_CR_HSERDY BSP_BIT32( 17 ) |
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191 | #define RCC_CR_HSEBYP BSP_BIT32( 18 ) |
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192 | #define RCC_CR_CSSON BSP_BIT32( 19 ) |
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193 | #define RCC_CR_PLLON BSP_BIT32( 24 ) |
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194 | #define RCC_CR_PLLRDY BSP_BIT32( 25 ) |
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195 | #define RCC_CR_PLLI2SON BSP_BIT32( 26 ) |
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196 | #define RCC_CR_PLLI2SRDY BSP_BIT32( 27 ) |
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197 | |
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198 | #define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 ) |
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199 | #define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 ) |
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200 | #define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 ) |
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201 | #define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 ) |
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202 | |
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203 | #define RCC_PLLCFGR_PLLP 16 |
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204 | #define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 ) |
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205 | #define RCC_PLLCFGR_PLLP_BY_2 0 |
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206 | #define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 ) |
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207 | #define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 ) |
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208 | #define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 ) |
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209 | |
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210 | #define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 ) |
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211 | #define RCC_PLLCFGR_PLLSRC_HSI 0 |
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212 | |
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213 | #define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 ) |
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214 | #define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 ) |
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215 | |
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216 | #define RCC_CFGR_SW 0 |
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217 | #define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 ) |
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218 | #define RCC_CFGR_SW_HSI 0 |
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219 | #define RCC_CFGR_SW_HSE 1 |
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220 | #define RCC_CFGR_SW_PLL 2 |
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221 | |
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222 | #define RCC_CFGR_SWS 2 |
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223 | #define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 ) |
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224 | #define RCC_CFGR_SWS_HSI 0 |
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225 | #define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 ) |
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226 | #define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 ) |
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227 | |
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228 | #define RCC_CFGR_HPRE 4 |
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229 | #define RCC_CFGR_HPRE_BY_1 0 |
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230 | #define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 ) |
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231 | #define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 ) |
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232 | #define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 ) |
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233 | #define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 ) |
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234 | #define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 ) |
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235 | #define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 ) |
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236 | #define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 ) |
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237 | #define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 ) |
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238 | |
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239 | #define RCC_CFGR_PPRE1 10 |
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240 | #define RCC_CFGR_PPRE1_BY_1 0 |
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241 | #define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 ) |
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242 | #define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 ) |
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243 | #define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 ) |
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244 | #define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 ) |
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245 | |
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246 | #define RCC_CFGR_PPRE2 13 |
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247 | #define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 ) |
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248 | #define RCC_CFGR_PPRE2_BY_1 0 |
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249 | #define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 ) |
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250 | #define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 ) |
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251 | #define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 ) |
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252 | #define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 ) |
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253 | |
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254 | #define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 ) |
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255 | #define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 ) |
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256 | |
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257 | #define RCC_CFGR_MCO1 21 |
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258 | #define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 ) |
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259 | #define RCC_CFGR_MCO1_HSI 0 |
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260 | #define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 ) |
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261 | #define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 ) |
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262 | #define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 ) |
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263 | |
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264 | #define RCC_CFGR_I2SSRC BSP_BIT32( 23 ) |
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265 | |
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266 | #define RCC_CFGR_MCO1PRE 24 |
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267 | #define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 ) |
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268 | #define RCC_CFGR_MCO1PRE_BY_1 0 |
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269 | #define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 ) |
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270 | #define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 ) |
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271 | #define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 ) |
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272 | #define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 ) |
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273 | |
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274 | #define RCC_CFGR_MCO2PRE 27 |
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275 | #define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 ) |
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276 | #define RCC_CFGR_MCO2PRE_BY_1 0 |
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277 | #define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 ) |
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278 | #define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 ) |
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279 | #define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 ) |
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280 | #define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 ) |
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281 | |
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282 | #define RCC_CFGR_MCO2 30 |
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283 | #define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 ) |
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284 | #define RCC_CFGR_MCO2_SYSCLK 0 |
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285 | #define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 ) |
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286 | #define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) |
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287 | #define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) |
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288 | |
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289 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ |
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