source: rtems/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h @ 78c9fe8

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Last change on this file since 78c9fe8 was d4edbdbc, checked in by Sebastian Huber <sebastian.huber@…>, on 03/20/15 at 13:09:26

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1/*
2 * Copyright (c) 2013 Chris Nott.  All rights reserved.
3 *
4 *  Virtual Logic
5 *  21-25 King St.
6 *  Rockdale NSW 2216
7 *  Australia
8 *  <rtems@vl.com.au>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H
16#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H
17
18#include <bsp/utility.h>
19
20#define USB_OTG_NUM_EPS 4
21#define USB_OTG_MAX_TX_FIFOS 4
22
23#define USB_FIFO_BASE 0x1000
24#define USB_FIFO_OFFS 0x1000
25
26struct stm32f4_otgfs_s {
27  uint32_t gotgctl; // 0x00: Control and status register
28#define STM32F4_OTGFS_GOTGCTL_BSVLD     BSP_BIT32(19) // B-session valid
29#define STM32F4_OTGFS_GOTGCTL_ASVLD     BSP_BIT32(18) // A-session valid
30#define STM32F4_OTGFS_GOTGCTL_DBCT      BSP_BIT32(17) // Debounce time
31#define STM32F4_OTGFS_GOTGCTL_CIDSTS    BSP_BIT32(16) // Connector ID status
32#define STM32F4_OTGFS_GOTGCTL_DHNPEN    BSP_BIT32(11) // Device HNP enable
33#define STM32F4_OTGFS_GOTGCTL_HSHNPEN   BSP_BIT32(10) // Host set HNP enable
34#define STM32F4_OTGFS_GOTGCTL_HNPRQ     BSP_BIT32(9)  // HNP request
35#define STM32F4_OTGFS_GOTGCTL_HNGSCS    BSP_BIT32(8)  // Host negotiation status
36#define STM32F4_OTGFS_GOTGCTL_SRQ       BSP_BIT32(1)  // Session request
37#define STM32F4_OTGFS_GOTGCTL_SRQSCS    BSP_BIT32(0)  // Session request success
38
39  uint32_t gotgint; // 0x04: Interrupt register
40#define STM32F4_OTGFS_GOTGINT_DBCDNE    BSP_BIT32(19) // Debounce done
41#define STM32F4_OTGFS_GOTGINT_ADTOCHG   BSP_BIT32(18) // A-device timeout change
42#define STM32F4_OTGFS_GOTGINT_HNGDET    BSP_BIT32(17) // Host negotiation detected
43#define STM32F4_OTGFS_GOTGINT_HNSSCHG   BSP_BIT32(9)  // Host negotiation success status change
44#define STM32F4_OTGFS_GOTGINT_SRSSCHG   BSP_BIT32(8)  // Session request status change
45#define STM32F4_OTGFS_GOTGINT_SEDET     BSP_BIT32(2)  // Session end detected
46
47  uint32_t gahbcfg; // 0x08: AHB configuration register
48#define STM32F4_OTGFS_GAHBCFG_PTXFELVL  BSP_BIT32(8)  // Periodic txfifo empty level
49#define STM32F4_OTGFS_GAHBCFG_TXFELVL   BSP_BIT32(7)  // Txfifo empty level
50#define STM32F4_OTGFS_GAHBCFG_GINTMSK   BSP_BIT32(0)  // Global interrupt mask
51
52  uint32_t gusbcfg; // 0x0C: USB configuration register
53#define STM32F4_OTGFS_GUSBCFG_CTXPKT    BSP_BIT32(31) // Corrupt TX packet
54#define STM32F4_OTGFS_GUSBCFG_FDMOD     BSP_BIT32(30) // Force device mode
55#define STM32F4_OTGFS_GUSBCFG_FHMOD     BSP_BIT32(29) // Force host mode
56#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13)  // USB turnaround time
57#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13)
58#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val)  BSP_FLD32SET(reg, val, 10, 13)
59#define STM32F4_OTGFS_GUSBCFG_HNPCAP    BSP_BIT32(9)  // HNP-capable
60#define STM32F4_OTGFS_GUSBCFG_SRPCAP    BSP_BIT32(8)  // SRP-capable
61#define STM32F4_OTGFS_GUSBCFG_PHYSEL    BSP_BIT32(6)  // Full speed serial transceiver select
62#define STM32F4_OTGFS_GUSBCFG_TOCAL(val)  BSP_FLD32(val, 0, 2)  // FS timeout calibration
63#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg)  BSP_FLD32GET(reg, 0, 2)
64#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
65
66  uint32_t grstctl; // 0x10: Reset register
67#define STM32F4_OTGFS_GRSTCTL_AHBIDL    BSP_BIT32(31) // AHB master idle
68#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number
69#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10)
70#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val)  BSP_FLD32SET(reg, val, 6, 10)
71#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL  STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10)
72#define STM32F4_OTGFS_GRSTCTL_TXFFLSH   BSP_BIT32(5)  // TX fifo flush
73#define STM32F4_OTGFS_GRSTCTL_RXFFLSH   BSP_BIT32(4)  // RX fifo flush
74#define STM32F4_OTGFS_GRSTCTL_FCRST     BSP_BIT32(2)  // Host frame counter reset
75#define STM32F4_OTGFS_GRSTCTL_HSRST     BSP_BIT32(1)  // HCLK soft reset
76#define STM32F4_OTGFS_GRSTCTL_CSRST     BSP_BIT32(0)  // Core soft reset
77
78  uint32_t gintsts; // 0x14: Core interrupt register
79#define STM32F4_OTGFS_GINTSTS_WKUPINT   BSP_BIT32(31) // Resume / remote wakeup detected interrupt
80#define STM32F4_OTGFS_GINTSTS_SRQINT    BSP_BIT32(30) // Session request / new session detected interrupt
81#define STM32F4_OTGFS_GINTSTS_DISCINT   BSP_BIT32(29) // Disconnect detected interrupt
82#define STM32F4_OTGFS_GINTSTS_CIDSCHG   BSP_BIT32(28) // Connector ID status change
83#define STM32F4_OTGFS_GINTSTS_PTXFE     BSP_BIT32(26) // Periodic TX fifo empty
84#define STM32F4_OTGFS_GINTSTS_HCINT     BSP_BIT32(25) // Host channels interrupt
85#define STM32F4_OTGFS_GINTSTS_HPRTINT   BSP_BIT32(24) // Host port interrupt
86#define STM32F4_OTGFS_GINTSTS_IPXFR     BSP_BIT32(21) // Incomplete periodic transfer
87#define STM32F4_OTGFS_GINTSTS_IISOOXFR  BSP_BIT32(21) // Incomplete isochronous OUT transfer
88#define STM32F4_OTGFS_GINTSTS_IISOIXFR  BSP_BIT32(20) // Incomplete isochronous IN transfer
89#define STM32F4_OTGFS_GINTSTS_OEPINT    BSP_BIT32(19) // OUT endpoint interrupt
90#define STM32F4_OTGFS_GINTSTS_IEPINT    BSP_BIT32(18) // IN endpoint interrupt
91#define STM32F4_OTGFS_GINTSTS_EOPF      BSP_BIT32(15) // End of periodic frame interrupt
92#define STM32F4_OTGFS_GINTSTS_ISOODRP   BSP_BIT32(14) // Isochronous OUT packet dropped interrupt
93#define STM32F4_OTGFS_GINTSTS_ENUMDNE   BSP_BIT32(13) // Enumeration done
94#define STM32F4_OTGFS_GINTSTS_USBRST    BSP_BIT32(12) // USB reset
95#define STM32F4_OTGFS_GINTSTS_USBSUSP   BSP_BIT32(11) // USB suspend
96#define STM32F4_OTGFS_GINTSTS_ESUSP     BSP_BIT32(10) // Early suspend
97#define STM32F4_OTGFS_GINTSTS_GONAKEFF  BSP_BIT32(7)  // Global OUT NAK effective
98#define STM32F4_OTGFS_GINTSTS_GINAKEFF  BSP_BIT32(6)  // Global IN non-periodic NAK effective
99#define STM32F4_OTGFS_GINTSTS_NPTXFE    BSP_BIT32(5)  // Non-periodic TX fifo empty
100#define STM32F4_OTGFS_GINTSTS_RXFLVL    BSP_BIT32(4)  // RX fifo non-empty
101#define STM32F4_OTGFS_GINTSTS_SOF       BSP_BIT32(3)  // Start of frame
102#define STM32F4_OTGFS_GINTSTS_OTGINT    BSP_BIT32(2)  // OTG interrupt
103#define STM32F4_OTGFS_GINTSTS_MMIS      BSP_BIT32(1)  // Mode mismatch interrupt
104#define STM32F4_OTGFS_GINTSTS_CMOD      BSP_BIT32(0)  // Current mode of operation
105
106  uint32_t gintmsk; // 0x18: Interrupt mask register
107
108  uint32_t grxstsr; // 0x1C: Receive status debug read
109
110  uint32_t grxstsp; // 0x20: OTG status read and pop
111#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24)  // Frame number
112#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24)
113#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val)  BSP_FLD32SET(reg, val, 21, 24)
114#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20)  // Packet status
115#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20)
116#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val)  BSP_FLD32SET(reg, val, 17, 20)
117#define PKTSTS_IN_DATA  (0x2)
118#define PKTSTS_IN_COMPLETE  (0x3)
119#define PKTSTS_TOGGLE_ERR (0x5)
120#define PKTSTS_HALTED (0x7)
121#define PKTSTS_OUTNAK (0x1)
122#define PKTSTS_OUT_DATA (0x2)
123#define PKTSTS_OUT_COMPLETE (0x3)
124#define PKTSTS_SETUP_COMPLETE (0x4)
125#define PKTSTS_SETUP_DATA (0x6)
126#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16)  // Data PID
127#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16)
128#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val)  BSP_FLD32SET(reg, val, 15, 16)
129#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0  STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0)
130#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1  STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1)
131#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2  STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2)
132#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3)
133#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count
134#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14)
135#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val)  BSP_FLD32SET(reg, val, 4, 14)
136#define STM32F4_OTGFS_GRXSTSP_CHNUM(val)  BSP_FLD32(val, 0, 3)  // Channel number
137#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg)  BSP_FLD32GET(reg, 0, 3)
138#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
139#define STM32F4_OTGFS_GRXSTSP_EPNUM(val)  BSP_FLD32(val, 0, 3)  // Endpoint number
140#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg)  BSP_FLD32GET(reg, 0, 3)
141#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
142
143  uint32_t grxfsiz; // 0x24: Receive FIFO size register
144#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15)
145#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15)
146#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val)  BSP_FLD32SET(reg, val, 0, 15)
147#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16
148#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256
149
150  uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size
151#define STM32F4_OTGFS_DIEPTXF_DEPTH(val)  BSP_FLD32(val, 16, 31)
152#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg)  BSP_FLD32GET(reg, 16, 31)
153#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
154#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16
155#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256
156#define STM32F4_OTGFS_DIEPTXF_SADDR(val)  BSP_FLD32(val, 0, 15)
157#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg)  BSP_FLD32GET(reg, 0, 15)
158#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
159
160  uint32_t resv2C;
161
162  uint32_t gi2cctl; // 0x30
163  uint32_t resv34;  // 0x34
164
165  uint32_t gccfg; // 0x38: General core configuration register
166#define STM32F4_OTGFS_GCCFG_NOVBUSSENS  BSP_BIT32(21) // Vbus sensing disable
167#define STM32F4_OTGFS_GCCFG_SOFOUTEN  BSP_BIT32(20) // SOF output enable
168#define STM32F4_OTGFS_GCCFG_VBUSBSEN  BSP_BIT32(19) // Vbus sensing "B" device
169#define STM32F4_OTGFS_GCCFG_VBUSASEN  BSP_BIT32(18) // Vbus sensing "A" device
170#define STM32F4_OTGFS_GCCFG_PWRDWN    BSP_BIT32(16) // Power down
171
172  uint32_t cid; // 0x3C: Product ID
173
174  uint32_t resv40[48];  // 0x40 - 0x9C
175
176  uint32_t hptxfsiz;  // 0x100
177
178  uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104
179
180} __attribute__ ((packed));
181typedef struct stm32f4_otgfs_s stm32f4_otgfs;
182
183struct stm32f4_otgfs_dregs_s {
184  uint32_t dcfg;  // 0x800
185#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12)  // Periodic frame interval
186#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12)
187#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val)  BSP_FLD32SET(reg, val, 11, 12)
188#define PFIVL_80 0
189#define PFIVL_85 1
190#define PFIVL_90 2
191#define PFIVL_95 3
192#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address
193#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10)
194#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val)  BSP_FLD32SET(reg, val, 4, 10)
195#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2)  // Non-zero-length status OUT handshake
196#define STM32F4_OTGFS_DCFG_DSPD(val)  BSP_FLD32(val, 0, 1)  // Device speed
197#define STM32F4_OTGFS_DCFG_DSPD_GET(reg)  BSP_FLD32GET(reg, 0, 1)
198#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
199#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3)
200
201  uint32_t dctl;  // 0x804
202#define STM32F4_OTGFS_DCTL_POPRGDNE   BSP_BIT32(11) // Power-on programming done
203#define STM32F4_OTGFS_DCTL_CGONAK     BSP_BIT32(10) // Clear global OUT NAK
204#define STM32F4_OTGFS_DCTL_SGONAK     BSP_BIT32(9)  // Set global OUT NAK
205#define STM32F4_OTGFS_DCTL_CGINAK     BSP_BIT32(8)  // Clear global IN NAK
206#define STM32F4_OTGFS_DCTL_SGINAK     BSP_BIT32(7)  // Set global IN NAK
207#define STM32F4_OTGFS_DCTL_TCTL(val)  BSP_FLD32(val, 4, 6)  // Test control
208#define STM32F4_OTGFS_DCTL_TCTL_GET(reg)  BSP_FLD32GET(reg, 4, 6)
209#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6)
210#define STM32F4_OTGFS_DCTL_GONSTS     BSP_BIT32(3)  // Global OUT NAK status
211#define STM32F4_OTGFS_DCTL_GINSTS     BSP_BIT32(2)  // Global IN NAK status
212#define STM32F4_OTGFS_DCTL_SDIS       BSP_BIT32(1)  // Soft disconnect
213#define STM32F4_OTGFS_DCTL_RWUSIG     BSP_BIT32(0)  // Remote wakeup signalling
214
215  uint32_t dsts;  // 0x808
216#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF
217#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21)
218#define STM32F4_OTGFS_DSTS_EERR       BSP_BIT32(3)  // Erratic error
219#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2)  // Enumerated speed
220#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2)
221#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3)
222#define STM32F4_OTGFS_DSTS_SUSPSTS    BSP_BIT32(0)  // Suspend status
223
224  uint32_t unused4; // 0x80C
225
226  uint32_t diepmsk; // 0x810
227
228  uint32_t doepmsk; // 0x814
229
230  uint32_t daint; // 0x818
231#define STM32F4_OTGFS_DAINT_OEPINT15    BSP_BIT32(31) // OUT endpoint 15 interrupt
232#define STM32F4_OTGFS_DAINT_OEPINT14    BSP_BIT32(30) // OUT endpoint 14 interrupt
233#define STM32F4_OTGFS_DAINT_OEPINT13    BSP_BIT32(29) // OUT endpoint 13 interrupt
234#define STM32F4_OTGFS_DAINT_OEPINT12    BSP_BIT32(28) // OUT endpoint 12 interrupt
235#define STM32F4_OTGFS_DAINT_OEPINT11    BSP_BIT32(27) // OUT endpoint 11 interrupt
236#define STM32F4_OTGFS_DAINT_OEPINT10    BSP_BIT32(26) // OUT endpoint 10 interrupt
237#define STM32F4_OTGFS_DAINT_OEPINT9     BSP_BIT32(25) // OUT endpoint 9 interrupt
238#define STM32F4_OTGFS_DAINT_OEPINT8     BSP_BIT32(24) // OUT endpoint 8 interrupt
239#define STM32F4_OTGFS_DAINT_OEPINT7     BSP_BIT32(23) // OUT endpoint 7 interrupt
240#define STM32F4_OTGFS_DAINT_OEPINT6     BSP_BIT32(22) // OUT endpoint 6 interrupt
241#define STM32F4_OTGFS_DAINT_OEPINT5     BSP_BIT32(21) // OUT endpoint 5 interrupt
242#define STM32F4_OTGFS_DAINT_OEPINT4     BSP_BIT32(20) // OUT endpoint 4 interrupt
243#define STM32F4_OTGFS_DAINT_OEPINT3     BSP_BIT32(19) // OUT endpoint 3 interrupt
244#define STM32F4_OTGFS_DAINT_OEPINT2     BSP_BIT32(18) // OUT endpoint 2 interrupt
245#define STM32F4_OTGFS_DAINT_OEPINT1     BSP_BIT32(17) // OUT endpoint 1 interrupt
246#define STM32F4_OTGFS_DAINT_OEPINT0     BSP_BIT32(16) // OUT endpoint 0 interrupt
247#define STM32F4_OTGFS_DAINT_IEPINT15    BSP_BIT32(15) // IN endpoint 15 interrupt
248#define STM32F4_OTGFS_DAINT_IEPINT14    BSP_BIT32(14) // IN endpoint 14 interrupt
249#define STM32F4_OTGFS_DAINT_IEPINT13    BSP_BIT32(13) // IN endpoint 13 interrupt
250#define STM32F4_OTGFS_DAINT_IEPINT12    BSP_BIT32(12) // IN endpoint 12 interrupt
251#define STM32F4_OTGFS_DAINT_IEPINT11    BSP_BIT32(11) // IN endpoint 11 interrupt
252#define STM32F4_OTGFS_DAINT_IEPINT10    BSP_BIT32(10) // IN endpoint 10 interrupt
253#define STM32F4_OTGFS_DAINT_IEPINT9     BSP_BIT32(9)  // IN endpoint 9 interrupt
254#define STM32F4_OTGFS_DAINT_IEPINT8     BSP_BIT32(8)  // IN endpoint 8 interrupt
255#define STM32F4_OTGFS_DAINT_IEPINT7     BSP_BIT32(7)  // IN endpoint 7 interrupt
256#define STM32F4_OTGFS_DAINT_IEPINT6     BSP_BIT32(6)  // IN endpoint 6 interrupt
257#define STM32F4_OTGFS_DAINT_IEPINT5     BSP_BIT32(5)  // IN endpoint 5 interrupt
258#define STM32F4_OTGFS_DAINT_IEPINT4     BSP_BIT32(4)  // IN endpoint 4 interrupt
259#define STM32F4_OTGFS_DAINT_IEPINT3     BSP_BIT32(3)  // IN endpoint 3 interrupt
260#define STM32F4_OTGFS_DAINT_IEPINT2     BSP_BIT32(2)  // IN endpoint 2 interrupt
261#define STM32F4_OTGFS_DAINT_IEPINT1     BSP_BIT32(1)  // IN endpoint 1 interrupt
262#define STM32F4_OTGFS_DAINT_IEPINT0     BSP_BIT32(0)  // IN endpoint 0 interrupt
263
264  uint32_t daintmsk;  // 0x81C
265#define STM32F4_OTGFS_DAINTMSK_OEPM(val)  BSP_FLD32(val, 16, 31)  // OUT endpoint interrupt mask
266#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg)  BSP_FLD32GET(reg, 16, 31)
267#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
268#define STM32F4_OTGFS_DAINTMSK_IEPM(val)  BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask
269#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg)  BSP_FLD32GET(reg, 0, 15)
270#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
271
272  uint32_t unused5[2];  // 0x820 - 0x824
273
274  uint32_t dvbusdis;  // 0x828
275#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val)  BSP_FLD32(val, 0, 15) // Device Vbus discharge time
276#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg)  BSP_FLD32GET(reg, 0, 15)
277#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
278
279  uint32_t dvbuspulse;  // 0x82C
280#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val)  BSP_FLD32(val, 0, 15) // Device Vbus pulsing time
281#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg)  BSP_FLD32GET(reg, 0, 15)
282#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
283
284  uint32_t unused6; // 0x830
285
286  uint32_t diepempmsk;  // 0x834
287#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15  BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask
288#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14  BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask
289#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13  BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask
290#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12  BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask
291#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11  BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask
292#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10  BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask
293#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9   BSP_BIT32(9)  // IN endpoint 9 TxFIFO empty interrupt mask
294#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8   BSP_BIT32(8)  // IN endpoint 8 TxFIFO empty interrupt mask
295#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7   BSP_BIT32(7)  // IN endpoint 7 TxFIFO empty interrupt mask
296#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6   BSP_BIT32(6)  // IN endpoint 6 TxFIFO empty interrupt mask
297#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5   BSP_BIT32(5)  // IN endpoint 5 TxFIFO empty interrupt mask
298#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4   BSP_BIT32(4)  // IN endpoint 4 TxFIFO empty interrupt mask
299#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3   BSP_BIT32(3)  // IN endpoint 3 TxFIFO empty interrupt mask
300#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2   BSP_BIT32(2)  // IN endpoint 2 TxFIFO empty interrupt mask
301#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1   BSP_BIT32(1)  // IN endpoint 1 TxFIFO empty interrupt mask
302#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0   BSP_BIT32(0)  // IN endpoint 0 TxFIFO empty interrupt mask
303
304} __attribute__ ((packed));
305typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs;
306
307struct stm32f4_otgfs_inepregs_s {
308  uint32_t diepctl;   // 0x900
309#define STM32F4_OTGFS_DIEPCTL_EPENA     BSP_BIT32(31) // Endpoint enable
310#define STM32F4_OTGFS_DIEPCTL_EPDIS     BSP_BIT32(30) // Endpoint disable
311#define STM32F4_OTGFS_DIEPCTL_SODDFRM   BSP_BIT32(29) // Set odd frame
312#define STM32F4_OTGFS_DIEPCTL_SD0PID    BSP_BIT32(28) // Set DATA0 PID / Set even frame
313#define STM32F4_OTGFS_DIEPCTL_SEVNFRM   BSP_BIT32(28) // Set DATA0 PID / Set even frame
314#define STM32F4_OTGFS_DIEPCTL_SNAK      BSP_BIT32(27) // Set NAK
315#define STM32F4_OTGFS_DIEPCTL_CNAK      BSP_BIT32(26) // Clear NAK
316#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25)  // TxFIFO number
317#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25)
318#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val)  BSP_FLD32SET(reg, val, 22, 25)
319#define STM32F4_OTGFS_DIEPCTL_STALL     BSP_BIT32(21) // Stall handshake
320#define STM32F4_OTGFS_DIEPCTL_EPTYP(val)  BSP_FLD32(val, 18, 19)  // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt
321#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg)  BSP_FLD32GET(reg, 18, 19)
322#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19)
323#define EPTYPE_CTRL 0
324#define EPTYPE_ISOC 1
325#define EPTYPE_BULK 2
326#define EPTYPE_INTR 3
327#define STM32F4_OTGFS_DIEPCTL_NAKSTS    BSP_BIT32(17) // NAK status
328#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID  BSP_BIT32(16) // Data PID / Even/odd frame
329#define STM32F4_OTGFS_DIEPCTL_USBAEP    BSP_BIT32(15) // USB active endpoint
330#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val)  BSP_FLD32(val, 0, 1)  // Maximum packet size (bytes)
331#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 1)
332#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
333#define EP0_MPSIZ_8   3
334#define EP0_MPSIZ_16  2
335#define EP0_MPSIZ_32  1
336#define EP0_MPSIZ_64  0
337#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8)
338#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16  STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16)
339#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32  STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32)
340#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64  STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64)
341#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val)  BSP_FLD32(val, 0, 10) // Maximum packet size (bytes)
342#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 10)
343#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
344
345  uint32_t reserved_04;
346
347  uint32_t diepint;   // 0x908
348#define STM32F4_OTGFS_DIEPINT_TXFE      BSP_BIT32(7)  // Transmit FIFO empty
349#define STM32F4_OTGFS_DIEPINT_INEPNE    BSP_BIT32(6)  // IN endpoint NAK effective
350#define STM32F4_OTGFS_DIEPINT_ITTXFE    BSP_BIT32(4)  // IN token received, TxFIFO empty
351#define STM32F4_OTGFS_DIEPINT_TOC       BSP_BIT32(3)  // Timeout condition
352#define STM32F4_OTGFS_DIEPINT_EPDISD    BSP_BIT32(1)  // Endpoint disabled
353#define STM32F4_OTGFS_DIEPINT_XFRC      BSP_BIT32(0)  // Transfer complete
354
355  uint32_t reserved_0C;
356
357  uint32_t dieptsiz;  // 0x910
358#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val)  BSP_FLD32(val, 19, 20)  // EP0 packet count
359#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg)  BSP_FLD32GET(reg, 19, 20)
360#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20)
361#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val)  BSP_FLD32(val, 0, 6)  // EP0 transfer size
362#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 6)
363#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
364#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val)  BSP_FLD32(val, 29, 30)  // Multi count
365#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg)  BSP_FLD32GET(reg, 29, 30)
366#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30)
367#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val)  BSP_FLD32(val, 19, 28)  // Packet count
368#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg)  BSP_FLD32GET(reg, 19, 28)
369#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28)
370#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val)  BSP_FLD32(val, 0, 18) // Transfer size
371#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 18)
372#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18)
373
374  uint32_t reserved_14;
375
376  uint32_t dtxfsts;   // 0x918
377#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val)  BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available
378#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg)  BSP_FLD32(reg, 0, 15)
379#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
380
381  uint32_t reserved_1C;
382
383} __attribute__ ((packed));
384typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs;
385
386struct stm32f4_otgfs_outepregs_s {
387  uint32_t doepctl; // 0xBx0: Endpoint control register
388#define STM32F4_OTGFS_DOEPCTL_EPENA     BSP_BIT32(31) // Endpoint enable
389#define STM32F4_OTGFS_DOEPCTL_EPDIS     BSP_BIT32(30) // Endpoint disable
390#define STM32F4_OTGFS_DOEPCTL_SD1PID    BSP_BIT32(29) // Set DATA1 PID / Set odd frame
391#define STM32F4_OTGFS_DOEPCTL_SD0PID    BSP_BIT32(28) // Set DATA0 PID / Set even frame
392#define STM32F4_OTGFS_DOEPCTL_SNAK      BSP_BIT32(27) // Set NAK
393#define STM32F4_OTGFS_DOEPCTL_CNAK      BSP_BIT32(26) // Clear NAK
394#define STM32F4_OTGFS_DOEPCTL_STALL     BSP_BIT32(21) // Stall handshake
395#define STM32F4_OTGFS_DOEPCTL_SNPM      BSP_BIT32(20) // Snoop mode
396#define STM32F4_OTGFS_DOEPCTL_EPTYP(val)  BSP_FLD32(val, 18, 19)  // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt
397#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg)  BSP_FLD32GET(reg, 18, 19)
398#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19)
399#define STM32F4_OTGFS_DOEPCTL_NAKSTS    BSP_BIT32(17) // NAK status
400#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID  BSP_BIT32(16) // Data PID / Even/odd frame
401#define STM32F4_OTGFS_DOEPCTL_USBAEP    BSP_BIT32(15) // USB active endpoint
402#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val)  BSP_FLD32(val, 0, 10) // Maximum packet size (bytes)
403#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 10)
404#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
405
406  uint32_t resv04;
407
408  uint32_t doepint; // 0xBx8: Endpoint interrupt register
409#define STM32F4_OTGFS_DOEPINT_B2BSTUP   BSP_BIT32(6)  // Back-to-back SETUP packets received
410#define STM32F4_OTGFS_DOEPINT_OTEPDIS   BSP_BIT32(4)  // OUT token received when endpoint disabled
411#define STM32F4_OTGFS_DOEPINT_STUP      BSP_BIT32(3)  // SETUP phase done
412#define STM32F4_OTGFS_DOEPINT_EPDISD    BSP_BIT32(1)  // Endpoint disabled interrupt
413#define STM32F4_OTGFS_DOEPINT_XFRC      BSP_BIT32(0)  // Transfer complete
414
415  uint32_t doeptsiz;  // 0xBy0
416#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30)  // EP0 SETUP packet count
417#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30)
418#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val)  BSP_FLD32SET(reg, val, 29, 30)
419#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT   BSP_BIT32(19) // EP0 packet count
420#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val)  BSP_FLD32(val, 0, 6)  // EP0 transfer size
421#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 6)
422#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
423#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val)  BSP_FLD32(val, 29, 30)  // Received data PID
424#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg)  BSP_FLD32GET(reg, 29, 30)
425#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30)
426#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val)  BSP_FLD32(val, 19, 28)  // Packet count
427#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg)  BSP_FLD32GET(reg, 19, 28)
428#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28)
429#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val)  BSP_FLD32(val, 0, 18) // Transfer size
430#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg)  BSP_FLD32GET(reg, 0, 18)
431#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18)
432
433  uint32_t resv14[3];
434} __attribute__ ((packed));
435typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs;
436
437struct stm32f4_otgfs_pwrctlregs_s {
438  uint32_t pcgcctl;   // 0xE00: Power and clock gating control register
439#define STM32F4_OTGFS_PCGCCTL_PHYSUSP   BSP_BIT32(4)  // PHY suspend
440#define STM32F4_OTGFS_PCGCCTL_GATEHCLK  BSP_BIT32(1)  // Gate HCLK
441#define STM32F4_OTGFS_PCGCCTL_STPPCLK   BSP_BIT32(0)  // Stop PHY clk
442} __attribute__ ((packed));
443typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs;
444
445#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */
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