1 | /* |
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2 | * Copyright (c) 2013 Chris Nott. All rights reserved. |
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3 | * |
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4 | * Virtual Logic |
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5 | * 21-25 King St. |
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6 | * Rockdale NSW 2216 |
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7 | * Australia |
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8 | * <rtems@vl.com.au> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H |
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16 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H |
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17 | |
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18 | #include <bsp/utility.h> |
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19 | |
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20 | #define USB_OTG_NUM_EPS 4 |
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21 | #define USB_OTG_MAX_TX_FIFOS 4 |
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22 | |
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23 | #define USB_FIFO_BASE 0x1000 |
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24 | #define USB_FIFO_OFFS 0x1000 |
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25 | |
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26 | struct stm32f4_otgfs_s { |
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27 | uint32_t gotgctl; // 0x00: Control and status register |
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28 | #define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid |
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29 | #define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid |
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30 | #define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time |
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31 | #define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status |
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32 | #define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable |
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33 | #define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable |
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34 | #define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request |
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35 | #define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status |
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36 | #define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request |
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37 | #define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success |
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38 | |
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39 | uint32_t gotgint; // 0x04: Interrupt register |
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40 | #define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done |
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41 | #define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change |
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42 | #define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected |
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43 | #define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change |
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44 | #define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change |
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45 | #define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected |
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46 | |
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47 | uint32_t gahbcfg; // 0x08: AHB configuration register |
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48 | #define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level |
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49 | #define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level |
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50 | #define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask |
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51 | |
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52 | uint32_t gusbcfg; // 0x0C: USB configuration register |
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53 | #define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet |
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54 | #define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode |
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55 | #define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode |
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56 | #define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time |
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57 | #define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13) |
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58 | #define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) |
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59 | #define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable |
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60 | #define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable |
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61 | #define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select |
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62 | #define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration |
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63 | #define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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64 | #define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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65 | |
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66 | uint32_t grstctl; // 0x10: Reset register |
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67 | #define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle |
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68 | #define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number |
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69 | #define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10) |
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70 | #define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) |
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71 | #define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10) |
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72 | #define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush |
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73 | #define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush |
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74 | #define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset |
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75 | #define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset |
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76 | #define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset |
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77 | |
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78 | uint32_t gintsts; // 0x14: Core interrupt register |
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79 | #define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt |
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80 | #define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt |
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81 | #define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt |
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82 | #define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change |
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83 | #define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty |
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84 | #define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt |
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85 | #define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt |
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86 | #define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer |
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87 | #define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer |
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88 | #define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer |
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89 | #define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt |
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90 | #define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt |
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91 | #define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt |
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92 | #define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt |
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93 | #define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done |
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94 | #define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset |
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95 | #define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend |
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96 | #define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend |
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97 | #define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective |
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98 | #define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective |
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99 | #define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty |
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100 | #define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty |
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101 | #define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame |
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102 | #define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt |
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103 | #define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt |
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104 | #define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation |
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105 | |
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106 | uint32_t gintmsk; // 0x18: Interrupt mask register |
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107 | |
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108 | uint32_t grxstsr; // 0x1C: Receive status debug read |
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109 | |
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110 | uint32_t grxstsp; // 0x20: OTG status read and pop |
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111 | #define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number |
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112 | #define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24) |
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113 | #define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24) |
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114 | #define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status |
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115 | #define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20) |
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116 | #define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20) |
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117 | #define PKTSTS_IN_DATA (0x2) |
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118 | #define PKTSTS_IN_COMPLETE (0x3) |
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119 | #define PKTSTS_TOGGLE_ERR (0x5) |
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120 | #define PKTSTS_HALTED (0x7) |
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121 | #define PKTSTS_OUTNAK (0x1) |
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122 | #define PKTSTS_OUT_DATA (0x2) |
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123 | #define PKTSTS_OUT_COMPLETE (0x3) |
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124 | #define PKTSTS_SETUP_COMPLETE (0x4) |
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125 | #define PKTSTS_SETUP_DATA (0x6) |
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126 | #define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID |
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127 | #define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16) |
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128 | #define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16) |
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129 | #define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0) |
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130 | #define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1) |
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131 | #define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2) |
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132 | #define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3) |
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133 | #define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count |
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134 | #define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14) |
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135 | #define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14) |
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136 | #define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number |
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137 | #define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) |
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138 | #define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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139 | #define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number |
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140 | #define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) |
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141 | #define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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142 | |
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143 | uint32_t grxfsiz; // 0x24: Receive FIFO size register |
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144 | #define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15) |
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145 | #define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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146 | #define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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147 | #define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16 |
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148 | #define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256 |
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149 | |
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150 | uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size |
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151 | #define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31) |
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152 | #define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31) |
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153 | #define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) |
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154 | #define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16 |
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155 | #define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256 |
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156 | #define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15) |
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157 | #define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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158 | #define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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159 | |
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160 | uint32_t resv2C; |
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161 | |
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162 | uint32_t gi2cctl; // 0x30 |
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163 | uint32_t resv34; // 0x34 |
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164 | |
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165 | uint32_t gccfg; // 0x38: General core configuration register |
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166 | #define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable |
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167 | #define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable |
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168 | #define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device |
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169 | #define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device |
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170 | #define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down |
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171 | |
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172 | uint32_t cid; // 0x3C: Product ID |
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173 | |
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174 | uint32_t resv40[48]; // 0x40 - 0x9C |
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175 | |
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176 | uint32_t hptxfsiz; // 0x100 |
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177 | |
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178 | uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104 |
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179 | |
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180 | } __attribute__ ((packed)); |
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181 | typedef struct stm32f4_otgfs_s stm32f4_otgfs; |
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182 | |
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183 | struct stm32f4_otgfs_dregs_s { |
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184 | uint32_t dcfg; // 0x800 |
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185 | #define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval |
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186 | #define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12) |
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187 | #define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) |
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188 | #define PFIVL_80 0 |
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189 | #define PFIVL_85 1 |
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190 | #define PFIVL_90 2 |
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191 | #define PFIVL_95 3 |
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192 | #define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address |
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193 | #define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10) |
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194 | #define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10) |
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195 | #define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake |
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196 | #define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed |
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197 | #define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1) |
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198 | #define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) |
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199 | #define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3) |
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200 | |
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201 | uint32_t dctl; // 0x804 |
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202 | #define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done |
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203 | #define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK |
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204 | #define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK |
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205 | #define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK |
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206 | #define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK |
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207 | #define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control |
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208 | #define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6) |
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209 | #define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6) |
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210 | #define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status |
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211 | #define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status |
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212 | #define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect |
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213 | #define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling |
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214 | |
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215 | uint32_t dsts; // 0x808 |
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216 | #define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF |
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217 | #define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21) |
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218 | #define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error |
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219 | #define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed |
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220 | #define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2) |
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221 | #define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3) |
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222 | #define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status |
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223 | |
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224 | uint32_t unused4; // 0x80C |
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225 | |
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226 | uint32_t diepmsk; // 0x810 |
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227 | |
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228 | uint32_t doepmsk; // 0x814 |
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229 | |
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230 | uint32_t daint; // 0x818 |
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231 | #define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt |
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232 | #define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt |
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233 | #define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt |
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234 | #define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt |
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235 | #define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt |
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236 | #define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt |
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237 | #define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt |
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238 | #define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt |
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239 | #define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt |
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240 | #define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt |
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241 | #define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt |
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242 | #define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt |
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243 | #define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt |
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244 | #define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt |
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245 | #define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt |
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246 | #define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt |
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247 | #define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt |
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248 | #define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt |
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249 | #define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt |
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250 | #define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt |
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251 | #define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt |
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252 | #define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt |
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253 | #define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt |
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254 | #define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt |
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255 | #define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt |
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256 | #define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt |
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257 | #define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt |
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258 | #define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt |
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259 | #define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt |
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260 | #define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt |
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261 | #define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt |
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262 | #define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt |
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263 | |
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264 | uint32_t daintmsk; // 0x81C |
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265 | #define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask |
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266 | #define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31) |
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267 | #define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) |
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268 | #define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask |
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269 | #define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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270 | #define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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271 | |
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272 | uint32_t unused5[2]; // 0x820 - 0x824 |
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273 | |
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274 | uint32_t dvbusdis; // 0x828 |
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275 | #define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time |
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276 | #define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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277 | #define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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278 | |
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279 | uint32_t dvbuspulse; // 0x82C |
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280 | #define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time |
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281 | #define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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282 | #define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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283 | |
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284 | uint32_t unused6; // 0x830 |
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285 | |
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286 | uint32_t diepempmsk; // 0x834 |
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287 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask |
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288 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask |
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289 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask |
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290 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask |
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291 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask |
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292 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask |
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293 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask |
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294 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask |
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295 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask |
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296 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask |
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297 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask |
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298 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask |
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299 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask |
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300 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask |
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301 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask |
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302 | #define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask |
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303 | |
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304 | } __attribute__ ((packed)); |
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305 | typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs; |
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306 | |
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307 | struct stm32f4_otgfs_inepregs_s { |
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308 | uint32_t diepctl; // 0x900 |
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309 | #define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable |
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310 | #define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable |
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311 | #define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame |
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312 | #define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame |
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313 | #define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame |
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314 | #define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK |
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315 | #define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK |
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316 | #define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number |
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317 | #define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25) |
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318 | #define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25) |
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319 | #define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake |
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320 | #define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt |
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321 | #define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) |
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322 | #define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) |
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323 | #define EPTYPE_CTRL 0 |
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324 | #define EPTYPE_ISOC 1 |
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325 | #define EPTYPE_BULK 2 |
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326 | #define EPTYPE_INTR 3 |
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327 | #define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status |
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328 | #define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame |
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329 | #define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint |
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330 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes) |
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331 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1) |
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332 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) |
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333 | #define EP0_MPSIZ_8 3 |
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334 | #define EP0_MPSIZ_16 2 |
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335 | #define EP0_MPSIZ_32 1 |
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336 | #define EP0_MPSIZ_64 0 |
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337 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8) |
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338 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16) |
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339 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32) |
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340 | #define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64) |
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341 | #define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) |
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342 | #define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) |
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343 | #define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) |
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344 | |
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345 | uint32_t reserved_04; |
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346 | |
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347 | uint32_t diepint; // 0x908 |
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348 | #define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty |
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349 | #define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective |
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350 | #define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty |
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351 | #define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition |
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352 | #define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled |
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353 | #define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete |
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354 | |
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355 | uint32_t reserved_0C; |
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356 | |
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357 | uint32_t dieptsiz; // 0x910 |
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358 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count |
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359 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20) |
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360 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20) |
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361 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size |
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362 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) |
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363 | #define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) |
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364 | #define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count |
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365 | #define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) |
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366 | #define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) |
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367 | #define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count |
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368 | #define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) |
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369 | #define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) |
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370 | #define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size |
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371 | #define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) |
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372 | #define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) |
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373 | |
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374 | uint32_t reserved_14; |
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375 | |
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376 | uint32_t dtxfsts; // 0x918 |
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377 | #define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available |
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378 | #define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15) |
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379 | #define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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380 | |
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381 | uint32_t reserved_1C; |
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382 | |
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383 | } __attribute__ ((packed)); |
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384 | typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs; |
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385 | |
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386 | struct stm32f4_otgfs_outepregs_s { |
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387 | uint32_t doepctl; // 0xBx0: Endpoint control register |
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388 | #define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable |
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389 | #define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable |
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390 | #define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame |
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391 | #define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame |
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392 | #define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK |
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393 | #define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK |
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394 | #define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake |
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395 | #define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode |
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396 | #define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt |
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397 | #define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) |
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398 | #define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) |
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399 | #define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status |
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400 | #define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame |
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401 | #define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint |
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402 | #define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) |
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403 | #define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) |
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404 | #define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) |
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405 | |
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406 | uint32_t resv04; |
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407 | |
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408 | uint32_t doepint; // 0xBx8: Endpoint interrupt register |
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409 | #define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received |
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410 | #define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled |
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411 | #define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done |
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412 | #define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt |
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413 | #define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete |
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414 | |
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415 | uint32_t doeptsiz; // 0xBy0 |
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416 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count |
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417 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) |
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418 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) |
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419 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count |
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420 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size |
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421 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) |
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422 | #define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) |
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423 | #define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID |
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424 | #define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30) |
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425 | #define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) |
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426 | #define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count |
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427 | #define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) |
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428 | #define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) |
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429 | #define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size |
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430 | #define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) |
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431 | #define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) |
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432 | |
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433 | uint32_t resv14[3]; |
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434 | } __attribute__ ((packed)); |
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435 | typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs; |
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436 | |
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437 | struct stm32f4_otgfs_pwrctlregs_s { |
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438 | uint32_t pcgcctl; // 0xE00: Power and clock gating control register |
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439 | #define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend |
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440 | #define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK |
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441 | #define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk |
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442 | } __attribute__ ((packed)); |
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443 | typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs; |
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444 | |
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445 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */ |
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