1 | /* |
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2 | * Copyright (c) 2013 Chris Nott. All rights reserved. |
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3 | * |
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4 | * Virtual Logic |
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5 | * 21-25 King St. |
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6 | * Rockdale NSW 2216 |
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7 | * Australia |
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8 | * <rtems@vl.com.au> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H |
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16 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H |
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17 | |
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18 | #include <bsp/utility.h> |
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19 | |
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20 | struct stm32f4_flash_s { |
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21 | |
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22 | uint32_t acr; // Access and control register |
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23 | #define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset |
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24 | #define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset |
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25 | #define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable |
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26 | #define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable |
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27 | #define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable |
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28 | #define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency |
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29 | #define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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30 | #define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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31 | |
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32 | uint32_t keyr; // Key register |
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33 | #define STM32F4_FLASH_KEYR_KEY1 0x45670123 |
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34 | #define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB |
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35 | |
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36 | uint32_t optkeyr; // Option key register |
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37 | #define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B |
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38 | #define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F |
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39 | |
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40 | uint32_t sr; // Status register |
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41 | #define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy |
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42 | #define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error |
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43 | #define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error |
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44 | #define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error |
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45 | #define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error |
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46 | #define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error |
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47 | #define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation |
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48 | |
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49 | uint32_t cr; // Control register |
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50 | #define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock |
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51 | #define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable |
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52 | #define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable |
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53 | #define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start |
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54 | #define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size |
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55 | #define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9) |
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56 | #define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) |
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57 | #define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number |
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58 | #define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6) |
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59 | #define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6) |
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60 | #define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase |
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61 | #define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase |
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62 | #define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming |
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63 | |
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64 | uint32_t optcr; // Option control register |
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65 | #define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect |
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66 | #define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27) |
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67 | #define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27) |
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68 | #define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect |
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69 | #define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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70 | #define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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71 | #define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes |
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72 | #define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7) |
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73 | #define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) |
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74 | #define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level |
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75 | #define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3) |
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76 | #define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) |
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77 | #define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start |
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78 | #define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock |
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79 | |
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80 | } __attribute__ ((packed)); |
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81 | typedef struct stm32f4_flash_s stm32f4_flash; |
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82 | |
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83 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ |
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