source: rtems/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h @ 040ed0b4

4.11
Last change on this file since 040ed0b4 was 040ed0b4, checked in by Chris Nott <chrisn@…>, on Oct 18, 2014 at 8:55:37 AM

bsp/stm32f4: Add header files

Added register definition headers for STM32F4 ADC, EXTI, PWR, SYSCFG,
TIM, OTGFS and updated FLASH and RCC. Fixed PLL_Q for USB 48MHz
operation. Added flash prefetch enable.

  • Property mode set to 100755
File size: 3.9 KB
Line 
1/*
2 * Copyright (c) 2013 Chris Nott.  All rights reserved.
3 *
4 *  Virtual Logic
5 *  21-25 King St.
6 *  Rockdale NSW 2216
7 *  Australia
8 *  <rtems@vl.com.au>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H
16#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H
17
18#include <bsp/utility.h>
19
20struct stm32f4_flash_s {
21
22  uint32_t acr;   // Access and control register
23#define STM32F4_FLASH_ACR_DCRST   BSP_BIT32(12) // Data cache reset
24#define STM32F4_FLASH_ACR_ICRST   BSP_BIT32(11) // Instruction cache reset
25#define STM32F4_FLASH_ACR_DCEN    BSP_BIT32(10) // Data cache enable
26#define STM32F4_FLASH_ACR_ICEN    BSP_BIT32(9)  // Instruction cache enable
27#define STM32F4_FLASH_ACR_PRFTEN  BSP_BIT32(8)  // Prefetch enable
28#define STM32F4_FLASH_ACR_LATENCY(val)  BSP_FLD32(val, 0, 2)  // Flash access latency
29#define STM32F4_FLASH_ACR_LATENCY_GET(reg)  BSP_FLD32GET(reg, 0, 2)
30#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
31
32  uint32_t keyr;  // Key register
33#define STM32F4_FLASH_KEYR_KEY1 0x45670123
34#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB
35
36  uint32_t optkeyr; // Option key register
37#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B
38#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F
39
40  uint32_t sr;    // Status register
41#define STM32F4_FLASH_SR_BSY    BSP_BIT32(16) // Busy
42#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7)  // Programming sequence error
43#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6)  // Programming parallelism error
44#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5)  // Programming alignment error
45#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4)  // Write protection error
46#define STM32F4_FLASH_SR_OPERR  BSP_BIT32(1)  // Operation error
47#define STM32F4_FLASH_SR_EOP    BSP_BIT32(0)  // End of operation
48
49  uint32_t cr;    // Control register
50#define STM32F4_FLASH_CR_LOCK   BSP_BIT32(31) // Lock
51#define STM32F4_FLASH_CR_ERRIE  BSP_BIT32(25) // Error interrupt enable
52#define STM32F4_FLASH_CR_EOPIE  BSP_BIT32(24) // End of operation interrupt enable
53#define STM32F4_FLASH_CR_STRT   BSP_BIT32(16) // Start
54#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9)  // Program size
55#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9)
56#define STM32F4_FLASH_CR_PSIZE_SET(reg, val)  BSP_FLD32SET(reg, val, 8, 9)
57#define STM32F4_FLASH_CR_SNB  BSP_FLD32(val, 3, 6)  // Sector number
58#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6)
59#define STM32F4_FLASH_CR_SNB_SET(reg, val)  BSP_FLD32SET(reg, val, 3, 6)
60#define STM32F4_FLASH_CR_MER    BSP_BIT32(2)  // Mass erase
61#define STM32F4_FLASH_CR_SER    BSP_BIT32(1)  // Sector erase
62#define STM32F4_FLASH_CR_PG     BSP_BIT32(0)  // Programming
63
64  uint32_t optcr;   // Option control register
65#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27)  // Not write protect
66#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27)
67#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val)  BSP_FLD32SET(reg, val, 16, 27)
68#define STM32F4_FLASH_OPTCR_RDP(val)  BSP_FLD32(val, 8, 15) // Read protect
69#define STM32F4_FLASH_OPTCR_RDP_GET(reg)  BSP_FLD32GET(reg, 8, 15)
70#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
71#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7)  // User option bytes
72#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7)
73#define STM32F4_FLASH_OPTCR_USER_SET(reg, val)  BSP_FLD32SET(reg, val, 5, 7)
74#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val)  BSP_FLD32(val, 2, 3)  // BOR reset level
75#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg)  BSP_FLD32GET(reg, 2, 3)
76#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
77#define STM32F4_FLASH_CR_OPTSTRT  BSP_BIT32(1)  // Option start
78#define STM32F4_FLASH_CR_OPTLOCK  BSP_BIT32(0)  // Option lock
79
80} __attribute__ ((packed));
81typedef struct stm32f4_flash_s stm32f4_flash;
82
83#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */
Note: See TracBrowser for help on using the repository browser.