1 | /* |
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2 | * Copyright (c) 2014 Chris Nott. All rights reserved. |
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3 | * |
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4 | * Virtual Logic |
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5 | * 21-25 King St. |
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6 | * Rockdale NSW 2216 |
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7 | * Australia |
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8 | * <rtems@vl.com.au> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H |
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16 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H |
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17 | |
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18 | #include <bsp/utility.h> |
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19 | |
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20 | struct stm32f4_adc_chan_s { |
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21 | uint32_t sr; // 0x00: Status register |
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22 | #define STM32F4_ADC_SR_OVR BSP_BIT32(5) // Overrun |
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23 | #define STM32F4_ADC_SR_STRT BSP_BIT32(4) // Regular channel start flag |
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24 | #define STM32F4_ADC_SR_JSTRT BSP_BIT32(3) // Injected channel start flag |
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25 | #define STM32F4_ADC_SR_JEOC BSP_BIT32(2) // Injected channel end of conversion |
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26 | #define STM32F4_ADC_SR_EOC BSP_BIT32(1) // Regular channel end of conversion |
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27 | #define STM32F4_ADC_SR_AWD BSP_BIT32(0) // Analog watchdog flag |
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28 | |
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29 | uint32_t cr1; // 0x04: Control register 1 |
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30 | #define STM32F4_ADC_CR1_OVRIE BSP_BIT32(26) // Overrun interrupt enable |
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31 | #define STM32F4_ADC_CR1_RES(val) BSP_FLD32(val, 24, 25) // Resolution |
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32 | #define STM32F4_ADC_CR1_RES_GET(reg) BSP_FLD32GET(reg, 24, 25) |
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33 | #define STM32F4_ADC_CR1_RES_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) |
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34 | #define ADC_CR1_RES_12BIT 0 |
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35 | #define ADC_CR1_RES_10BIT 1 |
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36 | #define ADC_CR1_RES_8BIT 2 |
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37 | #define ADC_CR1_RES_6BIT 3 |
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38 | #define STM32F4_ADC_CR1_AWDEN BSP_BIT32(23) // Analog watchdog enable on regular channels |
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39 | #define STM32F4_ADC_CR1_JAWDEN BSP_BIT32(22) // Analog watchdog enable on injected channels |
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40 | #define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count |
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41 | #define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15) |
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42 | #define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) |
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43 | #define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels |
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44 | #define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels |
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45 | #define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion |
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46 | #define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode |
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47 | #define STM32F4_ADC_CR1_SCAN BSP_BIT32(8) // Scan mode |
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48 | #define STM32F4_ADC_CR1_JEOCIE BSP_BIT32(7) // Interrupt enable for injected channels |
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49 | #define STM32F4_ADC_CR1_AWDIE BSP_BIT32(6) // Analog watchdog interrupt enable |
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50 | #define STM32F4_ADC_CR1_EOCIE BSP_BIT32(5) // Interrupt enable for EOC |
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51 | #define STM32F4_ADC_CR1_AWDCH(val) BSP_FLD32(val, 0, 4) // Analog watchdog channel select bits |
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52 | #define STM32F4_ADC_CR1_AWDCH_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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53 | #define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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54 | |
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55 | uint32_t cr2; // 0x08: Control register 2 |
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56 | #define STM32F4_ADC_CR2_SWSTART BSP_BIT32(30) // Start conversion of regular channels |
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57 | #define STM32F4_ADC_CR2_EXTEN(val) BSP_FLD32(val, 28, 29) // External trigger enable for regular channels |
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58 | #define STM32F4_ADC_CR2_EXTEN_GET(reg) BSP_FLD32GET(reg, 28, 29) |
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59 | #define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29) |
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60 | #define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21) // External trigger enable for injected channels |
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61 | #define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21) |
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62 | #define STM32F4_ADC_CR2_JEXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) |
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63 | #define ADC_CR2_TRIGGER_DISABLE 0 |
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64 | #define ADC_CR2_TRIGGER_RISING 1 |
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65 | #define ADC_CR2_TRIGGER_FALLING 2 |
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66 | #define ADC_CR2_TRIGGER_BOTH 3 |
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67 | #define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27) // External event select for regular group |
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68 | #define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27) |
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69 | #define STM32F4_ADC_CR2_EXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) |
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70 | #define ADC_CR2_EVT_TIMER1_CC1 0x0 |
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71 | #define ADC_CR2_EVT_TIMER1_CC2 0x1 |
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72 | #define ADC_CR2_EVT_TIMER1_CC3 0x2 |
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73 | #define ADC_CR2_EVT_TIMER2_CC2 0x3 |
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74 | #define ADC_CR2_EVT_TIMER2_CC3 0x4 |
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75 | #define ADC_CR2_EVT_TIMER2_CC4 0x5 |
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76 | #define ADC_CR2_EVT_TIMER2_TRGO 0x6 |
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77 | #define ADC_CR2_EVT_TIMER3_CC1 0x7 |
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78 | #define ADC_CR2_EVT_TIMER3_TRGO 0x8 |
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79 | #define ADC_CR2_EVT_TIMER4_CC1 0x9 |
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80 | #define ADC_CR2_EVT_TIMER5_CC1 0xa |
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81 | #define ADC_CR2_EVT_TIMER5_CC2 0xb |
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82 | #define ADC_CR2_EVT_TIMER5_CC3 0xc |
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83 | #define ADC_CR2_EVT_TIMER8_CC1 0xd |
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84 | #define ADC_CR2_EVT_TIMER8_TRGO 0xe |
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85 | #define ADC_CR2_EVT_EXTI_11 0xf |
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86 | #define STM32F4_ADC_CR2_JSWSTART BSP_BIT32(22) // Start conversion of injected channels |
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87 | #define STM32F4_ADC_CR2_JEXTSEL(val) BSP_FLD32(val, 16, 19) // External event select for injected group |
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88 | #define STM32F4_ADC_CR2_JEXTSEL_GET(reg) BSP_FLD32GET(reg, 16, 19) |
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89 | #define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) |
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90 | #define ADC_CR2_JEVT_TIMER1_CC4 0x0 |
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91 | #define ADC_CR2_JEVT_TIMER1_TRGO 0x1 |
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92 | #define ADC_CR2_JEVT_TIMER2_CC1 0x2 |
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93 | #define ADC_CR2_JEVT_TIMER2_TRGO 0x3 |
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94 | #define ADC_CR2_JEVT_TIMER3_CC2 0x4 |
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95 | #define ADC_CR2_JEVT_TIMER3_CC4 0x5 |
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96 | #define ADC_CR2_JEVT_TIMER4_CC1 0x6 |
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97 | #define ADC_CR2_JEVT_TIMER4_CC2 0x7 |
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98 | #define ADC_CR2_JEVT_TIMER4_CC3 0x8 |
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99 | #define ADC_CR2_JEVT_TIMER4_TRGO 0x9 |
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100 | #define ADC_CR2_JEVT_TIMER5_CC4 0xa |
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101 | #define ADC_CR2_JEVT_TIMER5_TRGO 0xb |
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102 | #define ADC_CR2_JEVT_TIMER8_CC2 0xc |
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103 | #define ADC_CR2_JEVT_TIMER8_CC3 0xd |
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104 | #define ADC_CR2_JEVT_TIMER8_CC4 0xe |
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105 | #define ADC_CR2_JEVT_EXTI_15 0xf |
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106 | #define STM32F4_ADC_CR2_ALIGN BSP_BIT32(11) // Data alignment |
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107 | #define STM32F4_ADC_CR2_ALIGN_RIGHT 0 |
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108 | #define STM32F4_ADC_CR2_ALIGN_LEFT STM32F4_ADC_CR2_ALIGN |
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109 | #define STM32F4_ADC_CR2_EOCS BSP_BIT32(10) // End of conversion selection |
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110 | #define STM32F4_ADC_CR2_DDS BSP_BIT32(9) // DMA disable selection (single ADC mode) |
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111 | #define STM32F4_ADC_CR2_DMA BSP_BIT32(8) // DMA access mode (single ADC) |
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112 | #define STM32F4_ADC_CR2_CONT BSP_BIT32(1) // Continuous conversion |
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113 | #define STM32F4_ADC_CR2_ADON BSP_BIT32(0) // A/D converter ON |
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114 | |
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115 | uint32_t smpr1; // 0x0C: Sample time register 1 |
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116 | #define ADC_SAMPLE_3CYCLE 0 |
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117 | #define ADC_SAMPLE_15CYCLE 1 |
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118 | #define ADC_SAMPLE_28CYCLE 2 |
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119 | #define ADC_SAMPLE_56CYCLE 3 |
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120 | #define ADC_SAMPLE_84CYCLE 4 |
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121 | #define ADC_SAMPLE_112CYCLE 5 |
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122 | #define ADC_SAMPLE_144CYCLE 6 |
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123 | #define ADC_SAMPLE_480CYCLE 7 |
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124 | #define STM32F4_ADC_SMP18(val) BSP_FLD32(val, 24, 26) // Channel 18 sampling time selection |
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125 | #define STM32F4_ADC_SMP18_GET(reg) BSP_FLD32GET(reg, 24, 26) |
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126 | #define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) |
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127 | #define STM32F4_ADC_SMP17(val) BSP_FLD32(val, 21, 23) // Channel 17 sampling time selection |
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128 | #define STM32F4_ADC_SMP17_GET(reg) BSP_FLD32GET(reg, 21, 23) |
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129 | #define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) |
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130 | #define STM32F4_ADC_SMP16(val) BSP_FLD32(val, 18, 20) // Channel 16 sampling time selection |
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131 | #define STM32F4_ADC_SMP16_GET(reg) BSP_FLD32GET(reg, 18, 20) |
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132 | #define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) |
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133 | #define STM32F4_ADC_SMP15(val) BSP_FLD32(val, 15, 17) // Channel 15 sampling time selection |
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134 | #define STM32F4_ADC_SMP15_GET(reg) BSP_FLD32GET(reg, 15, 17) |
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135 | #define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) |
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136 | #define STM32F4_ADC_SMP14(val) BSP_FLD32(val, 12, 14) // Channel 14 sampling time selection |
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137 | #define STM32F4_ADC_SMP14_GET(reg) BSP_FLD32GET(reg, 12, 14) |
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138 | #define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) |
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139 | #define STM32F4_ADC_SMP13(val) BSP_FLD32(val, 9, 11) // Channel 13 sampling time selection |
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140 | #define STM32F4_ADC_SMP13_GET(reg) BSP_FLD32GET(reg, 9, 11) |
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141 | #define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) |
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142 | #define STM32F4_ADC_SMP12(val) BSP_FLD32(val, 6, 8) // Channel 12 sampling time selection |
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143 | #define STM32F4_ADC_SMP12_GET(reg) BSP_FLD32GET(reg, 6, 8) |
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144 | #define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) |
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145 | #define STM32F4_ADC_SMP11(val) BSP_FLD32(val, 3, 5) // Channel 11 sampling time selection |
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146 | #define STM32F4_ADC_SMP11_GET(reg) BSP_FLD32GET(reg, 3, 5) |
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147 | #define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) |
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148 | #define STM32F4_ADC_SMP10(val) BSP_FLD32(val, 0, 2) // Channel 10 sampling time selection |
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149 | #define STM32F4_ADC_SMP10_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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150 | #define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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151 | |
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152 | uint32_t smpr2; // 0x10: Sample time register 2 |
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153 | #define STM32F4_ADC_SMP9(val) BSP_FLD32(val, 27, 29) // Channel 9 sampling time selection |
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154 | #define STM32F4_ADC_SMP9_GET(reg) BSP_FLD32GET(reg, 27, 29) |
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155 | #define STM32F4_ADC_SMP9_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) |
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156 | #define STM32F4_ADC_SMP8(val) BSP_FLD32(val, 24, 26) // Channel 8 sampling time selection |
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157 | #define STM32F4_ADC_SMP8_GET(reg) BSP_FLD32GET(reg, 24, 26) |
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158 | #define STM32F4_ADC_SMP8_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) |
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159 | #define STM32F4_ADC_SMP7(val) BSP_FLD32(val, 21, 23) // Channel 7 sampling time selection |
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160 | #define STM32F4_ADC_SMP7_GET(reg) BSP_FLD32GET(reg, 21, 23) |
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161 | #define STM32F4_ADC_SMP7_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) |
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162 | #define STM32F4_ADC_SMP6(val) BSP_FLD32(val, 18, 20) // Channel 6 sampling time selection |
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163 | #define STM32F4_ADC_SMP6_GET(reg) BSP_FLD32GET(reg, 18, 20) |
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164 | #define STM32F4_ADC_SMP6_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) |
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165 | #define STM32F4_ADC_SMP5(val) BSP_FLD32(val, 15, 17) // Channel 5 sampling time selection |
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166 | #define STM32F4_ADC_SMP5_GET(reg) BSP_FLD32GET(reg, 15, 17) |
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167 | #define STM32F4_ADC_SMP5_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) |
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168 | #define STM32F4_ADC_SMP4(val) BSP_FLD32(val, 12, 14) // Channel 4 sampling time selection |
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169 | #define STM32F4_ADC_SMP4_GET(reg) BSP_FLD32GET(reg, 12, 14) |
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170 | #define STM32F4_ADC_SMP4_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) |
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171 | #define STM32F4_ADC_SMP3(val) BSP_FLD32(val, 9, 11) // Channel 3 sampling time selection |
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172 | #define STM32F4_ADC_SMP3_GET(reg) BSP_FLD32GET(reg, 9, 11) |
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173 | #define STM32F4_ADC_SMP3_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) |
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174 | #define STM32F4_ADC_SMP2(val) BSP_FLD32(val, 6, 8) // Channel 2 sampling time selection |
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175 | #define STM32F4_ADC_SMP2_GET(reg) BSP_FLD32GET(reg, 6, 8) |
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176 | #define STM32F4_ADC_SMP2_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) |
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177 | #define STM32F4_ADC_SMP1(val) BSP_FLD32(val, 3, 5) // Channel 1 sampling time selection |
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178 | #define STM32F4_ADC_SMP1_GET(reg) BSP_FLD32GET(reg, 3, 5) |
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179 | #define STM32F4_ADC_SMP1_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) |
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180 | #define STM32F4_ADC_SMP0(val) BSP_FLD32(val, 0, 2) // Channel 0 sampling time selection |
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181 | #define STM32F4_ADC_SMP0_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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182 | #define STM32F4_ADC_SMP0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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183 | |
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184 | uint32_t jofr[4]; // 0x14-0x20: Injected channel data offset registers |
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185 | #define STM32F4_ADC_JOFFSET(val) BSP_FLD32(val, 0, 11) // Data offset for injected channel |
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186 | #define STM32F4_ADC_JOFFSET_GET(reg) BSP_FLD32GET(reg, 0, 11) |
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187 | #define STM32F4_ADC_JOFFSET_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) |
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188 | |
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189 | uint32_t htr; // 0x24: Watchdog higher threshold register |
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190 | #define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11) // Analog watchdog higher threshold |
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191 | #define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11) |
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192 | #define STM32F4_ADC_HT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) |
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193 | |
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194 | uint32_t ltr; // 0x28: Watchdog lower threshold register |
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195 | #define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11) // Analog watchdog lower threshold |
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196 | #define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11) |
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197 | #define STM32F4_ADC_LT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) |
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198 | |
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199 | uint32_t sqr[3]; // 0x2c-0x34: Regular sequence registers |
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200 | #define STM32F4_ADC_SQR_L(val) BSP_FLD32(val, 20, 23) // Regular channel sequence length |
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201 | #define STM32F4_ADC_SQR_L_GET(reg) BSP_FLD32GET(reg, 20, 23) |
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202 | #define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) |
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203 | |
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204 | uint32_t jsqr; // 0x38: Injected sequence register |
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205 | #define STM32F4_ADC_JSQR_JL(val) BSP_FLD32(val, 20, 21) // Injected sequence length |
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206 | #define STM32F4_ADC_JSQR_JL_GET(reg) BSP_FLD32GET(reg, 20, 21) |
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207 | #define STM32F4_ADC_JSQR_JL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) |
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208 | #define STM32F4_ADC_JSQR_JSQ4(val) BSP_FLD32(val, 15, 19) // 4th conversion in injected sequence |
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209 | #define STM32F4_ADC_JSQR_JSQ4_GET(reg) BSP_FLD32GET(reg, 15, 19) |
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210 | #define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19) |
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211 | #define STM32F4_ADC_JSQR_JSQ3(val) BSP_FLD32(val, 10, 14) // 3rd conversion in injected sequence |
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212 | #define STM32F4_ADC_JSQR_JSQ3_GET(reg) BSP_FLD32GET(reg, 10, 14) |
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213 | #define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14) |
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214 | #define STM32F4_ADC_JSQR_JSQ2(val) BSP_FLD32(val, 5, 9) // 2nd conversion in injected sequence |
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215 | #define STM32F4_ADC_JSQR_JSQ2_GET(reg) BSP_FLD32GET(reg, 5, 9) |
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216 | #define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9) |
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217 | #define STM32F4_ADC_JSQR_JSQ1(val) BSP_FLD32(val, 0, 4) // 1st conversion in injected sequence |
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218 | #define STM32F4_ADC_JSQR_JSQ1_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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219 | #define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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220 | |
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221 | uint32_t jdr[4]; // 0x3c-0x48: Injected data registers |
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222 | #define STM32F4_ADC_JDATA(val) BSP_FLD32(val, 0, 15) // Injected data |
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223 | #define STM32F4_ADC_JDATA_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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224 | #define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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225 | |
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226 | uint32_t dr; // 0x4c: Regular data register |
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227 | #define STM32F4_ADC_DATA(val) BSP_FLD32(val, 0, 15) // Regular data |
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228 | #define STM32F4_ADC_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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229 | #define STM32F4_ADC_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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230 | |
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231 | } __attribute__ ((packed)); |
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232 | typedef struct stm32f4_adc_chan_s stm32f4_adc_chan; |
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233 | |
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234 | struct stm32f4_adc_com_s { |
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235 | uint32_t csr; // 0x00: Common status register |
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236 | #define STM32F4_ADC_CSR_OVR3 BSP_BIT32(21) // Overrun flag ADC3 |
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237 | #define STM32F4_ADC_CSR_STRT3 BSP_BIT32(20) // Regular start flag ADC3 |
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238 | #define STM32F4_ADC_CSR_JSTRT3 BSP_BIT32(19) // Injected start flag ADC3 |
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239 | #define STM32F4_ADC_CSR_JEOC3 BSP_BIT32(18) // Injected channel end of conversion flag ADC3 |
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240 | #define STM32F4_ADC_CSR_EOC3 BSP_BIT32(17) // Channel end of conversion flag ADC3 |
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241 | #define STM32F4_ADC_CSR_AWD3 BSP_BIT32(16) // Analog watchdog flag ADC3 |
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242 | #define STM32F4_ADC_CSR_OVR2 BSP_BIT32(13) // Overrun flag ADC2 |
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243 | #define STM32F4_ADC_CSR_STRT2 BSP_BIT32(12) // Regular start flag ADC2 |
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244 | #define STM32F4_ADC_CSR_JSTRT2 BSP_BIT32(11) // Injected start flag ADC2 |
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245 | #define STM32F4_ADC_CSR_JEOC2 BSP_BIT32(10) // Injected channel end of conversion flag ADC2 |
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246 | #define STM32F4_ADC_CSR_EOC2 BSP_BIT32(9) // Channel end of conversion flag ADC2 |
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247 | #define STM32F4_ADC_CSR_AWD2 BSP_BIT32(8) // Analog watchdog flag ADC2 |
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248 | #define STM32F4_ADC_CSR_OVR1 BSP_BIT32(5) // Overrun flag ADC1 |
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249 | #define STM32F4_ADC_CSR_STRT1 BSP_BIT32(4) // Regular start flag ADC1 |
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250 | #define STM32F4_ADC_CSR_JSTRT1 BSP_BIT32(3) // Injected start flag ADC1 |
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251 | #define STM32F4_ADC_CSR_JEOC1 BSP_BIT32(2) // Injected channel end of conversion flag ADC1 |
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252 | #define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1 |
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253 | #define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1 |
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254 | |
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255 | uint32_t ccr; // 0x00: Common control register |
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256 | #define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable |
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257 | #define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable |
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258 | #define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar |
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259 | #define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17) |
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260 | #define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) |
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261 | #define ADC_ADCPRE_PCLK2_2 0 |
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262 | #define ADC_ADCPRE_PCLK2_4 1 |
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263 | #define ADC_ADCPRE_PCLK2_6 2 |
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264 | #define ADC_ADCPRE_PCLK2_8 3 |
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265 | #define STM32F4_ADC_CCR_DMA(val) BSP_FLD32(val, 14, 15) // DMA access mode for multi ADC |
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266 | #define STM32F4_ADC_CCR_DMA_GET(reg) BSP_FLD32GET(reg, 14, 15) |
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267 | #define STM32F4_ADC_CCR_DMA_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) |
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268 | #define ADC_DMA_DISABLE 0 |
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269 | #define ADC_DMA_MODE1 1 |
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270 | #define ADC_DMA_MODE2 2 |
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271 | #define ADC_DMA_MODE3 3 |
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272 | #define STM32F4_ADC_CCR_DDS BSP_BIT32(13) // DMA disable selection |
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273 | #define STM32F4_ADC_CCR_DELAY(val) BSP_FLD32(val, 8, 11) // Delay between sampling phases |
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274 | #define STM32F4_ADC_CCR_DELAY_GET(reg) BSP_FLD32GET(reg, 8, 11) |
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275 | #define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) |
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276 | #define ADC_DELAY_5T 0 |
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277 | #define ADC_DELAY_6T 1 |
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278 | #define ADC_DELAY_7T 2 |
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279 | #define ADC_DELAY_8T 3 |
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280 | #define ADC_DELAY_9T 4 |
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281 | #define ADC_DELAY_10T 5 |
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282 | #define ADC_DELAY_11T 6 |
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283 | #define ADC_DELAY_12T 7 |
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284 | #define ADC_DELAY_13T 8 |
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285 | #define ADC_DELAY_14T 9 |
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286 | #define ADC_DELAY_15T 10 |
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287 | #define ADC_DELAY_16T 11 |
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288 | #define ADC_DELAY_17T 12 |
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289 | #define ADC_DELAY_18T 13 |
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290 | #define ADC_DELAY_19T 14 |
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291 | #define ADC_DELAY_20T 15 |
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292 | #define STM32F4_ADC_CCR_MULTI(val) BSP_FLD32(val, 0, 4) // Multi ADC mode |
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293 | #define STM32F4_ADC_CCR_MULTI_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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294 | #define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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295 | #define ADC_MULTI_INDEPENDENT 0x00 |
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296 | #define ADC_MULTI_DUAL_REG_INJ 0x01 |
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297 | #define ADC_MULTI_DUAL_REG_ALT 0x02 |
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298 | #define ADC_MULTI_DUAL_INJ 0x05 |
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299 | #define ADC_MULTI_DUAL_REG 0x06 |
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300 | #define ADC_MULTI_DUAL_INTRL 0x07 |
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301 | #define ADC_MULTI_DUAL_ALT_TRIG 0x09 |
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302 | #define ADC_MULTI_TRIPLE_REG_INJ 0x11 |
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303 | #define ADC_MULTI_TRIPLE_REG_ALT 0x12 |
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304 | #define ADC_MULTI_TRIPLE_INJ 0x15 |
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305 | #define ADC_MULTI_TRIPLE_REG 0x16 |
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306 | #define ADC_MULTI_TRIPLE_INTRL 0x17 |
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307 | #define ADC_MULTI_TRIPLE_ALT_TRIG 0x19 |
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308 | |
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309 | uint32_t cdr; // 0x00: Common regular data register |
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310 | #define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item |
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311 | #define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31) |
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312 | #define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) |
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313 | #define STM32F4_ADC_CDR_DATA1(val) BSP_FLD32(val, 0, 15) // 1st data item |
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314 | #define STM32F4_ADC_CDR_DATA1_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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315 | #define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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316 | |
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317 | } __attribute__ ((packed)); |
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318 | typedef struct stm32f4_adc_com_s stm32f4_adc_com; |
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319 | |
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320 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */ |
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