source: rtems/c/src/lib/libbsp/arm/stm32f4/include/io.h @ 1485a58

4.115
Last change on this file since 1485a58 was 1485a58, checked in by Christian Mauderer <Christian.Mauderer@…>, on 09/18/13 at 13:44:42

bsp/stm32f4: Add STM32F10XXX support.
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File size: 10.9 KB
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[228ece9]1/*
2 * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_STM32F4_IO_H
16#define LIBBSP_ARM_STM32F4_IO_H
17
18#include <stdbool.h>
[1485a58]19#include <stdint.h>
20#include <bspopts.h>
[228ece9]21
22#ifdef __cplusplus
23extern "C" {
24#endif /* __cplusplus */
25
[1485a58]26#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
27
28#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
29
30#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
31
32#ifdef STM32F4_FAMILY_F4XXXX
33
[228ece9]34typedef enum {
35  STM32F4_GPIO_MODE_INPUT,
36  STM32F4_GPIO_MODE_OUTPUT,
37  STM32F4_GPIO_MODE_AF,
38  STM32F4_GPIO_MODE_ANALOG
39} stm32f4_gpio_mode;
40
41typedef enum {
42  STM32F4_GPIO_OTYPE_PUSH_PULL,
43  STM32F4_GPIO_OTYPE_OPEN_DRAIN
44} stm32f4_gpio_otype;
45
46typedef enum {
47  STM32F4_GPIO_OSPEED_2_MHZ,
48  STM32F4_GPIO_OSPEED_25_MHZ,
49  STM32F4_GPIO_OSPEED_50_MHZ,
50  STM32F4_GPIO_OSPEED_100_MHZ
51} stm32f4_gpio_ospeed;
52
53typedef enum {
54  STM32F4_GPIO_NO_PULL,
55  STM32F4_GPIO_PULL_UP,
56  STM32F4_GPIO_PULL_DOWN
57} stm32f4_gpio_pull;
58
59typedef enum {
60  STM32F4_GPIO_AF_SYSTEM = 0,
61  STM32F4_GPIO_AF_TIM1 = 1,
62  STM32F4_GPIO_AF_TIM2 = 1,
63  STM32F4_GPIO_AF_TIM3 = 2,
64  STM32F4_GPIO_AF_TIM4 = 2,
65  STM32F4_GPIO_AF_TIM5 = 2,
66  STM32F4_GPIO_AF_TIM8 = 3,
67  STM32F4_GPIO_AF_TIM9 = 3,
68  STM32F4_GPIO_AF_TIM10 = 3,
69  STM32F4_GPIO_AF_TIM11 = 3,
70  STM32F4_GPIO_AF_I2C1 = 4,
71  STM32F4_GPIO_AF_I2C2 = 4,
72  STM32F4_GPIO_AF_I2C3 = 4,
73  STM32F4_GPIO_AF_SPI1 = 5,
74  STM32F4_GPIO_AF_SPI2 = 5,
75  STM32F4_GPIO_AF_SPI3 = 6,
76  STM32F4_GPIO_AF_USART1 = 7,
77  STM32F4_GPIO_AF_USART2 = 7,
78  STM32F4_GPIO_AF_USART3 = 7,
79  STM32F4_GPIO_AF_UART4 = 8,
80  STM32F4_GPIO_AF_UART5 = 8,
81  STM32F4_GPIO_AF_USART6 = 8,
82  STM32F4_GPIO_AF_CAN1 = 9,
83  STM32F4_GPIO_AF_CAN2 = 9,
84  STM32F4_GPIO_AF_TIM12 = 9,
85  STM32F4_GPIO_AF_TIM13 = 9,
86  STM32F4_GPIO_AF_TIM14 = 9,
87  STM32F4_GPIO_AF_OTG_FS = 10,
88  STM32F4_GPIO_AF_OTG_HS = 10,
89  STM32F4_GPIO_AF_ETH = 11,
90  STM32F4_GPIO_AF_FSMC = 12,
91  STM32F4_GPIO_AF_OTG_HS_FS = 12,
92  STM32F4_GPIO_AF_SDIO = 12,
93  STM32F4_GPIO_AF_DCMI = 13,
94  STM32F4_GPIO_AF_EVENTOUT = 15
95} stm32f4_gpio_af;
96
[7be19f8]97typedef union {
98  struct {
99    uint32_t pin_first : 8;
100    uint32_t pin_last : 8;
101    uint32_t mode : 2;
102    uint32_t otype : 1;
103    uint32_t ospeed : 2;
104    uint32_t pupd : 2;
105    uint32_t output : 1;
106    uint32_t af : 4;
107    uint32_t reserved : 4;
108  } fields;
109
110  uint32_t value;
[228ece9]111} stm32f4_gpio_config;
112
[1485a58]113#define STM32F4_GPIO_CONFIG_TERMINAL \
114  { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
115
116#endif /* STM32F4_FAMILY_F4XXXX */
117#ifdef STM32F4_FAMILY_F10XXX
118
119typedef enum {
120  STM32F4_GPIO_MODE_INPUT,
121  STM32F4_GPIO_MODE_OUTPUT_10MHz,
122  STM32F4_GPIO_MODE_OUTPUT_2MHz,
123  STM32F4_GPIO_MODE_OUTPUT_50MHz
124} stm32f4_gpio_mode;
125
126typedef enum {
127  STM32F4_GPIO_CNF_IN_ANALOG = 0,
128  STM32F4_GPIO_CNF_IN_FLOATING = 1,
129  STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
130
131  STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
132  STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
133  STM32F4_GPIO_CNF_OUT_AF_PP = 2,
134  STM32F4_GPIO_CNF_OUT_AF_OD = 3,
135} stm32f4_gpio_cnf;
136
137typedef enum {
138  STM32F4_GPIO_REMAP_DONT_CHANGE,
139  STM32F4_GPIO_REMAP_SPI1_0,
140  STM32F4_GPIO_REMAP_SPI1_1,
141  STM32F4_GPIO_REMAP_I2C1_0,
142  STM32F4_GPIO_REMAP_I2C1_1,
143  STM32F4_GPIO_REMAP_USART1_0,
144  STM32F4_GPIO_REMAP_USART1_1,
145  STM32F4_GPIO_REMAP_USART2_0,
146  STM32F4_GPIO_REMAP_USART2_1,
147  STM32F4_GPIO_REMAP_USART3_0,
148  STM32F4_GPIO_REMAP_USART3_1,
149  STM32F4_GPIO_REMAP_USART3_3,
150  STM32F4_GPIO_REMAP_TIM1_0,
151  STM32F4_GPIO_REMAP_TIM1_1,
152  STM32F4_GPIO_REMAP_TIM1_3,
153  STM32F4_GPIO_REMAP_TIM2_0,
154  STM32F4_GPIO_REMAP_TIM2_1,
155  STM32F4_GPIO_REMAP_TIM2_2,
156  STM32F4_GPIO_REMAP_TIM2_3,
157  STM32F4_GPIO_REMAP_TIM3_0,
158  STM32F4_GPIO_REMAP_TIM3_2,
159  STM32F4_GPIO_REMAP_TIM3_3,
160  STM32F4_GPIO_REMAP_TIM4_0,
161  STM32F4_GPIO_REMAP_TIM4_1,
162  STM32F4_GPIO_REMAP_CAN1_0,
163  STM32F4_GPIO_REMAP_CAN1_2,
164  STM32F4_GPIO_REMAP_CAN1_3,
165  STM32F4_GPIO_REMAP_PD01_0,
166  STM32F4_GPIO_REMAP_PD01_1,
167  STM32F4_GPIO_REMAP_TIM5CH4_0,
168  STM32F4_GPIO_REMAP_TIM5CH4_1,
169  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
170  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
171  STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
172  STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
173  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
174  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
175  STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
176  STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
177  STM32F4_GPIO_REMAP_ETH_0,
178  STM32F4_GPIO_REMAP_ETH_1,
179  STM32F4_GPIO_REMAP_CAN2_0,
180  STM32F4_GPIO_REMAP_CAN2_1,
181  STM32F4_GPIO_REMAP_MII_RMII_0,
182  STM32F4_GPIO_REMAP_MII_RMII_1,
183  STM32F4_GPIO_REMAP_SWJ_0,
184  STM32F4_GPIO_REMAP_SWJ_1,
185  STM32F4_GPIO_REMAP_SWJ_2,
186  STM32F4_GPIO_REMAP_SWJ_4,
187  STM32F4_GPIO_REMAP_SPI3_0,
188  STM32F4_GPIO_REMAP_SPI3_1,
189  STM32F4_GPIO_REMAP_TIM2ITR1_0,
190  STM32F4_GPIO_REMAP_TIM2ITR1_1,
191  STM32F4_GPIO_REMAP_PTP_PPS_0,
192  STM32F4_GPIO_REMAP_PTP_PPS_1,
193  STM32F4_GPIO_REMAP_TIM15_0,
194  STM32F4_GPIO_REMAP_TIM15_1,
195  STM32F4_GPIO_REMAP_TIM16_0,
196  STM32F4_GPIO_REMAP_TIM16_1,
197  STM32F4_GPIO_REMAP_TIM17_0,
198  STM32F4_GPIO_REMAP_TIM17_1,
199  STM32F4_GPIO_REMAP_CEC_0,
200  STM32F4_GPIO_REMAP_CEC_1,
201  STM32F4_GPIO_REMAP_TIM1_DMA_0,
202  STM32F4_GPIO_REMAP_TIM1_DMA_1,
203  STM32F4_GPIO_REMAP_TIM9_0,
204  STM32F4_GPIO_REMAP_TIM9_1,
205  STM32F4_GPIO_REMAP_TIM10_0,
206  STM32F4_GPIO_REMAP_TIM10_1,
207  STM32F4_GPIO_REMAP_TIM11_0,
208  STM32F4_GPIO_REMAP_TIM11_1,
209  STM32F4_GPIO_REMAP_TIM13_0,
210  STM32F4_GPIO_REMAP_TIM13_1,
211  STM32F4_GPIO_REMAP_TIM14_0,
212  STM32F4_GPIO_REMAP_TIM14_1,
213  STM32F4_GPIO_REMAP_FSMC_0,
214  STM32F4_GPIO_REMAP_FSMC_1,
215  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
216  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
217  STM32F4_GPIO_REMAP_TIM12_0,
218  STM32F4_GPIO_REMAP_TIM12_1,
219  STM32F4_GPIO_REMAP_MISC_0,
220  STM32F4_GPIO_REMAP_MISC_1,
221} stm32f4_gpio_remap;
222
223typedef union {
224  struct {
225    uint32_t pin_first : 8;
226    uint32_t pin_last : 8;
227    uint32_t mode : 2;
228    uint32_t cnf : 2;
229    uint32_t output : 1;
230    uint32_t remap : 8;
231    uint32_t reserved : 3;
232  } fields;
233
234  uint32_t value;
235} stm32f4_gpio_config;
236
237#define STM32F4_GPIO_CONFIG_TERMINAL \
238  { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
239
240#endif /* STM32F4_FAMILY_F10XXX */
241
[7be19f8]242extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
243
244void stm32f4_gpio_set_clock(int pin, bool set);
245
[228ece9]246void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
247
[7be19f8]248/**
249 * @brief Sets the GPIO configuration of an array terminated by
250 * STM32F4_GPIO_CONFIG_TERMINAL.
251 */
252void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs);
253
[228ece9]254void stm32f4_gpio_set_output(int pin, bool set);
255
256bool stm32f4_gpio_get_input(int pin);
257
[1485a58]258#ifdef STM32F4_FAMILY_F4XXXX
259
[7be19f8]260#define STM32F4_PIN_USART(port, idx, altfunc) \
261  { \
262    { \
263      .pin_first = STM32F4_GPIO_PIN(port, idx), \
264      .pin_last = STM32F4_GPIO_PIN(port, idx), \
265      .mode = STM32F4_GPIO_MODE_AF, \
266      .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \
267      .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \
268      .pupd = STM32F4_GPIO_PULL_UP, \
269      .af = altfunc \
270    } \
271  }
272
273#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1)
274#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1)
275#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1)
276#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1)
277
278#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2)
279#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2)
280#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2)
281#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2)
282
283#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3)
284#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3)
285#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3)
286#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3)
287
288#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4)
289#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4)
290#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4)
291#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4)
292
293#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5)
294#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5)
295
296#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
297#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
298
[1485a58]299#endif /* STM32F4_FAMILY_F4XXXX */
300#ifdef STM32F4_FAMILY_F10XXX
301
302#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
303  { \
304    { \
305      .pin_first = STM32F4_GPIO_PIN(port, idx), \
306      .pin_last = STM32F4_GPIO_PIN(port, idx), \
307      .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
308      .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
309      .output = 0, \
310      .remap = remapvalue \
311    } \
312  }
313
314#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
315  { \
316    { \
317      .pin_first = STM32F4_GPIO_PIN(port, idx), \
318      .pin_last = STM32F4_GPIO_PIN(port, idx), \
319      .mode = STM32F4_GPIO_MODE_INPUT, \
320      .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
321      .output = 0, \
322      .remap = remapvalue \
323    } \
324  }
325
326#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0,  9, STM32F4_GPIO_REMAP_USART1_0)
327#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
328#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1,  6, STM32F4_GPIO_REMAP_USART1_1)
329#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1,  7, STM32F4_GPIO_REMAP_USART1_1)
330
331#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0,  2, STM32F4_GPIO_REMAP_USART2_0)
332#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0,  3, STM32F4_GPIO_REMAP_USART2_0)
333#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3,  5, STM32F4_GPIO_REMAP_USART2_1)
334#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3,  6, STM32F4_GPIO_REMAP_USART2_1)
335
336#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
337#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
338#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
339#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
340#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3,  8, STM32F4_GPIO_REMAP_USART3_3)
341#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3,  9, STM32F4_GPIO_REMAP_USART3_3)
342
343#define STM32F4_PIN_UART4_TX        STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
344#define STM32F4_PIN_UART4_RX        STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
345
346#define STM32F4_PIN_UART5_TX        STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
347#define STM32F4_PIN_UART5_RX        STM32F4_PIN_USART_RX(3,  2, STM32F4_GPIO_REMAP_DONT_CHANGE)
348
349#endif /* STM32F4_FAMILY_F10XXX */
350
[228ece9]351#ifdef __cplusplus
352}
353#endif /* __cplusplus */
354
355#endif /* LIBBSP_ARM_STM32F4_IO_H */
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