[c918737e] | 1 | /* |
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| 2 | * Copyright (c) 2013 Christian Mauderer. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Obere Lagerstr. 30 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <rtems@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[c918737e] | 13 | */ |
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| 14 | |
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| 15 | /* The I2C-module can not run with libi2c. The reason for this is, that libi2c |
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| 16 | * needs a possibility to generate a stop condition separately. This controller |
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| 17 | * wants to generate the condition automatically when sending or receiving data. |
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| 18 | */ |
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| 19 | |
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| 20 | #include <bsp.h> |
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| 21 | #include <bsp/i2c.h> |
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| 22 | #include <bsp/rcc.h> |
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| 23 | #include <bsp/irq.h> |
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| 24 | #include <bsp/irq-generic.h> |
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| 25 | #include <assert.h> |
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| 26 | |
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| 27 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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| 28 | |
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| 29 | #include <rtems/status-checks.h> |
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| 30 | |
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| 31 | #define STM32F4_I2C_INITIAL_BITRATE 100000 |
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| 32 | |
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| 33 | #define I2C_RW_BIT 0x1 |
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| 34 | |
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| 35 | stm32f4_rcc_index i2c_rcc_index [] = { |
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| 36 | STM32F4_RCC_I2C1, |
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| 37 | STM32F4_RCC_I2C2, |
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| 38 | }; |
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| 39 | |
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| 40 | static stm32f4_rcc_index i2c_get_rcc_index(stm32f4_i2c_bus_entry *e) |
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| 41 | { |
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| 42 | return i2c_rcc_index [e->index]; |
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| 43 | } |
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| 44 | |
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| 45 | static uint32_t i2c_get_pclk(stm32f4_i2c_bus_entry *e) |
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| 46 | { |
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| 47 | return STM32F4_PCLK1; |
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| 48 | } |
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| 49 | |
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| 50 | rtems_status_code stm32f4_i2c_set_bitrate( |
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| 51 | stm32f4_i2c_bus_entry *e, |
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| 52 | uint32_t br |
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| 53 | ) |
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| 54 | { |
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| 55 | volatile stm32f4_i2c *regs = e->regs; |
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| 56 | uint32_t ccr; |
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| 57 | uint32_t trise; |
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| 58 | uint32_t pclk = i2c_get_pclk(e); |
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| 59 | |
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| 60 | /* Make sure, that the module is disabled */ |
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| 61 | if((regs->cr1 & STM32F4_I2C_CR1_PE) != 0) |
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| 62 | { |
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| 63 | return RTEMS_RESOURCE_IN_USE; |
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| 64 | } |
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| 65 | |
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| 66 | /* Configure clock control register and rise time register */ |
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| 67 | ccr = regs->ccr; |
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| 68 | trise = regs->trise; |
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| 69 | |
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| 70 | if(br <= 100000) |
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| 71 | { |
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| 72 | uint32_t ccr_val = pclk / (2 * br); |
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| 73 | /* according to datasheet, the rise time for standard mode is 1us -> 1MHz */ |
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| 74 | uint32_t trise_val = pclk / 1000000 + 1; |
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| 75 | trise = STM32F4_I2C_TRISE_SET(trise, trise_val); |
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| 76 | |
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| 77 | if(ccr_val > STM32F4_I2C_CCR_CCR_MAX) |
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| 78 | { |
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| 79 | return RTEMS_INVALID_NUMBER; |
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| 80 | } |
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| 81 | |
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| 82 | /* standard mode */ |
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| 83 | ccr &= ~STM32F4_I2C_CCR_FS; |
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| 84 | ccr = STM32F4_I2C_CCR_CCR_SET(ccr, ccr_val); |
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| 85 | } |
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| 86 | else |
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| 87 | { |
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| 88 | /* FIXME: Implement speeds 100kHz < f <= 400kHz (fast mode) */ |
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| 89 | return RTEMS_NOT_IMPLEMENTED; |
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| 90 | } |
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| 91 | |
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| 92 | regs->ccr = ccr; |
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| 93 | regs->trise = trise; |
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| 94 | |
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| 95 | return RTEMS_SUCCESSFUL; |
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| 96 | } |
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| 97 | |
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| 98 | static void stm32f4_i2c_handler(void *arg) |
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| 99 | { |
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| 100 | /* This handler implements the suggested read method from stm32f103xx |
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| 101 | * reference manual if the handler is not the one with the highest priority */ |
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| 102 | stm32f4_i2c_bus_entry *e = arg; |
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| 103 | volatile stm32f4_i2c *regs = e->regs; |
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| 104 | uint32_t sr1 = regs->sr1; |
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| 105 | uint8_t *data = e->data; |
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| 106 | uint8_t *last = e->last; |
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| 107 | bool read = e->read; |
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| 108 | bool wake_task = false; |
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| 109 | uint32_t cr1; |
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| 110 | |
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| 111 | if(sr1 & STM32F4_I2C_SR1_SB) { |
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| 112 | /* Start condition sent. */ |
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| 113 | regs->dr = e->addr_with_rw; |
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| 114 | } |
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| 115 | |
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| 116 | if(read) { |
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| 117 | size_t len = e->len; |
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| 118 | |
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| 119 | if(len == 1) { |
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| 120 | /* special case for one single byte */ |
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| 121 | if(sr1 & STM32F4_I2C_SR1_ADDR) { |
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| 122 | cr1 = regs->cr1; |
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| 123 | cr1 &= ~STM32F4_I2C_CR1_ACK; |
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| 124 | regs->cr1 = cr1; |
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| 125 | |
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| 126 | /* Read sr2 to clear flag */ |
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| 127 | regs->sr2; |
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| 128 | |
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| 129 | cr1 = regs->cr1; |
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| 130 | cr1 |= STM32F4_I2C_CR1_STOP; |
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| 131 | regs->cr1 = cr1; |
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| 132 | } else if(sr1 & STM32F4_I2C_SR1_RxNE) { |
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| 133 | *data = regs->dr; |
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| 134 | wake_task = true; |
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| 135 | } |
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| 136 | } else if (len == 2) { |
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| 137 | /* special case for two bytes */ |
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| 138 | if(sr1 & STM32F4_I2C_SR1_ADDR) { |
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| 139 | /* Read sr2 to clear flag */ |
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| 140 | regs->sr2; |
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| 141 | |
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| 142 | cr1 = regs->cr1; |
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| 143 | cr1 &= ~STM32F4_I2C_CR1_ACK; |
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| 144 | regs->cr1 = cr1; |
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| 145 | } else if(sr1 & STM32F4_I2C_SR1_BTF) { |
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| 146 | cr1 = regs->cr1; |
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| 147 | cr1 |= STM32F4_I2C_CR1_STOP; |
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| 148 | regs->cr1 = cr1; |
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| 149 | |
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| 150 | *data = regs->dr; |
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| 151 | ++data; |
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| 152 | *data = regs->dr; |
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| 153 | wake_task = true; |
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| 154 | } |
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| 155 | } else { |
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| 156 | /* more than two bytes */ |
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| 157 | if(sr1 & STM32F4_I2C_SR1_ADDR) { |
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| 158 | /* Read sr2 to clear flag */ |
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| 159 | regs->sr2; |
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| 160 | } else if(sr1 & STM32F4_I2C_SR1_BTF && data == last - 2) { |
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| 161 | cr1 = regs->cr1; |
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| 162 | cr1 &= ~STM32F4_I2C_CR1_ACK; |
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| 163 | regs->cr1 = cr1; |
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| 164 | |
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| 165 | *data = regs->dr; |
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| 166 | ++data; |
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| 167 | |
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| 168 | cr1 = regs->cr1; |
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| 169 | cr1 |= STM32F4_I2C_CR1_STOP; |
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| 170 | regs->cr1 = cr1; |
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| 171 | |
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| 172 | *data = regs->dr; |
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| 173 | ++data; |
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| 174 | } else if((sr1 & STM32F4_I2C_SR1_RxNE) && (data != last - 2)) { |
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| 175 | *data = regs->dr; |
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| 176 | |
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| 177 | if(data == last) { |
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| 178 | wake_task = true; |
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| 179 | } else { |
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| 180 | ++data; |
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| 181 | } |
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| 182 | } |
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| 183 | } |
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| 184 | } else /* write */ { |
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| 185 | if(sr1 & STM32F4_I2C_SR1_ADDR) { |
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| 186 | /* Address sent */ |
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| 187 | regs->sr2; |
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| 188 | } |
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| 189 | |
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| 190 | if((sr1 & (STM32F4_I2C_SR1_ADDR | STM32F4_I2C_SR1_TxE)) && (data <= last)) { |
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| 191 | regs->dr = *data; |
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| 192 | ++data; |
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| 193 | } else if(sr1 & STM32F4_I2C_SR1_BTF) { |
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| 194 | uint32_t cr1 = regs->cr1; |
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| 195 | cr1 |= STM32F4_I2C_CR1_STOP; |
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| 196 | regs->cr1 = cr1; |
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| 197 | wake_task = true; |
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| 198 | } |
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| 199 | } |
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| 200 | |
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| 201 | e->data = data; |
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| 202 | |
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| 203 | if(wake_task) { |
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| 204 | bsp_interrupt_vector_disable(e->vector); |
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| 205 | rtems_event_transient_send(e->task_id); |
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| 206 | } |
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| 207 | } |
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| 208 | |
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| 209 | static rtems_status_code i2c_wait_done(stm32f4_i2c_bus_entry *e) |
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| 210 | { |
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| 211 | bsp_interrupt_vector_enable(e->vector); |
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| 212 | e->task_id = rtems_task_self(); |
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| 213 | return rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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| 214 | } |
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| 215 | |
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| 216 | rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e) |
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| 217 | { |
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| 218 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 219 | volatile stm32f4_i2c *regs = e->regs; |
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| 220 | stm32f4_rcc_index rcc_index = i2c_get_rcc_index(e); |
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| 221 | uint32_t pclk = i2c_get_pclk(e); |
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| 222 | uint32_t cr1 = 0; |
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| 223 | uint32_t cr2 = 0; |
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| 224 | |
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| 225 | assert(pclk >= 2000000); |
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| 226 | |
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| 227 | /* Create mutex */ |
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| 228 | sc = rtems_semaphore_create ( |
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| 229 | rtems_build_name ('I', '2', 'C', '1' + e->index), |
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| 230 | 0, |
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| 231 | RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, |
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| 232 | 0, |
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| 233 | &e->mutex |
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| 234 | ); |
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| 235 | RTEMS_CHECK_SC(sc, "create mutex"); |
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| 236 | |
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| 237 | /* Install interrupt handler and disable this vector */ |
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| 238 | sc = rtems_interrupt_handler_install( |
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| 239 | e->vector, |
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| 240 | "I2C", |
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| 241 | RTEMS_INTERRUPT_UNIQUE, |
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| 242 | stm32f4_i2c_handler, |
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| 243 | e |
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| 244 | ); |
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| 245 | RTEMS_CHECK_SC(sc, "install interrupt handler"); |
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| 246 | bsp_interrupt_vector_disable(e->vector); |
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| 247 | |
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| 248 | /* Enable module clock */ |
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| 249 | stm32f4_rcc_set_clock(rcc_index, true); |
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| 250 | |
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| 251 | /* Setup initial bit rate */ |
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[0255beaf] | 252 | sc = stm32f4_i2c_set_bitrate(e, STM32F4_I2C_INITIAL_BITRATE); |
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[c918737e] | 253 | RTEMS_CHECK_SC(sc, "set bitrate"); |
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| 254 | |
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| 255 | /* Set config registers */ |
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| 256 | cr2 = regs->cr2; |
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| 257 | cr2 = STM32F4_I2C_CR2_FREQ_SET(cr2, pclk / 1000000); |
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| 258 | cr2 |= STM32F4_I2C_CR2_ITEVTEN; |
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| 259 | cr2 |= STM32F4_I2C_CR2_ITBUFEN; |
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| 260 | regs->cr2 = cr2; |
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| 261 | |
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| 262 | cr1 = regs->cr1; |
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| 263 | cr1 |= STM32F4_I2C_CR1_PE; |
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| 264 | regs->cr1 = cr1; |
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| 265 | |
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| 266 | return RTEMS_SUCCESSFUL; |
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| 267 | } |
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| 268 | |
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| 269 | rtems_status_code stm32f4_i2c_process_message( |
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| 270 | stm32f4_i2c_bus_entry *e, |
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| 271 | stm32f4_i2c_message *msg |
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| 272 | ) |
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| 273 | { |
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| 274 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 275 | rtems_status_code sc_return = RTEMS_SUCCESSFUL; |
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| 276 | volatile stm32f4_i2c *regs = e->regs; |
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| 277 | uint16_t max_7_bit_address = (1 << 7) - 1; |
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| 278 | uint32_t cr1 = regs->cr1; |
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| 279 | |
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| 280 | if(msg->addr > max_7_bit_address) { |
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| 281 | return RTEMS_NOT_IMPLEMENTED; |
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| 282 | } |
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| 283 | |
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| 284 | if(msg->len == 0) { |
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| 285 | return RTEMS_INVALID_SIZE; |
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| 286 | } |
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| 287 | |
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| 288 | sc = rtems_semaphore_obtain(e->mutex, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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| 289 | RTEMS_CHECK_SC(sc, "obtaining mutex"); |
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| 290 | |
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| 291 | e->data = msg->buf; |
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| 292 | e->last = msg->buf + msg->len - 1; |
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| 293 | e->len = msg->len; |
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| 294 | |
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| 295 | e->addr_with_rw = msg->addr << 1; |
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| 296 | if(msg->read) { |
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| 297 | e->addr_with_rw |= I2C_RW_BIT; |
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| 298 | } |
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| 299 | e->read = msg->read; |
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| 300 | |
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| 301 | /* Check if no stop is active. */ |
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| 302 | if(cr1 & STM32F4_I2C_CR1_STOP) { |
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| 303 | return RTEMS_IO_ERROR; |
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| 304 | } |
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| 305 | |
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| 306 | /* Start */ |
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| 307 | cr1 = regs->cr1; |
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| 308 | if(e->len == 2) { |
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| 309 | cr1 |= STM32F4_I2C_CR1_POS; |
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| 310 | } else { |
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| 311 | cr1 &= ~STM32F4_I2C_CR1_POS; |
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| 312 | } |
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| 313 | cr1 |= STM32F4_I2C_CR1_ACK; |
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| 314 | cr1 |= STM32F4_I2C_CR1_START; |
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| 315 | regs->cr1 = cr1; |
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| 316 | |
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| 317 | /* Wait for end of message */ |
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| 318 | sc = i2c_wait_done(e); |
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| 319 | |
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| 320 | if(sc != RTEMS_SUCCESSFUL) { |
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| 321 | sc_return = sc; |
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| 322 | } |
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| 323 | |
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| 324 | sc = rtems_semaphore_release(e->mutex); |
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| 325 | RTEMS_CHECK_SC(sc, "releasing mutex"); |
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| 326 | |
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| 327 | return sc_return; |
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| 328 | } |
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| 329 | |
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