[1781f59f] | 1 | /* |
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| 2 | * GP32 Memory Map |
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| 3 | * |
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| 4 | * Copyright (c) 2004 by Cogent Computer Systems |
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| 5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * |
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| 10 | * http://www.rtems.com/license/LICENSE. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | #include <rtems.h> |
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| 15 | #include <libcpu/mmu.h> |
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| 16 | |
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| 17 | /* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than |
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| 18 | * that, you'll have TLB lookups, which could hurt performance. |
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| 19 | */ |
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| 20 | mmu_sect_map_t mem_map[] = { |
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| 21 | /* <phys addr> <virt addr> <size> <flags> */ |
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| 22 | {0x30000000, 0x00000000, 1, MMU_CACHE_NONE}, /* SDRAM for vectors */ |
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| 23 | {0x30000000, 0x30000000, 32, MMU_CACHE_WTHROUGH}, /* SDRAM W cache */ |
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| 24 | {0x32000000, 0x32000000, 32, MMU_CACHE_NONE}, /* SDRAM W/O cache */ |
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| 25 | {0x48000000, 0x48000000, 256, MMU_CACHE_NONE}, /* Internals Regs - */ |
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| 26 | {0x50000000, 0x50000000, 256, MMU_CACHE_NONE}, /* Internal Regs - */ |
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| 27 | {0x00000000, 0x00000000, 0, 0} /* The end */ |
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| 28 | }; |
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