source: rtems/c/src/lib/libbsp/arm/smdk2410/start/start.S @ 2433a8ab

Last change on this file since 2433a8ab was 2433a8ab, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 7, 2017 at 1:32:42 PM

arm: Remove legacy execption support

  • Property mode set to 100644
File size: 5.4 KB
Line 
1/*
2 * SMDK2410 startup code
3 */
4
5/*
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#include <bsp/linker-symbols.h>
12
13/* Some standard definitions...*/
14.equ PSR_MODE_USR,       0x10
15.equ PSR_MODE_FIQ,       0x11
16.equ PSR_MODE_IRQ,       0x12
17.equ PSR_MODE_SVC,       0x13
18.equ PSR_MODE_ABT,       0x17
19.equ PSR_MODE_UNDEF,     0x1B
20.equ PSR_MODE_SYS,       0x1F
21
22.equ PSR_I,              0x80
23.equ PSR_F,              0x40
24.equ PSR_T,              0x20
25
26.text
27.globl  _start
28_start:
29        b               _start2
30
31@---------------------------------------------------------------------------------
32@ AXF addresses
33@---------------------------------------------------------------------------------
34        .word   bsp_section_text_begin
35        .word   bsp_section_rodata_end
36        .word   bsp_section_data_begin
37        .word   bsp_section_bss_end
38        .word   bsp_section_bss_begin
39        .word   bsp_section_bss_end
40
41@---------------------------------------------------------------------------------
42@ GamePark magic sequence
43@---------------------------------------------------------------------------------
44        .word   0x44450011
45        .word   0x44450011
46        .word   0x01234567
47        .word   0x12345678
48        .word   0x23456789
49        .word   0x34567890
50        .word   0x45678901
51        .word   0x56789012
52        .word   0x23456789
53        .word   0x34567890
54        .word   0x45678901
55        .word   0x56789012
56        .word   0x23456789
57        .word   0x34567890
58        .word   0x45678901
59        .word   0x56789012
60
61@---------------------------------------------------------------------------------
62_start2:
63@---------------------------------------------------------------------------------
64
65        /*
66         * Since I don't plan to return to the bootloader,
67         * I don't have to save the registers.
68         *
69         * I'll just set the CPSR for SVC mode, interrupts
70         * off, and ARM instructions.
71         */
72        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
73        msr     cpsr, r0
74
75        /* --- Initialize stack pointer registers */
76        /* Enter IRQ mode and set up the IRQ stack pointer */
77        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
78        msr     cpsr, r0
79        ldr     r1, =bsp_stack_irq_size
80        ldr     sp, =bsp_stack_irq_begin
81        add     sp, sp, r1
82
83        /* Enter FIQ mode and set up the FIQ stack pointer */
84        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
85        msr     cpsr, r0
86        ldr     r1, =bsp_stack_fiq_size
87        ldr     sp, =bsp_stack_fiq_begin
88        add     sp, sp, r1
89
90        /* Enter ABT mode and set up the ABT stack pointer */
91        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
92        msr     cpsr, r0
93        ldr     r1, =bsp_stack_abt_size
94        ldr     sp, =bsp_stack_abt_begin
95        add     sp, sp, r1
96
97        /* Set up the SVC stack pointer last and stay in SVC mode */
98        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
99        msr     cpsr, r0
100        ldr     r1, =bsp_stack_svc_size
101        ldr     sp, =bsp_stack_svc_begin
102        add     sp, sp, r1
103        sub     sp, sp, #0x64
104
105
106        /* disable mmu, I and D caches*/
107        nop
108        nop
109        mrc p15, 0, r0, c1, c0, 0
110        bic r0, r0, #0x01
111        bic r0, r0, #0x04
112        bic r0, r0, #0x01000
113        mcr p15, 0, r0, c1, c0, 0
114        nop
115        nop
116
117        /* clean data cache */
118        mov   r1,#0x00
119Loop1:
120        mov   r2,#0x00
121Loop2:
122        mov r3, r2, lsl#26
123        orr r3, r3, r1, lsl#5
124        mcr p15, 0, r3, c7, c14, 2
125        add r2, r2, #0x01
126        cmp r2, #64
127        bne Loop2
128        add r1, r1, #0x01
129        cmp r1, #8
130        bne Loop1
131
132
133        /*
134         * Initialize the MMU. After we return, the MMU is enabled,
135         * and memory may be remapped. I hope we don't remap this
136         * memory away.
137         */
138        ldr     r0, =mem_map
139        bl      mmu_init
140
141        /*
142         * Initialize the exception vectors. This includes the
143         * exceptions vectors (0x00000000-0x0000001c), and the
144         * pointers to the exception handlers (0x00000020-0x0000003c).
145         */
146        mov     r0, #0
147        adr     r1, vector_block
148        ldmia   r1!, {r2-r9}
149        stmia   r0!, {r2-r9}
150        ldmia   r1!, {r2-r9}
151        stmia   r0!, {r2-r9}
152
153        /* Now we are prepared to start the BSP's C code */
154        mov     r0, #0
155        bl      boot_card
156
157        /*
158         * Theoretically, we could return to what started us up,
159         * but we'd have to have saved the registers and stacks.
160         * Instead, we'll just reset.
161         */
162        bl      bsp_reset
163
164        /* We shouldn't get here. If we do, hang */
165_hang:  b       _hang
166
167
168/*
169 * This is the exception vector table and the pointers to
170 * the functions that handle the exceptions. It's a total
171 * of 16 words (64 bytes)
172 */
173vector_block:
174        ldr    pc, handler_addr_reset
175        ldr    pc, handler_addr_undef
176        ldr    pc, handler_addr_swi
177        ldr    pc, handler_addr_prefetch
178        ldr    pc, handler_addr_abort
179        nop
180        ldr    pc, handler_addr_irq
181        ldr    pc, handler_addr_fiq
182
183handler_addr_reset:
184        .word  bsp_reset
185
186handler_addr_undef:
187        .word  _ARMV4_Exception_undef_default
188
189handler_addr_swi:
190        .word  _ARMV4_Exception_swi_default
191
192handler_addr_prefetch:
193        .word  _ARMV4_Exception_pref_abort_default
194
195handler_addr_abort:
196        .word  _ARMV4_Exception_data_abort_default
197
198handler_addr_reserved:
199        .word  _ARMV4_Exception_reserved_default
200
201handler_addr_irq:
202        .word  _ARMV4_Exception_interrupt
203
204handler_addr_fiq:
205        .word  _ARMV4_Exception_fiq_default
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