source: rtems/c/src/lib/libbsp/arm/smdk2410/include/bsp.h @ 02f4c11

Last change on this file since 02f4c11 was 02f4c11, checked in by Joel Sherrill <joel@…>, on Mar 30, 2016 at 7:04:22 PM

arm/smdk2410/include/bsp.h: Do not include <rtems/iosupp.h>

  • Property mode set to 100644
File size: 1.5 KB
Line 
1/**
2 * @file
3 * @ingroup arm_smdk2410
4 * @brief Global BSP definitons.
5 */
6
7/*
8 *  Copyright (c) Canon Research France SA.]
9 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef LIBBSP_ARM_SMDK2410_BSP_H
17#define LIBBSP_ARM_SMDK2410_BSP_H
18
19#include <bspopts.h>
20#include <bsp/default-initial-extension.h>
21
22#include <rtems.h>
23#include <s3c24xx.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#define BSP_FEATURE_IRQ_EXTENSION
30
31/**
32 * @brief functions to get the differents s3c2400 clks
33 * @{
34 */
35
36uint32_t get_FCLK(void);
37uint32_t get_HCLK(void);
38uint32_t get_PCLK(void);
39uint32_t get_UCLK(void);
40
41/** @} */
42
43/* What is the input clock freq in hertz? */
44/** @brief 12 MHz oscillator */
45#define BSP_OSC_FREQ  12000000
46/** @brief FCLK=133Mhz */
47#define M_MDIV 81
48#define M_PDIV 2
49#define M_SDIV 1
50/** @brief HCLK=FCLK/2, PCLK=FCLK/2 */
51#define M_CLKDIVN 2
52/** @brief enable refresh */
53#define REFEN   0x1
54/** @brief CBR(CAS before RAS)/auto refresh */
55#define TREFMD  0x0
56/** @brief 2 clk */
57#define Trp     0x0
58/** @brief 7 clk */
59#define Trc     0x3
60/** @brief 3 clk */
61#define Tchr    0x2
62
63/**
64 * @brief This BSP provides its own IDLE thread to override the RTEMS one.
65 *
66 *  So we prototype it and define the constant confdefs.h expects
67 *  to configure a BSP specific one.
68 */
69void *bsp_idle_thread(uintptr_t ignored);
70
71/** @} */
72
73#define BSP_IDLE_TASK_BODY bsp_idle_thread
74
75#ifdef __cplusplus
76}
77#endif
78
79#endif /* _BSP_H */
80
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