4.115
Last change
on this file since 991fdb33 was
991fdb33,
checked in by Martin Galvan <martin.galvan@…>, on 02/26/15 at 20:31:27
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ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATION
This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and
three hooks for BSP-specific register init code to arm/shared/start.S.
Said hooks are bsp_start_init_registers_core (intended for initializing
the ARM core registers), bsp_start_init_registers_banked_fiq (for the
FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU
registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in
a BSP's configure.ac (so that it appears in its bspopts.h).
This patch also adds the register init code required by the TMS570.
We've tested it with the tms570ls3137_hdk.cfg config and it works fine.
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Property mode set to
100644
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File size:
2.0 KB
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Rev | Line | |
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[991fdb33] | 1 | /** |
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| 2 | * @file bsp-start-init-registers.S |
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| 3 | * |
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| 4 | * @brief ARM register initialization routines. |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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| 8 | * Copyright (c) 2015 Taller Technologies. All rights reserved. |
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| 9 | * |
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| 10 | * @author Martin Galvan <martin.galvan@tallertechnologies.com> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.org/license/LICENSE. |
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| 15 | */ |
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| 16 | |
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| 17 | /* |
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| 18 | * These routines initialize the core and VFP registers of ARM CPUs. |
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| 19 | * This is necessary for boards that operate in a 1oo1D fashion, |
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| 20 | * such as the TMS570. |
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| 21 | */ |
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| 22 | |
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| 23 | #include <rtems/asm.h> |
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| 24 | |
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| 25 | .section .text |
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| 26 | .syntax unified |
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| 27 | .cpu cortex-r4 |
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| 28 | .arm |
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| 29 | |
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| 30 | /* Initialization of the ARM core registers. */ |
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| 31 | FUNCTION_ENTRY(bsp_start_init_registers_core) |
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| 32 | mov r0, #0 |
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| 33 | mov r1, #0 |
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| 34 | mov r2, #0 |
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| 35 | mov r3, #0 |
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| 36 | mov r4, #0 |
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| 37 | mov r5, #0 |
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| 38 | mov r6, #0 |
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| 39 | mov r7, #0 |
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| 40 | mov r8, #0 |
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| 41 | mov r9, #0 |
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| 42 | mov r10, #0 |
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| 43 | mov r11, #0 |
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| 44 | mov r12, #0 |
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| 45 | mov r13, #0 |
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| 46 | |
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| 47 | bx lr |
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| 48 | FUNCTION_END(bsp_start_init_registers_core) |
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| 49 | |
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| 50 | /* Initialization of the FIQ mode banked registers. */ |
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| 51 | FUNCTION_ENTRY(bsp_start_init_registers_banked_fiq) |
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| 52 | mov r8, #0 |
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| 53 | mov r9, #0 |
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| 54 | mov r10, #0 |
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| 55 | mov r11, #0 |
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| 56 | mov r12, #0 |
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| 57 | |
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| 58 | bx lr |
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| 59 | FUNCTION_END(bsp_start_init_registers_banked_fiq) |
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| 60 | |
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| 61 | #ifdef ARM_MULTILIB_VFP |
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| 62 | |
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| 63 | /* Initialization of the FPU registers. */ |
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| 64 | FUNCTION_ENTRY(bsp_start_init_registers_vfp) |
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| 65 | mov r0, #0 |
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| 66 | vmov d0, r0, r0 |
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| 67 | vmov d1, r0, r0 |
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| 68 | vmov d2, r0, r0 |
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| 69 | vmov d3, r0, r0 |
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| 70 | vmov d4, r0, r0 |
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| 71 | vmov d5, r0, r0 |
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| 72 | vmov d6, r0, r0 |
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| 73 | vmov d7, r0, r0 |
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| 74 | vmov d8, r0, r0 |
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| 75 | vmov d9, r0, r0 |
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| 76 | vmov d10, r0, r0 |
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| 77 | vmov d11, r0, r0 |
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| 78 | vmov d12, r0, r0 |
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| 79 | vmov d13, r0, r0 |
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| 80 | vmov d14, r0, r0 |
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| 81 | vmov d15, r0, r0 |
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| 82 | |
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| 83 | #ifdef ARM_MULTILIB_VFP_D32 |
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| 84 | vmov d16, r0, r0 |
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| 85 | vmov d17, r0, r0 |
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| 86 | vmov d18, r0, r0 |
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| 87 | vmov d19, r0, r0 |
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| 88 | vmov d20, r0, r0 |
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| 89 | vmov d21, r0, r0 |
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| 90 | vmov d22, r0, r0 |
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| 91 | vmov d23, r0, r0 |
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| 92 | vmov d24, r0, r0 |
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| 93 | vmov d25, r0, r0 |
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| 94 | vmov d26, r0, r0 |
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| 95 | vmov d27, r0, r0 |
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| 96 | vmov d28, r0, r0 |
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| 97 | vmov d29, r0, r0 |
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| 98 | vmov d30, r0, r0 |
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| 99 | vmov d31, r0, r0 |
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| 100 | #endif /* ARM_MULTILIB_VFP_D32 */ |
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| 101 | |
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| 102 | bx lr |
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| 103 | FUNCTION_END(bsp_start_init_registers_vfp) |
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| 104 | |
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| 105 | #endif /* ARM_MULTILIB_VFP */ |
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