source: rtems/c/src/lib/libbsp/arm/shared/start/start.S @ a45dfa14

4.115
Last change on this file since a45dfa14 was 8ae37323, checked in by Sebastian Huber <sebastian.huber@…>, on 08/10/14 at 16:36:30

arm: Add support for FPv4-SP floating point unit

This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief Boot and system start code.
5 */
6
7/*
8 * Copyright (c) 2008-2014 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#include <rtems/asm.h>
22#include <rtems/system.h>       
23#include <rtems/score/cpu.h>
24       
25#include <bspopts.h>
26#include <bsp/irq.h>
27#include <bsp/linker-symbols.h>
28
29        /* External symbols */
30        .extern bsp_reset
31        .extern boot_card
32        .extern bsp_start_hook_0
33        .extern bsp_start_hook_1
34        .extern bsp_stack_irq_end
35        .extern bsp_stack_fiq_end
36        .extern bsp_stack_abt_end
37        .extern bsp_stack_und_end
38        .extern bsp_stack_svc_end
39#ifdef RTEMS_SMP
40        .extern bsp_stack_all_size
41#endif
42        .extern _ARMV4_Exception_undef_default
43        .extern _ARMV4_Exception_swi_default
44        .extern _ARMV4_Exception_data_abort_default
45        .extern _ARMV4_Exception_pref_abort_default
46        .extern _ARMV4_Exception_reserved_default
47        .extern _ARMV4_Exception_interrupt
48        .extern _ARMV4_Exception_fiq_default
49        .extern _ARMV7M_Exception_default
50
51        /* Global symbols */
52        .globl  _start
53        .globl  bsp_start_vector_table_begin
54        .globl  bsp_start_vector_table_end
55        .globl  bsp_start_vector_table_size
56        .globl  bsp_vector_table_size
57
58        .section        ".bsp_start_text", "ax"
59
60#if defined(ARM_MULTILIB_ARCH_V4)
61
62        .arm
63
64/*
65 * This is the exception vector table and the pointers to the default
66 * exceptions handlers.
67 */
68
69bsp_start_vector_table_begin:
70
71        ldr     pc, handler_addr_reset
72        ldr     pc, handler_addr_undef
73        ldr     pc, handler_addr_swi
74        ldr     pc, handler_addr_prefetch
75        ldr     pc, handler_addr_abort
76
77        /* Program signature checked by boot loader */
78        .word   0xb8a06f58
79
80        ldr     pc, handler_addr_irq
81        ldr     pc, handler_addr_fiq
82
83handler_addr_reset:
84
85#ifdef BSP_START_RESET_VECTOR
86        .word   BSP_START_RESET_VECTOR
87#else
88        .word   _start
89#endif
90
91handler_addr_undef:
92
93        .word   _ARMV4_Exception_undef_default
94
95handler_addr_swi:
96
97        .word   _ARMV4_Exception_swi_default
98
99handler_addr_prefetch:
100
101        .word   _ARMV4_Exception_pref_abort_default
102
103handler_addr_abort:
104
105        .word   _ARMV4_Exception_data_abort_default
106
107handler_addr_reserved:
108
109        .word   _ARMV4_Exception_reserved_default
110
111handler_addr_irq:
112
113        .word   _ARMV4_Exception_interrupt
114
115handler_addr_fiq:
116
117        .word   _ARMV4_Exception_fiq_default
118
119bsp_start_vector_table_end:
120
121/* Start entry */
122
123_start:
124
125        /*
126         * We do not save the context since we do not return to the boot
127         * loader.
128         */
129
130#ifdef RTEMS_SMP
131        /* Read MPIDR */
132        mrc     p15, 0, r0, c0, c0, 5
133
134        /* Calculate stack offset */
135        and     r0, #0xff
136        ldr     r1, =bsp_stack_all_size
137        mul     r1, r0
138#endif
139
140        /*
141         * Set SVC mode, disable interrupts and enable ARM instructions.
142         */
143        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
144        msr     cpsr, r0
145
146        /* Initialize stack pointer registers for the various modes */
147
148        /* Enter IRQ mode and set up the IRQ stack pointer */
149        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
150        msr     cpsr, r0
151        ldr     sp, =bsp_stack_irq_end
152#ifdef RTEMS_SMP
153        add     sp, r1
154#endif
155
156        /* Enter FIQ mode and set up the FIQ stack pointer */
157        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
158        msr     cpsr, r0
159        ldr     sp, =bsp_stack_fiq_end
160#ifdef RTEMS_SMP
161        add     sp, r1
162#endif
163
164        /* Enter ABT mode and set up the ABT stack pointer */
165        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
166        msr     cpsr, r0
167        ldr     sp, =bsp_stack_abt_end
168#ifdef RTEMS_SMP
169        add     sp, r1
170#endif
171
172        /* Enter UND mode and set up the UND stack pointer */
173        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
174        msr     cpsr, r0
175        ldr     sp, =bsp_stack_und_end
176#ifdef RTEMS_SMP
177        add     sp, r1
178#endif
179
180        /* Enter SVC mode and set up the SVC stack pointer */
181        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
182        msr     cpsr, r0
183        ldr     sp, =bsp_stack_svc_end
184#ifdef RTEMS_SMP
185        add     sp, r1
186#endif
187
188        /* Stay in SVC mode */
189
190#ifdef ARM_MULTILIB_VFP_D32
191        /* Read CPACR */
192        mrc p15, 0, r0, c1, c0, 2
193
194        /* Enable CP10 and CP11 */
195        orr r0, r0, #(1 << 20)
196        orr r0, r0, #(1 << 22)
197
198        /* Clear ASEDIS and D32DIS */
199        bic r0, r0, #(3 << 30)
200
201        /* Write CPACR */
202        mcr p15, 0, r0, c1, c0, 2
203        isb
204
205        /* Enable FPU */
206        mov r0, #(1 << 30)
207        vmsr FPEXC, r0
208#endif
209
210        /*
211         * Branch to start hook 0.
212         *
213         * The previous code and parts of the start hook 0 may run with an
214         * address offset.  This implies that only branches relative to the
215         * program counter are allowed.  After the start hook 0 it is assumed
216         * that the code can run at its intended position.  Thus the link
217         * register will be loaded with the absolute address.  In THUMB mode
218         * the start hook 0 must be within a 2kByte range due to the branch
219         * instruction limitation.
220         */
221
222        ldr     lr, =bsp_start_hook_0_done
223#ifdef __thumb__
224        orr     lr, #1
225#endif
226
227        SWITCH_FROM_ARM_TO_THUMB        r0
228
229        b       bsp_start_hook_0
230
231bsp_start_hook_0_done:
232
233        SWITCH_FROM_THUMB_TO_ARM
234
235        /*
236         * Initialize the exception vectors.  This includes the exceptions
237         * vectors and the pointers to the default exception handlers.
238         */
239
240        ldr     r0, =bsp_vector_table_begin
241        adr     r1, bsp_start_vector_table_begin
242        cmp     r0, r1
243        beq     bsp_vector_table_copy_done
244        ldmia   r1!, {r2-r9}
245        stmia   r0!, {r2-r9}
246        ldmia   r1!, {r2-r9}
247        stmia   r0!, {r2-r9}
248
249bsp_vector_table_copy_done:
250
251        SWITCH_FROM_ARM_TO_THUMB        r0
252
253        /* Branch to start hook 1 */
254        bl      bsp_start_hook_1
255
256        /* Branch to boot card */
257        mov     r0, #0
258        bl      boot_card
259
260twiddle:
261
262        /* Branch to reset function */
263        bl      bsp_reset
264
265        b       twiddle
266
267#elif defined(ARM_MULTILIB_ARCH_V7M)
268
269#include <rtems/score/armv7m.h>
270
271        .syntax unified
272
273        .extern bsp_stack_main_end
274
275        .thumb
276
277bsp_start_vector_table_begin:
278
279        .word   bsp_stack_main_end
280        .word   _start /* Reset */
281        .word   _ARMV7M_Exception_default /* NMI */
282        .word   _ARMV7M_Exception_default /* Hard Fault */
283        .word   _ARMV7M_Exception_default /* MPU Fault */
284        .word   _ARMV7M_Exception_default /* Bus Fault */
285        .word   _ARMV7M_Exception_default /* Usage Fault */
286        .word   _ARMV7M_Exception_default /* Reserved */
287        .word   _ARMV7M_Exception_default /* Reserved */
288        .word   _ARMV7M_Exception_default /* Reserved */
289        .word   _ARMV7M_Exception_default /* Reserved */
290        .word   _ARMV7M_Exception_default /* SVC */
291        .word   _ARMV7M_Exception_default /* Debug Monitor */
292        .word   _ARMV7M_Exception_default /* Reserved */
293        .word   _ARMV7M_Exception_default /* PendSV */
294        .word   _ARMV7M_Exception_default /* SysTick */
295        .rept   BSP_INTERRUPT_VECTOR_MAX + 1
296        .word   _ARMV7M_Exception_default /* IRQ */
297        .endr
298
299bsp_start_vector_table_end:
300
301        .thumb_func
302
303_start:
304
305#ifdef ARM_MULTILIB_VFP
306        /*
307         * Enable CP10 and CP11 coprocessors for privileged and user mode in
308         * CPACR (bits 20-23).  Ensure that write to register completes.
309         */
310        ldr     r0, =ARMV7M_CPACR
311        ldr     r1, [r0]
312        orr     r1, r1, #(0xf << 20)
313        str     r1, [r0]
314        dsb
315        isb
316#endif
317
318        ldr     sp, =bsp_stack_main_end
319        ldr     lr, =bsp_start_hook_0_done + 1
320        b       bsp_start_hook_0
321
322bsp_start_hook_0_done:
323
324        bl      bsp_start_hook_1
325        movs    r0, #0
326        bl      boot_card
327
328twiddle:
329
330        bl      bsp_reset
331        b       twiddle
332
333#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
334
335        .set    bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
336        .set    bsp_vector_table_size, bsp_start_vector_table_size
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