source: rtems/c/src/lib/libbsp/arm/shared/start/start.S @ 9dcc683

4.115
Last change on this file since 9dcc683 was 9ce65803, checked in by Sebastian Huber <sebastian.huber@…>, on 05/02/13 at 11:37:30

bsps/arm: Copy vector table only if necessary
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/**
2 * @file
3 *
4 * @brief Boot and system start code.
5 */
6
7/*
8 * Copyright (c) 2008-2013 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.com/license/LICENSE.
19 */
20
21#include <rtems/asm.h>
22#include <rtems/system.h>       
23#include <rtems/score/cpu.h>
24       
25#include <bspopts.h>
26#include <bsp/irq.h>
27#include <bsp/linker-symbols.h>
28
29        /* External symbols */
30        .extern bsp_reset
31        .extern boot_card
32        .extern bsp_start_hook_0
33        .extern bsp_start_hook_1
34        .extern _ARMV4_Exception_undef_default
35        .extern _ARMV4_Exception_swi_default
36        .extern _ARMV4_Exception_data_abort_default
37        .extern _ARMV4_Exception_pref_abort_default
38        .extern _ARMV4_Exception_reserved_default
39        .extern _ARMV4_Exception_irq_default
40        .extern _ARMV4_Exception_fiq_default
41        .extern _ARMV7M_Exception_default
42
43        /* Global symbols */
44        .globl  _start
45        .globl  bsp_start_vector_table_begin
46        .globl  bsp_start_vector_table_end
47        .globl  bsp_start_vector_table_size
48        .globl  bsp_vector_table_size
49
50        .section        ".bsp_start_text", "ax"
51
52#if defined(ARM_MULTILIB_ARCH_V4)
53
54        .arm
55
56/*
57 * This is the exception vector table and the pointers to the default
58 * exceptions handlers.
59 */
60
61bsp_start_vector_table_begin:
62
63        ldr     pc, handler_addr_reset
64        ldr     pc, handler_addr_undef
65        ldr     pc, handler_addr_swi
66        ldr     pc, handler_addr_prefetch
67        ldr     pc, handler_addr_abort
68
69        /* Program signature checked by boot loader */
70        .word   0xb8a06f58
71
72        ldr     pc, handler_addr_irq
73        ldr     pc, handler_addr_fiq
74
75handler_addr_reset:
76
77#ifdef BSP_START_RESET_VECTOR
78        .word   BSP_START_RESET_VECTOR
79#else
80        .word   _start
81#endif
82
83handler_addr_undef:
84
85        .word   _ARMV4_Exception_undef_default
86
87handler_addr_swi:
88
89        .word   _ARMV4_Exception_swi_default
90
91handler_addr_prefetch:
92
93        .word   _ARMV4_Exception_data_abort_default
94
95handler_addr_abort:
96
97        .word   _ARMV4_Exception_pref_abort_default
98
99handler_addr_reserved:
100
101        .word   _ARMV4_Exception_reserved_default
102
103handler_addr_irq:
104
105        .word   _ARMV4_Exception_irq_default
106
107handler_addr_fiq:
108
109        .word   _ARMV4_Exception_fiq_default
110
111bsp_start_vector_table_end:
112
113/* Start entry */
114
115_start:
116
117        /*
118         * We do not save the context since we do not return to the boot
119         * loader.
120         */
121
122        /*
123         * Set SVC mode, disable interrupts and enable ARM instructions.
124         */
125        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
126        msr     cpsr, r0
127
128        /* Initialize stack pointer registers for the various modes */
129
130        /* Enter IRQ mode and set up the IRQ stack pointer */
131        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
132        msr     cpsr, r0
133        ldr     sp, =bsp_stack_irq_end
134
135        /* Enter FIQ mode and set up the FIQ stack pointer */
136        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
137        msr     cpsr, r0
138        ldr     sp, =bsp_stack_fiq_end
139
140        /* Enter ABT mode and set up the ABT stack pointer */
141        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
142        msr     cpsr, r0
143        ldr     sp, =bsp_stack_abt_end
144
145        /* Enter UND mode and set up the UND stack pointer */
146        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
147        msr     cpsr, r0
148        ldr     sp, =bsp_stack_und_end
149
150        /* Enter SVC mode and set up the SVC stack pointer */
151        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
152        msr     cpsr, r0
153        ldr     sp, =bsp_stack_svc_end
154
155        /* Stay in SVC mode */
156
157        /*
158         * Branch to start hook 0.
159         *
160         * The previous code and parts of the start hook 0 may run with an
161         * address offset.  This implies that only branches relative to the
162         * program counter are allowed.  After the start hook 0 it is assumed
163         * that the code can run at its intended position.  Thus the link
164         * register will be loaded with the absolute address.  In THUMB mode
165         * the start hook 0 must be within a 2kByte range due to the branch
166         * instruction limitation.
167         */
168
169        ldr     lr, =bsp_start_hook_0_done
170#ifdef __thumb__
171        orr     lr, #1
172#endif
173
174        SWITCH_FROM_ARM_TO_THUMB        r0
175
176        b       bsp_start_hook_0
177
178bsp_start_hook_0_done:
179
180        SWITCH_FROM_THUMB_TO_ARM
181
182        /*
183         * Initialize the exception vectors.  This includes the exceptions
184         * vectors and the pointers to the default exception handlers.
185         */
186
187        ldr     r0, =bsp_vector_table_begin
188        adr     r1, bsp_start_vector_table_begin
189        cmp     r0, r1
190        beq     bsp_vector_table_copy_done
191        ldmia   r1!, {r2-r9}
192        stmia   r0!, {r2-r9}
193        ldmia   r1!, {r2-r9}
194        stmia   r0!, {r2-r9}
195
196bsp_vector_table_copy_done:
197
198        SWITCH_FROM_ARM_TO_THUMB        r0
199
200        /* Branch to start hook 1 */
201        bl      bsp_start_hook_1
202
203        /* Branch to boot card */
204        mov     r0, #0
205        bl      boot_card
206
207twiddle:
208
209        /* Branch to reset function */
210        bl      bsp_reset
211
212        b       twiddle
213
214#elif defined(ARM_MULTILIB_ARCH_V7M)
215
216        .syntax unified
217
218        .extern bsp_stack_main_end
219
220        .thumb
221
222bsp_start_vector_table_begin:
223
224        .word   bsp_stack_main_end
225        .word   _start /* Reset */
226        .word   _ARMV7M_Exception_default /* NMI */
227        .word   _ARMV7M_Exception_default /* Hard Fault */
228        .word   _ARMV7M_Exception_default /* MPU Fault */
229        .word   _ARMV7M_Exception_default /* Bus Fault */
230        .word   _ARMV7M_Exception_default /* Usage Fault */
231        .word   _ARMV7M_Exception_default /* Reserved */
232        .word   _ARMV7M_Exception_default /* Reserved */
233        .word   _ARMV7M_Exception_default /* Reserved */
234        .word   _ARMV7M_Exception_default /* Reserved */
235        .word   _ARMV7M_Exception_default /* SVC */
236        .word   _ARMV7M_Exception_default /* Debug Monitor */
237        .word   _ARMV7M_Exception_default /* Reserved */
238        .word   _ARMV7M_Exception_default /* PendSV */
239        .word   _ARMV7M_Exception_default /* SysTick */
240        .rept   BSP_INTERRUPT_VECTOR_MAX + 1
241        .word   _ARMV7M_Exception_default /* IRQ */
242        .endr
243
244bsp_start_vector_table_end:
245
246        .thumb_func
247
248_start:
249
250        ldr     sp, =bsp_stack_main_end
251        ldr     lr, =bsp_start_hook_0_done + 1
252        b       bsp_start_hook_0
253
254bsp_start_hook_0_done:
255
256        bl      bsp_start_hook_1
257        movs    r0, #0
258        bl      boot_card
259
260twiddle:
261
262        bl      bsp_reset
263        b       twiddle
264
265#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
266
267        .set    bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
268        .set    bsp_vector_table_size, bsp_start_vector_table_size
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