source: rtems/c/src/lib/libbsp/arm/shared/start/start.S @ 991fdb33

4.115
Last change on this file since 991fdb33 was 991fdb33, checked in by Martin Galvan <martin.galvan@…>, on Feb 26, 2015 at 8:31:27 PM

ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATION

This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and
three hooks for BSP-specific register init code to arm/shared/start.S.
Said hooks are bsp_start_init_registers_core (intended for initializing
the ARM core registers), bsp_start_init_registers_banked_fiq (for the
FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU
registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in
a BSP's configure.ac (so that it appears in its bspopts.h).

This patch also adds the register init code required by the TMS570.
We've tested it with the tms570ls3137_hdk.cfg config and it works fine.

  • Property mode set to 100644
File size: 7.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief Boot and system start code.
5 */
6
7/*
8 * Copyright (c) 2008-2014 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#include <rtems/asm.h>
22#include <rtems/system.h>       
23#include <rtems/score/cpu.h>
24       
25#include <bspopts.h>
26#include <bsp/irq.h>
27#include <bsp/linker-symbols.h>
28
29        /* External symbols */
30        .extern bsp_reset
31        .extern boot_card
32        .extern bsp_start_hook_0
33        .extern bsp_start_hook_1
34        .extern bsp_stack_irq_end
35        .extern bsp_stack_fiq_end
36        .extern bsp_stack_abt_end
37        .extern bsp_stack_und_end
38        .extern bsp_stack_svc_end
39#ifdef RTEMS_SMP
40        .extern bsp_stack_all_size
41#endif
42        .extern _ARMV4_Exception_undef_default
43        .extern _ARMV4_Exception_swi_default
44        .extern _ARMV4_Exception_data_abort_default
45        .extern _ARMV4_Exception_pref_abort_default
46        .extern _ARMV4_Exception_reserved_default
47        .extern _ARMV4_Exception_interrupt
48        .extern _ARMV4_Exception_fiq_default
49        .extern _ARMV7M_Exception_default
50
51#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
52        .extern bsp_start_init_registers_core
53        .extern bsp_start_init_registers_banked_fiq
54        .extern bsp_start_init_registers_vfp
55#endif
56
57        /* Global symbols */
58        .globl  _start
59        .globl  bsp_start_vector_table_begin
60        .globl  bsp_start_vector_table_end
61        .globl  bsp_start_vector_table_size
62        .globl  bsp_vector_table_size
63
64        .section        ".bsp_start_text", "ax"
65
66#if defined(ARM_MULTILIB_ARCH_V4)
67
68        .arm
69
70/*
71 * This is the exception vector table and the pointers to the default
72 * exceptions handlers.
73 */
74
75bsp_start_vector_table_begin:
76
77        ldr     pc, handler_addr_reset
78        ldr     pc, handler_addr_undef
79        ldr     pc, handler_addr_swi
80        ldr     pc, handler_addr_prefetch
81        ldr     pc, handler_addr_abort
82
83        /* Program signature checked by boot loader */
84        .word   0xb8a06f58
85
86        ldr     pc, handler_addr_irq
87        ldr     pc, handler_addr_fiq
88
89handler_addr_reset:
90
91#ifdef BSP_START_RESET_VECTOR
92        .word   BSP_START_RESET_VECTOR
93#else
94        .word   _start
95#endif
96
97handler_addr_undef:
98
99        .word   _ARMV4_Exception_undef_default
100
101handler_addr_swi:
102
103        .word   _ARMV4_Exception_swi_default
104
105handler_addr_prefetch:
106
107        .word   _ARMV4_Exception_pref_abort_default
108
109handler_addr_abort:
110
111        .word   _ARMV4_Exception_data_abort_default
112
113handler_addr_reserved:
114
115        .word   _ARMV4_Exception_reserved_default
116
117handler_addr_irq:
118
119        .word   _ARMV4_Exception_interrupt
120
121handler_addr_fiq:
122
123        .word   _ARMV4_Exception_fiq_default
124
125bsp_start_vector_table_end:
126
127/* Start entry */
128
129_start:
130
131        /*
132         * We do not save the context since we do not return to the boot
133         * loader.
134         */
135
136#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
137        bl bsp_start_init_registers_core
138#endif
139
140#ifdef RTEMS_SMP
141        /* Read MPIDR */
142        mrc     p15, 0, r0, c0, c0, 5
143
144        /* Calculate stack offset */
145        and     r0, #0xff
146        ldr     r1, =bsp_stack_all_size
147        mul     r1, r0
148#endif
149
150        /*
151         * Set SVC mode, disable interrupts and enable ARM instructions.
152         */
153        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
154        msr     cpsr, r0
155
156        /* Initialize stack pointer registers for the various modes */
157
158        /* Enter IRQ mode and set up the IRQ stack pointer */
159        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
160        msr     cpsr, r0
161        ldr     sp, =bsp_stack_irq_end
162#ifdef RTEMS_SMP
163        add     sp, r1
164#endif
165
166        /* Enter FIQ mode and set up the FIQ stack pointer */
167        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
168        msr     cpsr, r0
169        ldr     sp, =bsp_stack_fiq_end
170#ifdef RTEMS_SMP
171        add     sp, r1
172#endif
173
174#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
175        bl bsp_start_init_registers_banked_fiq
176#endif
177
178        /* Enter ABT mode and set up the ABT stack pointer */
179        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
180        msr     cpsr, r0
181        ldr     sp, =bsp_stack_abt_end
182#ifdef RTEMS_SMP
183        add     sp, r1
184#endif
185
186        /* Enter UND mode and set up the UND stack pointer */
187        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
188        msr     cpsr, r0
189        ldr     sp, =bsp_stack_und_end
190#ifdef RTEMS_SMP
191        add     sp, r1
192#endif
193
194        /* Enter SVC mode and set up the SVC stack pointer */
195        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
196        msr     cpsr, r0
197        ldr     sp, =bsp_stack_svc_end
198#ifdef RTEMS_SMP
199        add     sp, r1
200#endif
201
202        /* Stay in SVC mode */
203
204#ifdef ARM_MULTILIB_VFP
205        /* Read CPACR */
206        mrc p15, 0, r0, c1, c0, 2
207
208        /* Enable CP10 and CP11 */
209        orr r0, r0, #(1 << 20)
210        orr r0, r0, #(1 << 22)
211
212        /*
213         * Clear ASEDIS and D32DIS.  Writes to D32DIS are ignored for VFP-D16.
214         */
215        bic r0, r0, #(3 << 30)
216
217        /* Write CPACR */
218        mcr p15, 0, r0, c1, c0, 2
219        isb
220
221        /* Enable FPU */
222        mov r0, #(1 << 30)
223        vmsr FPEXC, r0
224
225#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
226        bl bsp_start_init_registers_vfp
227#endif
228
229#endif /* ARM_MULTILIB_VFP */
230
231        /*
232         * Branch to start hook 0.
233         *
234         * The previous code and parts of the start hook 0 may run with an
235         * address offset.  This implies that only branches relative to the
236         * program counter are allowed.  After the start hook 0 it is assumed
237         * that the code can run at its intended position.  Thus the link
238         * register will be loaded with the absolute address.  In THUMB mode
239         * the start hook 0 must be within a 2kByte range due to the branch
240         * instruction limitation.
241         */
242
243        ldr     lr, =bsp_start_hook_0_done
244#ifdef __thumb__
245        orr     lr, #1
246#endif
247
248        SWITCH_FROM_ARM_TO_THUMB        r0
249
250        b       bsp_start_hook_0
251
252bsp_start_hook_0_done:
253
254        SWITCH_FROM_THUMB_TO_ARM
255
256        /*
257         * Initialize the exception vectors.  This includes the exceptions
258         * vectors and the pointers to the default exception handlers.
259         */
260
261        ldr     r0, =bsp_vector_table_begin
262        adr     r1, bsp_start_vector_table_begin
263        cmp     r0, r1
264        beq     bsp_vector_table_copy_done
265        ldmia   r1!, {r2-r9}
266        stmia   r0!, {r2-r9}
267        ldmia   r1!, {r2-r9}
268        stmia   r0!, {r2-r9}
269
270bsp_vector_table_copy_done:
271
272        SWITCH_FROM_ARM_TO_THUMB        r0
273
274        /* Branch to start hook 1 */
275        bl      bsp_start_hook_1
276
277        /* Branch to boot card */
278        mov     r0, #0
279        bl      boot_card
280
281twiddle:
282
283        /* Branch to reset function */
284        bl      bsp_reset
285
286        b       twiddle
287
288#elif defined(ARM_MULTILIB_ARCH_V7M)
289
290#include <rtems/score/armv7m.h>
291
292        .syntax unified
293
294        .extern bsp_stack_main_end
295
296        .thumb
297
298bsp_start_vector_table_begin:
299
300        .word   bsp_stack_main_end
301        .word   _start /* Reset */
302        .word   _ARMV7M_Exception_default /* NMI */
303        .word   _ARMV7M_Exception_default /* Hard Fault */
304        .word   _ARMV7M_Exception_default /* MPU Fault */
305        .word   _ARMV7M_Exception_default /* Bus Fault */
306        .word   _ARMV7M_Exception_default /* Usage Fault */
307        .word   _ARMV7M_Exception_default /* Reserved */
308        .word   _ARMV7M_Exception_default /* Reserved */
309        .word   _ARMV7M_Exception_default /* Reserved */
310        .word   _ARMV7M_Exception_default /* Reserved */
311        .word   _ARMV7M_Exception_default /* SVC */
312        .word   _ARMV7M_Exception_default /* Debug Monitor */
313        .word   _ARMV7M_Exception_default /* Reserved */
314        .word   _ARMV7M_Exception_default /* PendSV */
315        .word   _ARMV7M_Exception_default /* SysTick */
316        .rept   BSP_INTERRUPT_VECTOR_MAX + 1
317        .word   _ARMV7M_Exception_default /* IRQ */
318        .endr
319
320bsp_start_vector_table_end:
321
322        .thumb_func
323
324_start:
325
326#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
327        bl bsp_start_init_registers_core
328#endif
329
330#ifdef ARM_MULTILIB_VFP
331        /*
332         * Enable CP10 and CP11 coprocessors for privileged and user mode in
333         * CPACR (bits 20-23).  Ensure that write to register completes.
334         */
335        ldr     r0, =ARMV7M_CPACR
336        ldr     r1, [r0]
337        orr     r1, r1, #(0xf << 20)
338        str     r1, [r0]
339        dsb
340        isb
341
342#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
343        bl bsp_start_init_registers_vfp
344#endif
345
346#endif /* ARM_MULTILIB_VFP */
347
348        ldr     sp, =bsp_stack_main_end
349        ldr     lr, =bsp_start_hook_0_done + 1
350        b       bsp_start_hook_0
351
352bsp_start_hook_0_done:
353
354        bl      bsp_start_hook_1
355        movs    r0, #0
356        bl      boot_card
357
358twiddle:
359
360        bl      bsp_reset
361        b       twiddle
362
363#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
364
365        .set    bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
366        .set    bsp_vector_table_size, bsp_start_vector_table_size
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