1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Boot and system start code. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2008 |
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9 | * Embedded Brains GmbH |
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10 | * Obere Lagerstr. 30 |
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11 | * D-82178 Puchheim |
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12 | * Germany |
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13 | * rtems@embedded-brains.de |
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14 | * |
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15 | * The license and distribution terms for this file may be found in the file |
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16 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <rtems/asm.h> |
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20 | #include <rtems/score/cpu.h> |
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21 | |
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22 | #include <bspopts.h> |
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23 | #include <bsp/linker-symbols.h> |
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24 | |
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25 | /* External symbols */ |
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26 | |
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27 | .extern bsp_reset |
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28 | .extern boot_card |
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29 | .extern bsp_start_hook_0 |
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30 | .extern bsp_start_hook_1 |
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31 | |
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32 | /* Global symbols */ |
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33 | |
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34 | .globl start |
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35 | .globl bsp_start_memcpy |
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36 | |
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37 | .section ".bsp_start", "ax" |
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38 | |
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39 | .arm |
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40 | |
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41 | /* |
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42 | * This is the exception vector table and the pointers to the default |
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43 | * exceptions handlers. |
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44 | */ |
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45 | |
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46 | vector_block: |
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47 | |
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48 | ldr pc, handler_addr_reset |
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49 | ldr pc, handler_addr_undef |
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50 | ldr pc, handler_addr_swi |
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51 | ldr pc, handler_addr_prefetch |
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52 | ldr pc, handler_addr_abort |
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53 | |
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54 | /* Program signature checked by boot loader */ |
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55 | .word 0xb8a06f58 |
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56 | |
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57 | ldr pc, handler_addr_irq |
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58 | ldr pc, handler_addr_fiq |
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59 | |
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60 | handler_addr_reset: |
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61 | |
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62 | #ifdef BSP_START_RESET_VECTOR |
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63 | .word BSP_START_RESET_VECTOR |
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64 | #else |
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65 | .word start |
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66 | #endif |
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67 | |
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68 | handler_addr_undef: |
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69 | |
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70 | .word twiddle |
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71 | |
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72 | handler_addr_swi: |
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73 | |
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74 | .word twiddle |
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75 | |
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76 | handler_addr_prefetch: |
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77 | |
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78 | .word twiddle |
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79 | |
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80 | handler_addr_abort: |
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81 | |
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82 | .word twiddle |
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83 | |
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84 | handler_addr_reserved: |
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85 | |
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86 | .word twiddle |
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87 | |
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88 | handler_addr_irq: |
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89 | |
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90 | .word twiddle |
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91 | |
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92 | handler_addr_fiq: |
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93 | |
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94 | .word twiddle |
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95 | |
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96 | /* Start entry */ |
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97 | |
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98 | start: |
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99 | |
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100 | /* |
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101 | * We do not save the context since we do not return to the boot |
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102 | * loader. |
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103 | */ |
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104 | |
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105 | /* |
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106 | * Set SVC mode, disable interrupts and enable ARM instructions. |
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107 | */ |
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108 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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109 | msr cpsr, r0 |
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110 | |
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111 | /* Initialize stack pointer registers for the various modes */ |
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112 | |
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113 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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114 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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115 | msr cpsr, r0 |
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116 | ldr sp, =bsp_stack_irq_end |
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117 | |
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118 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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119 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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120 | msr cpsr, r0 |
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121 | ldr sp, =bsp_stack_fiq_end |
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122 | |
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123 | /* Enter ABT mode and set up the ABT stack pointer */ |
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124 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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125 | msr cpsr, r0 |
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126 | ldr sp, =bsp_stack_abt_end |
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127 | |
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128 | /* Enter UND mode and set up the UND stack pointer */ |
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129 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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130 | msr cpsr, r0 |
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131 | ldr sp, =bsp_stack_und_end |
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132 | |
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133 | /* Enter SVC mode and set up the SVC stack pointer */ |
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134 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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135 | msr cpsr, r0 |
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136 | ldr sp, =bsp_stack_svc_end |
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137 | |
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138 | /* Stay in SVC mode */ |
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139 | |
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140 | /* |
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141 | * Branch to start hook 0. |
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142 | * |
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143 | * The previous code and parts of the start hook 0 may run with an |
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144 | * address offset. This implies that only branches relative to the |
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145 | * program counter are allowed. After the start hook 0 it is assumed |
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146 | * that the code can run at its intended position. Thus the link |
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147 | * register will be loaded with the absolute address. In THUMB mode |
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148 | * the start hook 0 must be within a 2kByte range due to the branch |
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149 | * instruction limitation. |
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150 | */ |
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151 | |
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152 | ldr lr, =bsp_start_hook_0_done |
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153 | #ifdef __thumb__ |
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154 | orr lr, #1 |
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155 | #endif |
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156 | |
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157 | SWITCH_FROM_ARM_TO_THUMB r0 |
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158 | |
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159 | b bsp_start_hook_0 |
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160 | |
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161 | bsp_start_hook_0_done: |
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162 | |
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163 | SWITCH_FROM_THUMB_TO_ARM |
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164 | |
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165 | /* |
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166 | * Initialize the exception vectors. This includes the exceptions |
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167 | * vectors and the pointers to the default exception handlers. |
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168 | */ |
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169 | |
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170 | ldr r0, =bsp_section_vector_begin |
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171 | adr r1, vector_block |
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172 | ldmia r1!, {r2-r9} |
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173 | stmia r0!, {r2-r9} |
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174 | ldmia r1!, {r2-r9} |
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175 | stmia r0!, {r2-r9} |
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176 | |
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177 | SWITCH_FROM_ARM_TO_THUMB r0 |
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178 | |
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179 | /* Branch to start hook 1 */ |
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180 | bl bsp_start_hook_1 |
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181 | |
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182 | /* Branch to boot card */ |
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183 | mov r0, #0 |
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184 | bl boot_card |
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185 | |
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186 | /* Branch to reset function */ |
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187 | bl bsp_reset |
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188 | |
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189 | SWITCH_FROM_THUMB_TO_ARM |
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190 | |
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191 | /* Spin forever */ |
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192 | |
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193 | twiddle: |
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194 | |
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195 | b twiddle |
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196 | |
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197 | DEFINE_FUNCTION_ARM(bsp_start_memcpy) |
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198 | |
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199 | /* Return if dest == src */ |
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200 | cmp r0, r1 |
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201 | bxeq lr |
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202 | |
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203 | /* Return if length is zero */ |
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204 | mov r3, #0 |
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205 | cmp r3, r2 |
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206 | bxeq lr |
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207 | |
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208 | /* Save non-volatile registers */ |
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209 | push {r4-r8, lr} |
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210 | |
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211 | /* Copy worker routine to stack */ |
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212 | adr ip, bsp_start_memcpy_begin |
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213 | ldm ip, {r3-r8} |
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214 | push {r3-r8} |
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215 | |
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216 | /* Execute worker routine */ |
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217 | mov r3, #0 |
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218 | mov ip, sp |
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219 | mov lr, pc |
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220 | bx ip |
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221 | |
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222 | /* Restore stack and non-volatile registers */ |
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223 | add sp, sp, #24 |
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224 | pop {r4-r8, lr} |
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225 | |
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226 | /* Return */ |
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227 | bx lr |
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228 | |
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229 | bsp_start_memcpy_begin: |
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230 | |
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231 | /* Worker routine */ |
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232 | ldr ip, [r1, r3] |
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233 | str ip, [r0, r3] |
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234 | add r3, r3, #4 |
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235 | cmp r3, r2 |
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236 | bcc bsp_start_memcpy_begin |
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237 | bx lr |
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