source: rtems/c/src/lib/libbsp/arm/shared/start/start.S @ 7a6f8d0

4.104.11
Last change on this file since 7a6f8d0 was 7a6f8d0, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 9, 2010 at 12:22:57 PM

added dma header
added thumb support to start.S
updated documentation

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief Boot and system start code.
5 */
6
7/*
8 * Copyright (c) 2008
9 * Embedded Brains GmbH
10 * Obere Lagerstr. 30
11 * D-82178 Puchheim
12 * Germany
13 * rtems@embedded-brains.de
14 *
15 * The license and distribution terms for this file may be found in the file
16 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
17 */
18
19#include <rtems/asm.h>
20#include <rtems/score/cpu.h>
21
22#include <bspopts.h>
23#include <bsp/linker-symbols.h>
24
25/* External symbols */
26
27.extern bsp_reset
28.extern boot_card
29.extern bsp_start_hook_0
30.extern bsp_start_hook_1
31
32/* Global symbols */
33
34.globl start
35.globl bsp_start_memcpy
36
37.section ".bsp_start", "ax"
38
39.arm
40
41/*
42 * This is the exception vector table and the pointers to the default
43 * exceptions handlers.
44 */
45
46vector_block:
47
48        ldr     pc, handler_addr_reset
49        ldr     pc, handler_addr_undef
50        ldr     pc, handler_addr_swi
51        ldr     pc, handler_addr_prefetch
52        ldr     pc, handler_addr_abort
53
54        /* Program signature checked by boot loader */
55        .word   0xb8a06f58
56
57        ldr     pc, handler_addr_irq
58        ldr     pc, handler_addr_fiq
59
60handler_addr_reset:
61
62#ifdef BSP_START_RESET_VECTOR
63        .word   BSP_START_RESET_VECTOR
64#else
65        .word   start
66#endif
67
68handler_addr_undef:
69
70        .word   twiddle
71
72handler_addr_swi:
73
74        .word   twiddle
75
76handler_addr_prefetch:
77
78        .word   twiddle
79
80handler_addr_abort:
81
82        .word   twiddle
83
84handler_addr_reserved:
85
86        .word   twiddle
87
88handler_addr_irq:
89
90        .word   twiddle
91
92handler_addr_fiq:
93
94        .word   twiddle
95
96/* Start entry */
97
98start:
99
100        /*
101         * We do not save the context since we do not return to the boot
102         * loader.
103         */
104
105        /*
106         * Set SVC mode, disable interrupts and enable ARM instructions.
107         */
108        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
109        msr     cpsr, r0
110
111        /* Initialize stack pointer registers for the various modes */
112
113        /* Enter IRQ mode and set up the IRQ stack pointer */
114        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
115        msr     cpsr, r0
116        ldr     sp, =bsp_stack_irq_end
117
118        /* Enter FIQ mode and set up the FIQ stack pointer */
119        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
120        msr     cpsr, r0
121        ldr     sp, =bsp_stack_fiq_end
122
123        /* Enter ABT mode and set up the ABT stack pointer */
124        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
125        msr     cpsr, r0
126        ldr     sp, =bsp_stack_abt_end
127
128        /* Enter UND mode and set up the UND stack pointer */
129        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
130        msr     cpsr, r0
131        ldr     sp, =bsp_stack_und_end
132
133        /* Enter SVC mode and set up the SVC stack pointer */
134        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
135        msr     cpsr, r0
136        ldr     sp, =bsp_stack_svc_end
137
138        /* Stay in SVC mode */
139
140        /*
141         * Branch to start hook 0.
142         *
143         * The previous code and parts of the start hook 0 may run with an
144         * address offset.  This implies that only branches relative to the
145         * program counter are allowed.  After the start hook 0 it is assumed
146         * that the code can run at its intended position.  Thus the link
147         * register will be loaded with the absolute address.  In THUMB mode
148         * the start hook 0 must be within a 2kByte range due to the branch
149         * instruction limitation.
150         */
151
152        ldr     lr, =bsp_start_hook_0_done
153#ifdef __thumb__
154        orr     lr, #1
155#endif
156
157        SWITCH_FROM_ARM_TO_THUMB        r0
158
159        b       bsp_start_hook_0
160
161bsp_start_hook_0_done:
162
163        SWITCH_FROM_THUMB_TO_ARM
164
165        /*
166         * Initialize the exception vectors.  This includes the exceptions
167         * vectors and the pointers to the default exception handlers.
168         */
169
170        ldr     r0, =bsp_section_vector_begin
171        adr     r1, vector_block
172        ldmia   r1!, {r2-r9}
173        stmia   r0!, {r2-r9}
174        ldmia   r1!, {r2-r9}
175        stmia   r0!, {r2-r9}
176
177        SWITCH_FROM_ARM_TO_THUMB        r0
178
179        /* Branch to start hook 1 */
180        bl      bsp_start_hook_1
181
182        /* Branch to boot card */
183        mov     r0, #0
184        bl      boot_card
185
186        /* Branch to reset function */
187        bl      bsp_reset
188
189        SWITCH_FROM_THUMB_TO_ARM
190
191        /* Spin forever */
192
193twiddle:
194
195        b       twiddle
196
197DEFINE_FUNCTION_ARM(bsp_start_memcpy)
198
199        /* Return if dest == src */
200        cmp     r0, r1
201        bxeq    lr
202
203        /* Return if length is zero */
204        mov     r3, #0
205        cmp     r3, r2
206        bxeq    lr
207
208        /* Save non-volatile registers */
209        push    {r4-r8, lr}
210
211        /* Copy worker routine to stack */
212        adr     ip, bsp_start_memcpy_begin
213        ldm     ip, {r3-r8}
214        push    {r3-r8}
215
216        /* Execute worker routine */
217        mov     r3, #0
218        mov     ip, sp
219        mov     lr, pc
220        bx      ip
221
222        /* Restore stack and non-volatile registers */
223        add     sp, sp, #24
224        pop     {r4-r8, lr}
225
226        /* Return */
227        bx      lr
228
229bsp_start_memcpy_begin:
230
231        /* Worker routine */
232        ldr     ip, [r1, r3]
233        str     ip, [r0, r3]
234        add     r3, r3, #4
235        cmp     r3, r2
236        bcc     bsp_start_memcpy_begin
237        bx      lr
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